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ARM: EXYNOS: use 'exynos4-sdhci' as device name for sdhci controllers
With the addition of platform specific driver data in the sdhci driver for EXYNOS4 and EXYNOS5, the device name of sdhci controllers on EXYNOS4 and EXYNOS5 are changed accordingly. Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org> [kgene.kim@samsung.com: re-worked on top of v3.4-rc2] Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
This commit is contained in:
Thomas Abraham
Kukjin Kim
parent
e816b57a33
commit
8482c81c77
@ -497,25 +497,25 @@ static struct clk exynos4_init_clocks_off[] = {
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.ctrlbit = (1 << 3),
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}, {
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.name = "hsmmc",
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.devname = "s3c-sdhci.0",
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.devname = "exynos4-sdhci.0",
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.parent = &exynos4_clk_aclk_133.clk,
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.enable = exynos4_clk_ip_fsys_ctrl,
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.ctrlbit = (1 << 5),
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}, {
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.name = "hsmmc",
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.devname = "s3c-sdhci.1",
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.devname = "exynos4-sdhci.1",
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.parent = &exynos4_clk_aclk_133.clk,
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.enable = exynos4_clk_ip_fsys_ctrl,
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.ctrlbit = (1 << 6),
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}, {
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.name = "hsmmc",
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.devname = "s3c-sdhci.2",
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.devname = "exynos4-sdhci.2",
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.parent = &exynos4_clk_aclk_133.clk,
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.enable = exynos4_clk_ip_fsys_ctrl,
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.ctrlbit = (1 << 7),
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}, {
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.name = "hsmmc",
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.devname = "s3c-sdhci.3",
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.devname = "exynos4-sdhci.3",
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.parent = &exynos4_clk_aclk_133.clk,
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.enable = exynos4_clk_ip_fsys_ctrl,
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.ctrlbit = (1 << 8),
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@ -1202,7 +1202,7 @@ static struct clksrc_clk exynos4_clk_sclk_uart3 = {
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static struct clksrc_clk exynos4_clk_sclk_mmc0 = {
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.clk = {
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.name = "sclk_mmc",
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.devname = "s3c-sdhci.0",
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.devname = "exynos4-sdhci.0",
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.parent = &exynos4_clk_dout_mmc0.clk,
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.enable = exynos4_clksrc_mask_fsys_ctrl,
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.ctrlbit = (1 << 0),
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@ -1213,7 +1213,7 @@ static struct clksrc_clk exynos4_clk_sclk_mmc0 = {
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static struct clksrc_clk exynos4_clk_sclk_mmc1 = {
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.clk = {
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.name = "sclk_mmc",
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.devname = "s3c-sdhci.1",
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.devname = "exynos4-sdhci.1",
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.parent = &exynos4_clk_dout_mmc1.clk,
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.enable = exynos4_clksrc_mask_fsys_ctrl,
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.ctrlbit = (1 << 4),
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@ -1224,7 +1224,7 @@ static struct clksrc_clk exynos4_clk_sclk_mmc1 = {
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static struct clksrc_clk exynos4_clk_sclk_mmc2 = {
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.clk = {
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.name = "sclk_mmc",
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.devname = "s3c-sdhci.2",
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.devname = "exynos4-sdhci.2",
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.parent = &exynos4_clk_dout_mmc2.clk,
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.enable = exynos4_clksrc_mask_fsys_ctrl,
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.ctrlbit = (1 << 8),
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@ -1235,7 +1235,7 @@ static struct clksrc_clk exynos4_clk_sclk_mmc2 = {
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static struct clksrc_clk exynos4_clk_sclk_mmc3 = {
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.clk = {
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.name = "sclk_mmc",
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.devname = "s3c-sdhci.3",
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.devname = "exynos4-sdhci.3",
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.parent = &exynos4_clk_dout_mmc3.clk,
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.enable = exynos4_clksrc_mask_fsys_ctrl,
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.ctrlbit = (1 << 12),
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@ -1340,10 +1340,10 @@ static struct clk_lookup exynos4_clk_lookup[] = {
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CLKDEV_INIT("exynos4210-uart.1", "clk_uart_baud0", &exynos4_clk_sclk_uart1.clk),
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CLKDEV_INIT("exynos4210-uart.2", "clk_uart_baud0", &exynos4_clk_sclk_uart2.clk),
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CLKDEV_INIT("exynos4210-uart.3", "clk_uart_baud0", &exynos4_clk_sclk_uart3.clk),
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CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &exynos4_clk_sclk_mmc0.clk),
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CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &exynos4_clk_sclk_mmc1.clk),
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CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &exynos4_clk_sclk_mmc2.clk),
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CLKDEV_INIT("s3c-sdhci.3", "mmc_busclk.2", &exynos4_clk_sclk_mmc3.clk),
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CLKDEV_INIT("exynos4-sdhci.0", "mmc_busclk.2", &exynos4_clk_sclk_mmc0.clk),
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CLKDEV_INIT("exynos4-sdhci.1", "mmc_busclk.2", &exynos4_clk_sclk_mmc1.clk),
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CLKDEV_INIT("exynos4-sdhci.2", "mmc_busclk.2", &exynos4_clk_sclk_mmc2.clk),
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CLKDEV_INIT("exynos4-sdhci.3", "mmc_busclk.2", &exynos4_clk_sclk_mmc3.clk),
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CLKDEV_INIT("exynos4-fb.0", "lcd", &exynos4_clk_fimd0),
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CLKDEV_INIT("dma-pl330.0", "apb_pclk", &exynos4_clk_pdma0),
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CLKDEV_INIT("dma-pl330.1", "apb_pclk", &exynos4_clk_pdma1),
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@ -455,25 +455,25 @@ static struct clk exynos5_init_clocks_off[] = {
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.ctrlbit = (1 << 20),
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}, {
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.name = "hsmmc",
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.devname = "s3c-sdhci.0",
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.devname = "exynos4-sdhci.0",
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.parent = &exynos5_clk_aclk_200.clk,
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.enable = exynos5_clk_ip_fsys_ctrl,
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.ctrlbit = (1 << 12),
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}, {
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.name = "hsmmc",
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.devname = "s3c-sdhci.1",
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.devname = "exynos4-sdhci.1",
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.parent = &exynos5_clk_aclk_200.clk,
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.enable = exynos5_clk_ip_fsys_ctrl,
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.ctrlbit = (1 << 13),
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}, {
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.name = "hsmmc",
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.devname = "s3c-sdhci.2",
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.devname = "exynos4-sdhci.2",
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.parent = &exynos5_clk_aclk_200.clk,
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.enable = exynos5_clk_ip_fsys_ctrl,
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.ctrlbit = (1 << 14),
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}, {
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.name = "hsmmc",
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.devname = "s3c-sdhci.3",
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.devname = "exynos4-sdhci.3",
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.parent = &exynos5_clk_aclk_200.clk,
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.enable = exynos5_clk_ip_fsys_ctrl,
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.ctrlbit = (1 << 15),
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@ -813,7 +813,7 @@ static struct clksrc_clk exynos5_clk_sclk_uart3 = {
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static struct clksrc_clk exynos5_clk_sclk_mmc0 = {
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.clk = {
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.name = "sclk_mmc",
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.devname = "s3c-sdhci.0",
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.devname = "exynos4-sdhci.0",
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.parent = &exynos5_clk_dout_mmc0.clk,
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.enable = exynos5_clksrc_mask_fsys_ctrl,
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.ctrlbit = (1 << 0),
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@ -824,7 +824,7 @@ static struct clksrc_clk exynos5_clk_sclk_mmc0 = {
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static struct clksrc_clk exynos5_clk_sclk_mmc1 = {
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.clk = {
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.name = "sclk_mmc",
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.devname = "s3c-sdhci.1",
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.devname = "exynos4-sdhci.1",
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.parent = &exynos5_clk_dout_mmc1.clk,
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.enable = exynos5_clksrc_mask_fsys_ctrl,
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.ctrlbit = (1 << 4),
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@ -835,7 +835,7 @@ static struct clksrc_clk exynos5_clk_sclk_mmc1 = {
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static struct clksrc_clk exynos5_clk_sclk_mmc2 = {
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.clk = {
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.name = "sclk_mmc",
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.devname = "s3c-sdhci.2",
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.devname = "exynos4-sdhci.2",
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.parent = &exynos5_clk_dout_mmc2.clk,
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.enable = exynos5_clksrc_mask_fsys_ctrl,
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.ctrlbit = (1 << 8),
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@ -846,7 +846,7 @@ static struct clksrc_clk exynos5_clk_sclk_mmc2 = {
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static struct clksrc_clk exynos5_clk_sclk_mmc3 = {
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.clk = {
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.name = "sclk_mmc",
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.devname = "s3c-sdhci.3",
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.devname = "exynos4-sdhci.3",
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.parent = &exynos5_clk_dout_mmc3.clk,
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.enable = exynos5_clksrc_mask_fsys_ctrl,
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.ctrlbit = (1 << 12),
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@ -990,10 +990,10 @@ static struct clk_lookup exynos5_clk_lookup[] = {
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CLKDEV_INIT("exynos4210-uart.1", "clk_uart_baud0", &exynos5_clk_sclk_uart1.clk),
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CLKDEV_INIT("exynos4210-uart.2", "clk_uart_baud0", &exynos5_clk_sclk_uart2.clk),
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CLKDEV_INIT("exynos4210-uart.3", "clk_uart_baud0", &exynos5_clk_sclk_uart3.clk),
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CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &exynos5_clk_sclk_mmc0.clk),
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CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &exynos5_clk_sclk_mmc1.clk),
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CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &exynos5_clk_sclk_mmc2.clk),
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CLKDEV_INIT("s3c-sdhci.3", "mmc_busclk.2", &exynos5_clk_sclk_mmc3.clk),
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CLKDEV_INIT("exynos4-sdhci.0", "mmc_busclk.2", &exynos5_clk_sclk_mmc0.clk),
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CLKDEV_INIT("exynos4-sdhci.1", "mmc_busclk.2", &exynos5_clk_sclk_mmc1.clk),
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CLKDEV_INIT("exynos4-sdhci.2", "mmc_busclk.2", &exynos5_clk_sclk_mmc2.clk),
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CLKDEV_INIT("exynos4-sdhci.3", "mmc_busclk.2", &exynos5_clk_sclk_mmc3.clk),
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CLKDEV_INIT("dma-pl330.0", "apb_pclk", &exynos5_clk_pdma0),
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CLKDEV_INIT("dma-pl330.1", "apb_pclk", &exynos5_clk_pdma1),
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CLKDEV_INIT("dma-pl330.2", "apb_pclk", &exynos5_clk_mdma1),
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@ -326,6 +326,11 @@ static void __init exynos4_map_io(void)
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s3c_fimc_setname(2, "exynos4-fimc");
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s3c_fimc_setname(3, "exynos4-fimc");
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s3c_sdhci_setname(0, "exynos4-sdhci");
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s3c_sdhci_setname(1, "exynos4-sdhci");
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s3c_sdhci_setname(2, "exynos4-sdhci");
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s3c_sdhci_setname(3, "exynos4-sdhci");
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/* The I2C bus controllers are directly compatible with s3c2440 */
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s3c_i2c0_setname("s3c2440-i2c");
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s3c_i2c1_setname("s3c2440-i2c");
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@ -344,6 +349,11 @@ static void __init exynos5_map_io(void)
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s3c_device_i2c0.resource[1].start = EXYNOS5_IRQ_IIC;
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s3c_device_i2c0.resource[1].end = EXYNOS5_IRQ_IIC;
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s3c_sdhci_setname(0, "exynos4-sdhci");
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s3c_sdhci_setname(1, "exynos4-sdhci");
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s3c_sdhci_setname(2, "exynos4-sdhci");
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s3c_sdhci_setname(3, "exynos4-sdhci");
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/* The I2C bus controllers are directly compatible with s3c2440 */
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s3c_i2c0_setname("s3c2440-i2c");
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s3c_i2c1_setname("s3c2440-i2c");
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@ -18,6 +18,8 @@
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#ifndef __PLAT_S3C_SDHCI_H
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#define __PLAT_S3C_SDHCI_H __FILE__
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#include <plat/devs.h>
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struct platform_device;
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struct mmc_host;
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struct mmc_card;
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@ -356,4 +358,30 @@ static inline void exynos4_default_sdhci3(void) { }
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#endif /* CONFIG_EXYNOS4_SETUP_SDHCI */
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static inline void s3c_sdhci_setname(int id, char *name)
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{
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switch (id) {
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#ifdef CONFIG_S3C_DEV_HSMMC
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case 0:
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s3c_device_hsmmc0.name = name;
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break;
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#endif
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#ifdef CONFIG_S3C_DEV_HSMMC1
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case 1:
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s3c_device_hsmmc1.name = name;
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break;
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#endif
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#ifdef CONFIG_S3C_DEV_HSMMC2
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case 2:
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s3c_device_hsmmc2.name = name;
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break;
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#endif
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#ifdef CONFIG_S3C_DEV_HSMMC3
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case 3:
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s3c_device_hsmmc3.name = name;
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break;
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#endif
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}
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}
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#endif /* __PLAT_S3C_SDHCI_H */
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