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drm/i915: Replace to_bpp_int() with fxp_q4_to_int()

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Replace the to_bpp_int() helper defined by the driver with the
equivalent fxp_q4_to_int() helper defined by DRM core.

v2: Rebase on the s/drm_x16/fxp_q4 change.

Acked-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240805150802.3568970-3-imre.deak@intel.com
This commit is contained in:
Imre Deak 2024-08-05 18:07:51 +03:00
parent 3196763851
commit 8466a14173
7 changed files with 19 additions and 21 deletions
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9
drivers/gpu/drm/i915/display/icl_dsi.c
View File

@ -27,6 +27,7 @@
#include <drm/display/drm_dsc_helper.h>
#include <drm/drm_atomic_helper.h>
#include <drm/drm_fixed.h>
#include <drm/drm_mipi_dsi.h>
#include "i915_reg.h"
@ -330,7 +331,7 @@ static int afe_clk(struct intel_encoder *encoder,
int bpp;
if (crtc_state->dsc.compression_enable)
bpp = to_bpp_int(crtc_state->dsc.compressed_bpp_x16);
bpp = fxp_q4_to_int(crtc_state->dsc.compressed_bpp_x16);
else
bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
@ -863,7 +864,7 @@ gen11_dsi_set_transcoder_timings(struct intel_encoder *encoder,
* compressed and non-compressed bpp.
*/
if (crtc_state->dsc.compression_enable) {
mul = to_bpp_int(crtc_state->dsc.compressed_bpp_x16);
mul = fxp_q4_to_int(crtc_state->dsc.compressed_bpp_x16);
div = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
}
@ -887,7 +888,7 @@ gen11_dsi_set_transcoder_timings(struct intel_encoder *encoder,
int bpp, line_time_us, byte_clk_period_ns;
if (crtc_state->dsc.compression_enable)
bpp = to_bpp_int(crtc_state->dsc.compressed_bpp_x16);
bpp = fxp_q4_to_int(crtc_state->dsc.compressed_bpp_x16);
else
bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
@ -1470,7 +1471,7 @@ static void gen11_dsi_get_timings(struct intel_encoder *encoder,
&pipe_config->hw.adjusted_mode;
if (pipe_config->dsc.compressed_bpp_x16) {
int div = to_bpp_int(pipe_config->dsc.compressed_bpp_x16);
int div = fxp_q4_to_int(pipe_config->dsc.compressed_bpp_x16);
int mul = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
adjusted_mode->crtc_htotal =

3
drivers/gpu/drm/i915/display/intel_display.c
View File

@ -39,6 +39,7 @@
#include <drm/drm_atomic_uapi.h>
#include <drm/drm_damage_helper.h>
#include <drm/drm_edid.h>
#include <drm/drm_fixed.h>
#include <drm/drm_fourcc.h>
#include <drm/drm_probe_helper.h>
#include <drm/drm_rect.h>
@ -4679,7 +4680,7 @@ intel_modeset_pipe_config(struct intel_atomic_state *state,
crtc_state->fec_enable = limits->force_fec_pipes & BIT(crtc->pipe);
crtc_state->max_link_bpp_x16 = limits->max_bpp_x16[crtc->pipe];
if (crtc_state->pipe_bpp > to_bpp_int(crtc_state->max_link_bpp_x16)) {
if (crtc_state->pipe_bpp > fxp_q4_to_int(crtc_state->max_link_bpp_x16)) {
drm_dbg_kms(&i915->drm,
"[CRTC:%d:%s] Link bpp limited to " BPP_X16_FMT "\n",
crtc->base.base.id, crtc->base.name,

7
drivers/gpu/drm/i915/display/intel_display_types.h
View File

@ -2200,18 +2200,13 @@ to_intel_frontbuffer(struct drm_framebuffer *fb)
return fb ? to_intel_framebuffer(fb)->frontbuffer : NULL;
}
static inline int to_bpp_int(int bpp_x16)
{
return bpp_x16 >> 4;
}
static inline int to_bpp_frac(int bpp_x16)
{
return bpp_x16 & 0xf;
}
#define BPP_X16_FMT "%d.%04d"
#define BPP_X16_ARGS(bpp_x16) to_bpp_int(bpp_x16), (to_bpp_frac(bpp_x16) * 625)
#define BPP_X16_ARGS(bpp_x16) fxp_q4_to_int(bpp_x16), (to_bpp_frac(bpp_x16) * 625)
static inline int to_bpp_int_roundup(int bpp_x16)
{

8
drivers/gpu/drm/i915/display/intel_dp.c
View File

@ -1694,8 +1694,8 @@ intel_dp_compute_link_config_wide(struct intel_dp *intel_dp,
int bpp, i, lane_count, clock = intel_dp_mode_clock(pipe_config, conn_state);
int mode_rate, link_rate, link_avail;
for (bpp = to_bpp_int(limits->link.max_bpp_x16);
bpp >= to_bpp_int(limits->link.min_bpp_x16);
for (bpp = fxp_q4_to_int(limits->link.max_bpp_x16);
bpp >= fxp_q4_to_int(limits->link.min_bpp_x16);
bpp -= 2 * 3) {
int link_bpp = intel_dp_output_bpp(pipe_config->output_format, bpp);
@ -2113,7 +2113,7 @@ static int dsc_compute_compressed_bpp(struct intel_dp *intel_dp,
adjusted_mode->hdisplay,
pipe_config->joiner_pipes);
dsc_max_bpp = min(dsc_max_bpp, dsc_joiner_max_bpp);
dsc_max_bpp = min(dsc_max_bpp, to_bpp_int(limits->link.max_bpp_x16));
dsc_max_bpp = min(dsc_max_bpp, fxp_q4_to_int(limits->link.max_bpp_x16));
if (DISPLAY_VER(i915) >= 13)
return xelpd_dsc_compute_link_config(intel_dp, connector, pipe_config, limits,
@ -2270,7 +2270,7 @@ static int intel_edp_dsc_compute_pipe_bpp(struct intel_dp *intel_dp,
pipe_config,
pipe_bpp / 3);
dsc_max_bpp = dsc_sink_max_bpp ? min(dsc_sink_max_bpp, dsc_src_max_bpp) : dsc_src_max_bpp;
dsc_max_bpp = min(dsc_max_bpp, to_bpp_int(limits->link.max_bpp_x16));
dsc_max_bpp = min(dsc_max_bpp, fxp_q4_to_int(limits->link.max_bpp_x16));
/* Compressed BPP should be less than the Input DSC bpp */
dsc_max_bpp = min(dsc_max_bpp, pipe_bpp - 1);

6
drivers/gpu/drm/i915/display/intel_dp_mst.c
View File

@ -309,8 +309,8 @@ static int intel_dp_mst_compute_link_config(struct intel_encoder *encoder,
* YUV420 is only half of the pipe bpp value.
*/
slots = intel_dp_mst_find_vcpi_slots_for_bpp(encoder, crtc_state,
to_bpp_int(limits->link.max_bpp_x16),
to_bpp_int(limits->link.min_bpp_x16),
fxp_q4_to_int(limits->link.max_bpp_x16),
fxp_q4_to_int(limits->link.min_bpp_x16),
limits,
conn_state, 2 * 3, false);
@ -375,7 +375,7 @@ static int intel_dp_dsc_mst_compute_link_config(struct intel_encoder *encoder,
crtc_state,
max_bpp / 3);
max_compressed_bpp = min(max_compressed_bpp,
to_bpp_int(limits->link.max_bpp_x16));
fxp_q4_to_int(limits->link.max_bpp_x16));
min_compressed_bpp = intel_dp_dsc_sink_min_compressed_bpp(crtc_state);
min_compressed_bpp = max(min_compressed_bpp,

2
drivers/gpu/drm/i915/display/intel_fdi.c
View File

@ -306,7 +306,7 @@ int intel_fdi_link_freq(struct drm_i915_private *i915,
bool intel_fdi_compute_pipe_bpp(struct intel_crtc_state *crtc_state)
{
int pipe_bpp = min(crtc_state->pipe_bpp,
to_bpp_int(crtc_state->max_link_bpp_x16));
fxp_q4_to_int(crtc_state->max_link_bpp_x16));
pipe_bpp = rounddown(pipe_bpp, 2 * 3);

5
drivers/gpu/drm/i915/display/intel_vdsc.c
View File

@ -8,6 +8,7 @@
#include <linux/limits.h>
#include <drm/display/drm_dsc_helper.h>
#include <drm/drm_fixed.h>
#include "i915_drv.h"
#include "intel_crtc.h"
@ -76,7 +77,7 @@ intel_vdsc_set_min_max_qp(struct drm_dsc_config *vdsc_cfg, int buf,
static void
calculate_rc_params(struct drm_dsc_config *vdsc_cfg)
{
int bpp = to_bpp_int(vdsc_cfg->bits_per_pixel);
int bpp = fxp_q4_to_int(vdsc_cfg->bits_per_pixel);
int bpc = vdsc_cfg->bits_per_component;
int qp_bpc_modifier = (bpc - 8) * 2;
int uncompressed_bpg_rate;
@ -263,7 +264,7 @@ int intel_dsc_compute_params(struct intel_crtc_state *pipe_config)
struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
struct drm_dsc_config *vdsc_cfg = &pipe_config->dsc.config;
u16 compressed_bpp = to_bpp_int(pipe_config->dsc.compressed_bpp_x16);
u16 compressed_bpp = fxp_q4_to_int(pipe_config->dsc.compressed_bpp_x16);
int err;
int ret;