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x86/paravirt: Drop {read,write}_cr8() hooks
There is a lot of infrastructure for functionality which is used exclusively in __{save,restore}_processor_state() on the suspend/resume path. cr8 is an alias of APIC_TASKPRI, and APIC_TASKPRI is saved/restored by lapic_{suspend,resume}(). Saving and restoring cr8 independently of the rest of the Local APIC state isn't a clever thing to be doing. Delete the suspend/resume cr8 handling, which shrinks the size of struct saved_context, and allows for the removal of both PVOPS. Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Juergen Gross <jgross@suse.com> Link: https://lkml.kernel.org/r/20190715151641.29210-1-andrew.cooper3@citrix.com
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@ -139,18 +139,6 @@ static inline void __write_cr4(unsigned long x)
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PVOP_VCALL1(cpu.write_cr4, x);
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}
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#ifdef CONFIG_X86_64
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static inline unsigned long read_cr8(void)
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{
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return PVOP_CALL0(unsigned long, cpu.read_cr8);
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}
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static inline void write_cr8(unsigned long x)
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{
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PVOP_VCALL1(cpu.write_cr8, x);
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}
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#endif
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static inline void arch_safe_halt(void)
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{
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PVOP_VCALL0(irq.safe_halt);
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@ -119,11 +119,6 @@ struct pv_cpu_ops {
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void (*write_cr4)(unsigned long);
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#ifdef CONFIG_X86_64
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unsigned long (*read_cr8)(void);
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void (*write_cr8)(unsigned long);
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#endif
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/* Segment descriptor handling */
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void (*load_tr_desc)(void);
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void (*load_gdt)(const struct desc_ptr *);
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@ -73,20 +73,6 @@ static inline unsigned long native_read_cr4(void)
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void native_write_cr4(unsigned long val);
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#ifdef CONFIG_X86_64
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static inline unsigned long native_read_cr8(void)
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{
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unsigned long cr8;
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asm volatile("movq %%cr8,%0" : "=r" (cr8));
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return cr8;
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}
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static inline void native_write_cr8(unsigned long val)
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{
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asm volatile("movq %0,%%cr8" :: "r" (val) : "memory");
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}
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#endif
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#ifdef CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS
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static inline u32 rdpkru(void)
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{
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@ -200,16 +186,6 @@ static inline void wbinvd(void)
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#ifdef CONFIG_X86_64
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static inline unsigned long read_cr8(void)
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{
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return native_read_cr8();
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}
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static inline void write_cr8(unsigned long x)
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{
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native_write_cr8(x);
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}
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static inline void load_gs_index(unsigned selector)
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{
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native_load_gs_index(selector);
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@ -34,7 +34,7 @@ struct saved_context {
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*/
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unsigned long kernelmode_gs_base, usermode_gs_base, fs_base;
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unsigned long cr0, cr2, cr3, cr4, cr8;
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unsigned long cr0, cr2, cr3, cr4;
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u64 misc_enable;
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bool misc_enable_saved;
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struct saved_msrs saved_msrs;
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@ -62,7 +62,6 @@ int main(void)
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ENTRY(cr2);
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ENTRY(cr3);
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ENTRY(cr4);
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ENTRY(cr8);
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ENTRY(gdt_desc);
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BLANK();
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#undef ENTRY
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@ -311,10 +311,6 @@ struct paravirt_patch_template pv_ops = {
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.cpu.read_cr0 = native_read_cr0,
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.cpu.write_cr0 = native_write_cr0,
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.cpu.write_cr4 = native_write_cr4,
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#ifdef CONFIG_X86_64
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.cpu.read_cr8 = native_read_cr8,
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.cpu.write_cr8 = native_write_cr8,
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#endif
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.cpu.wbinvd = native_wbinvd,
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.cpu.read_msr = native_read_msr,
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.cpu.write_msr = native_write_msr,
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@ -122,9 +122,6 @@ static void __save_processor_state(struct saved_context *ctxt)
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ctxt->cr2 = read_cr2();
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ctxt->cr3 = __read_cr3();
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ctxt->cr4 = __read_cr4();
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#ifdef CONFIG_X86_64
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ctxt->cr8 = read_cr8();
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#endif
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ctxt->misc_enable_saved = !rdmsrl_safe(MSR_IA32_MISC_ENABLE,
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&ctxt->misc_enable);
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msr_save_context(ctxt);
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@ -207,7 +204,6 @@ static void notrace __restore_processor_state(struct saved_context *ctxt)
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#else
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/* CONFIG X86_64 */
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wrmsrl(MSR_EFER, ctxt->efer);
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write_cr8(ctxt->cr8);
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__write_cr4(ctxt->cr4);
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#endif
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write_cr3(ctxt->cr3);
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@ -877,16 +877,6 @@ static void xen_write_cr4(unsigned long cr4)
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native_write_cr4(cr4);
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}
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#ifdef CONFIG_X86_64
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static inline unsigned long xen_read_cr8(void)
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{
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return 0;
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}
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static inline void xen_write_cr8(unsigned long val)
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{
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BUG_ON(val);
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}
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#endif
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static u64 xen_read_msr_safe(unsigned int msr, int *err)
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{
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@ -1023,11 +1013,6 @@ static const struct pv_cpu_ops xen_cpu_ops __initconst = {
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.write_cr4 = xen_write_cr4,
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#ifdef CONFIG_X86_64
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.read_cr8 = xen_read_cr8,
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.write_cr8 = xen_write_cr8,
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#endif
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.wbinvd = native_wbinvd,
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.read_msr = xen_read_msr,
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