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IB/mlx5: Add mlx5_ib_update_mtt to update page tables after creation
The new function allows updating the page tables of a memory region after it was created. This can be used to handle page faults and page invalidations. Since mlx5_ib_update_mtt will need to work from within page invalidation, so it must not block on memory allocation. It employs an atomic memory allocation mechanism that is used as a fallback when kmalloc(GFP_ATOMIC) fails. In order to reuse code from mlx5_ib_populate_pas, the patch splits this function and add the needed parameters. Signed-off-by: Haggai Eran <haggaie@mellanox.com> Signed-off-by: Shachar Raindel <raindel@mellanox.com> Signed-off-by: Roland Dreier <roland@purestorage.com>
This commit is contained in:
Haggai Eran
Roland Dreier
parent
cc149f751b
commit
832a6b06ab
@ -140,12 +140,16 @@ static u64 umem_dma_to_mtt(dma_addr_t umem_dma)
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* dev - mlx5_ib device
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* umem - umem to use to fill the pages
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* page_shift - determines the page size used in the resulting array
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* offset - offset into the umem to start from,
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* only implemented for ODP umems
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* num_pages - total number of pages to fill
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* pas - bus addresses array to fill
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* access_flags - access flags to set on all present pages.
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use enum mlx5_ib_mtt_access_flags for this.
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*/
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void mlx5_ib_populate_pas(struct mlx5_ib_dev *dev, struct ib_umem *umem,
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int page_shift, __be64 *pas, int access_flags)
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void __mlx5_ib_populate_pas(struct mlx5_ib_dev *dev, struct ib_umem *umem,
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int page_shift, size_t offset, size_t num_pages,
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__be64 *pas, int access_flags)
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{
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unsigned long umem_page_shift = ilog2(umem->page_size);
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int shift = page_shift - umem_page_shift;
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@ -160,13 +164,11 @@ void mlx5_ib_populate_pas(struct mlx5_ib_dev *dev, struct ib_umem *umem,
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const bool odp = umem->odp_data != NULL;
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if (odp) {
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int num_pages = ib_umem_num_pages(umem);
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WARN_ON(shift != 0);
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WARN_ON(access_flags != (MLX5_IB_MTT_READ | MLX5_IB_MTT_WRITE));
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for (i = 0; i < num_pages; ++i) {
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dma_addr_t pa = umem->odp_data->dma_list[i];
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dma_addr_t pa = umem->odp_data->dma_list[offset + i];
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pas[i] = cpu_to_be64(umem_dma_to_mtt(pa));
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}
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@ -194,6 +196,13 @@ void mlx5_ib_populate_pas(struct mlx5_ib_dev *dev, struct ib_umem *umem,
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}
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}
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void mlx5_ib_populate_pas(struct mlx5_ib_dev *dev, struct ib_umem *umem,
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int page_shift, __be64 *pas, int access_flags)
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{
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return __mlx5_ib_populate_pas(dev, umem, page_shift, 0,
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ib_umem_num_pages(umem), pas,
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access_flags);
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}
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int mlx5_ib_get_buf_offset(u64 addr, int page_shift, u32 *offset)
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{
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u64 page_size;
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@ -527,6 +527,8 @@ struct ib_mr *mlx5_ib_get_dma_mr(struct ib_pd *pd, int acc);
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struct ib_mr *mlx5_ib_reg_user_mr(struct ib_pd *pd, u64 start, u64 length,
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u64 virt_addr, int access_flags,
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struct ib_udata *udata);
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int mlx5_ib_update_mtt(struct mlx5_ib_mr *mr, u64 start_page_index,
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int npages, int zap);
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int mlx5_ib_dereg_mr(struct ib_mr *ibmr);
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int mlx5_ib_destroy_mr(struct ib_mr *ibmr);
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struct ib_mr *mlx5_ib_create_mr(struct ib_pd *pd,
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@ -558,6 +560,9 @@ int mlx5_ib_init_fmr(struct mlx5_ib_dev *dev);
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void mlx5_ib_cleanup_fmr(struct mlx5_ib_dev *dev);
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void mlx5_ib_cont_pages(struct ib_umem *umem, u64 addr, int *count, int *shift,
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int *ncont, int *order);
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void __mlx5_ib_populate_pas(struct mlx5_ib_dev *dev, struct ib_umem *umem,
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int page_shift, size_t offset, size_t num_pages,
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__be64 *pas, int access_flags);
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void mlx5_ib_populate_pas(struct mlx5_ib_dev *dev, struct ib_umem *umem,
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int page_shift, __be64 *pas, int access_flags);
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void mlx5_ib_copy_pas(u64 *old, u64 *new, int step, int num);
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@ -44,9 +44,13 @@ enum {
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MAX_PENDING_REG_MR = 8,
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};
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enum {
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MLX5_UMR_ALIGN = 2048
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};
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#define MLX5_UMR_ALIGN 2048
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#ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
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static __be64 mlx5_ib_update_mtt_emergency_buffer[
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MLX5_UMR_MTT_MIN_CHUNK_SIZE/sizeof(__be64)]
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__aligned(MLX5_UMR_ALIGN);
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static DEFINE_MUTEX(mlx5_ib_update_mtt_emergency_buffer_mutex);
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#endif
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static int order2idx(struct mlx5_ib_dev *dev, int order)
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{
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@ -822,6 +826,128 @@ free_mr:
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return mr;
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}
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#ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
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int mlx5_ib_update_mtt(struct mlx5_ib_mr *mr, u64 start_page_index, int npages,
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int zap)
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{
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struct mlx5_ib_dev *dev = mr->dev;
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struct device *ddev = dev->ib_dev.dma_device;
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struct umr_common *umrc = &dev->umrc;
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struct mlx5_ib_umr_context umr_context;
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struct ib_umem *umem = mr->umem;
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int size;
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__be64 *pas;
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dma_addr_t dma;
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struct ib_send_wr wr, *bad;
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struct mlx5_umr_wr *umrwr = (struct mlx5_umr_wr *)&wr.wr.fast_reg;
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struct ib_sge sg;
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int err = 0;
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const int page_index_alignment = MLX5_UMR_MTT_ALIGNMENT / sizeof(u64);
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const int page_index_mask = page_index_alignment - 1;
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size_t pages_mapped = 0;
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size_t pages_to_map = 0;
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size_t pages_iter = 0;
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int use_emergency_buf = 0;
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/* UMR copies MTTs in units of MLX5_UMR_MTT_ALIGNMENT bytes,
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* so we need to align the offset and length accordingly */
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if (start_page_index & page_index_mask) {
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npages += start_page_index & page_index_mask;
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start_page_index &= ~page_index_mask;
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}
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pages_to_map = ALIGN(npages, page_index_alignment);
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if (start_page_index + pages_to_map > MLX5_MAX_UMR_PAGES)
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return -EINVAL;
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size = sizeof(u64) * pages_to_map;
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size = min_t(int, PAGE_SIZE, size);
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/* We allocate with GFP_ATOMIC to avoid recursion into page-reclaim
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* code, when we are called from an invalidation. The pas buffer must
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* be 2k-aligned for Connect-IB. */
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pas = (__be64 *)get_zeroed_page(GFP_ATOMIC);
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if (!pas) {
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mlx5_ib_warn(dev, "unable to allocate memory during MTT update, falling back to slower chunked mechanism.\n");
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pas = mlx5_ib_update_mtt_emergency_buffer;
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size = MLX5_UMR_MTT_MIN_CHUNK_SIZE;
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use_emergency_buf = 1;
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mutex_lock(&mlx5_ib_update_mtt_emergency_buffer_mutex);
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memset(pas, 0, size);
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}
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pages_iter = size / sizeof(u64);
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dma = dma_map_single(ddev, pas, size, DMA_TO_DEVICE);
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if (dma_mapping_error(ddev, dma)) {
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mlx5_ib_err(dev, "unable to map DMA during MTT update.\n");
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err = -ENOMEM;
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goto free_pas;
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}
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for (pages_mapped = 0;
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pages_mapped < pages_to_map && !err;
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pages_mapped += pages_iter, start_page_index += pages_iter) {
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dma_sync_single_for_cpu(ddev, dma, size, DMA_TO_DEVICE);
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npages = min_t(size_t,
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pages_iter,
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ib_umem_num_pages(umem) - start_page_index);
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if (!zap) {
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__mlx5_ib_populate_pas(dev, umem, PAGE_SHIFT,
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start_page_index, npages, pas,
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MLX5_IB_MTT_PRESENT);
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/* Clear padding after the pages brought from the
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* umem. */
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memset(pas + npages, 0, size - npages * sizeof(u64));
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}
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dma_sync_single_for_device(ddev, dma, size, DMA_TO_DEVICE);
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memset(&wr, 0, sizeof(wr));
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wr.wr_id = (u64)(unsigned long)&umr_context;
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sg.addr = dma;
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sg.length = ALIGN(npages * sizeof(u64),
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MLX5_UMR_MTT_ALIGNMENT);
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sg.lkey = dev->umrc.mr->lkey;
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wr.send_flags = MLX5_IB_SEND_UMR_FAIL_IF_FREE |
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MLX5_IB_SEND_UMR_UPDATE_MTT;
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wr.sg_list = &sg;
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wr.num_sge = 1;
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wr.opcode = MLX5_IB_WR_UMR;
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umrwr->npages = sg.length / sizeof(u64);
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umrwr->page_shift = PAGE_SHIFT;
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umrwr->mkey = mr->mmr.key;
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umrwr->target.offset = start_page_index;
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mlx5_ib_init_umr_context(&umr_context);
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down(&umrc->sem);
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err = ib_post_send(umrc->qp, &wr, &bad);
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if (err) {
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mlx5_ib_err(dev, "UMR post send failed, err %d\n", err);
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} else {
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wait_for_completion(&umr_context.done);
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if (umr_context.status != IB_WC_SUCCESS) {
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mlx5_ib_err(dev, "UMR completion failed, code %d\n",
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umr_context.status);
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err = -EFAULT;
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}
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}
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up(&umrc->sem);
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}
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dma_unmap_single(ddev, dma, size, DMA_TO_DEVICE);
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free_pas:
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if (!use_emergency_buf)
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free_page((unsigned long)pas);
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else
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mutex_unlock(&mlx5_ib_update_mtt_emergency_buffer_mutex);
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return err;
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}
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#endif
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static struct mlx5_ib_mr *reg_create(struct ib_pd *pd, u64 virt_addr,
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u64 length, struct ib_umem *umem,
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int npages, int page_shift,
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@ -200,6 +200,7 @@ enum {
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#define MLX5_UMR_MTT_ALIGNMENT 0x40
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#define MLX5_UMR_MTT_MASK (MLX5_UMR_MTT_ALIGNMENT - 1)
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#define MLX5_UMR_MTT_MIN_CHUNK_SIZE MLX5_UMR_MTT_ALIGNMENT
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enum mlx5_event {
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MLX5_EVENT_TYPE_COMP = 0x0,
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