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nios2: Exception handling
This patch contains the exception entry code (kernel/entry.S) and misaligned exception. Signed-off-by: Ley Foon Tan <lftan@altera.com>
This commit is contained in:
Ley Foon Tan
parent
27d22413e6
commit
82ed08dd1b
555
arch/nios2/kernel/entry.S
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555
arch/nios2/kernel/entry.S
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@ -0,0 +1,555 @@
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/*
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* linux/arch/nios2/kernel/entry.S
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*
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* Copyright (C) 2013-2014 Altera Corporation
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* Copyright (C) 2009, Wind River Systems Inc
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*
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* Implemented by fredrik.markstrom@gmail.com and ivarholmqvist@gmail.com
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*
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* Copyright (C) 1999-2002, Greg Ungerer (gerg@snapgear.com)
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* Copyright (C) 1998 D. Jeff Dionne <jeff@lineo.ca>,
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* Kenneth Albanowski <kjahds@kjahds.com>,
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* Copyright (C) 2000 Lineo Inc. (www.lineo.com)
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* Copyright (C) 2004 Microtronix Datacom Ltd.
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Linux/m68k support by Hamish Macdonald
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*
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* 68060 fixes by Jesper Skov
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* ColdFire support by Greg Ungerer (gerg@snapgear.com)
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* 5307 fixes by David W. Miller
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* linux 2.4 support David McCullough <davidm@snapgear.com>
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*/
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#include <linux/sys.h>
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#include <linux/linkage.h>
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#include <asm/asm-offsets.h>
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#include <asm/asm-macros.h>
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#include <asm/thread_info.h>
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#include <asm/errno.h>
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#include <asm/setup.h>
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#include <asm/entry.h>
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#include <asm/unistd.h>
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#include <asm/processor.h>
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.macro GET_THREAD_INFO reg
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.if THREAD_SIZE & 0xffff0000
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andhi \reg, sp, %hi(~(THREAD_SIZE-1))
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.else
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addi \reg, r0, %lo(~(THREAD_SIZE-1))
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and \reg, \reg, sp
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.endif
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.endm
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.macro kuser_cmpxchg_check
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/*
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* Make sure our user space atomic helper is restarted if it was
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* interrupted in a critical region.
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* ea-4 = address of interrupted insn (ea must be preserved).
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* sp = saved regs.
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* cmpxchg_ldw = first critical insn, cmpxchg_stw = last critical insn.
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* If ea <= cmpxchg_stw and ea > cmpxchg_ldw then saved EA is set to
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* cmpxchg_ldw + 4.
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*/
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/* et = cmpxchg_stw + 4 */
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movui et, (KUSER_BASE + 4 + (cmpxchg_stw - __kuser_helper_start))
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bgtu ea, et, 1f
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subi et, et, (cmpxchg_stw - cmpxchg_ldw) /* et = cmpxchg_ldw + 4 */
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bltu ea, et, 1f
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stw et, PT_EA(sp) /* fix up EA */
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mov ea, et
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1:
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.endm
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.section .rodata
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.align 4
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exception_table:
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.word unhandled_exception /* 0 - Reset */
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.word unhandled_exception /* 1 - Processor-only Reset */
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.word external_interrupt /* 2 - Interrupt */
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.word handle_trap /* 3 - Trap Instruction */
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.word instruction_trap /* 4 - Unimplemented instruction */
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.word handle_illegal /* 5 - Illegal instruction */
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.word handle_unaligned /* 6 - Misaligned data access */
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.word handle_unaligned /* 7 - Misaligned destination address */
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.word handle_diverror /* 8 - Division error */
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.word protection_exception_ba /* 9 - Supervisor-only instr. address */
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.word protection_exception_instr /* 10 - Supervisor only instruction */
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.word protection_exception_ba /* 11 - Supervisor only data address */
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.word unhandled_exception /* 12 - Double TLB miss (data) */
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.word protection_exception_pte /* 13 - TLB permission violation (x) */
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.word protection_exception_pte /* 14 - TLB permission violation (r) */
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.word protection_exception_pte /* 15 - TLB permission violation (w) */
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.word unhandled_exception /* 16 - MPU region violation */
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trap_table:
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.word handle_system_call /* 0 */
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.word instruction_trap /* 1 */
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.word instruction_trap /* 2 */
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.word instruction_trap /* 3 */
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.word instruction_trap /* 4 */
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.word instruction_trap /* 5 */
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.word instruction_trap /* 6 */
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.word instruction_trap /* 7 */
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.word instruction_trap /* 8 */
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.word instruction_trap /* 9 */
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.word instruction_trap /* 10 */
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.word instruction_trap /* 11 */
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.word instruction_trap /* 12 */
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.word instruction_trap /* 13 */
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.word instruction_trap /* 14 */
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.word instruction_trap /* 15 */
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.word instruction_trap /* 16 */
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.word instruction_trap /* 17 */
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.word instruction_trap /* 18 */
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.word instruction_trap /* 19 */
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.word instruction_trap /* 20 */
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.word instruction_trap /* 21 */
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.word instruction_trap /* 22 */
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.word instruction_trap /* 23 */
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.word instruction_trap /* 24 */
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.word instruction_trap /* 25 */
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.word instruction_trap /* 26 */
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.word instruction_trap /* 27 */
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.word instruction_trap /* 28 */
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.word instruction_trap /* 29 */
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.word instruction_trap /* 30 */
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.word handle_breakpoint /* 31 */
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.text
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.set noat
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.set nobreak
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ENTRY(inthandler)
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SAVE_ALL
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kuser_cmpxchg_check
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/* Clear EH bit before we get a new excpetion in the kernel
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* and after we have saved it to the exception frame. This is done
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* whether it's trap, tlb-miss or interrupt. If we don't do this
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* estatus is not updated the next exception.
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*/
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rdctl r24, status
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movi r9, %lo(~STATUS_EH)
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and r24, r24, r9
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wrctl status, r24
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/* Read cause and vector and branch to the associated handler */
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mov r4, sp
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rdctl r5, exception
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movia r9, exception_table
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add r24, r9, r5
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ldw r24, 0(r24)
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jmp r24
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/***********************************************************************
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* Handle traps
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***********************************************************************
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*/
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ENTRY(handle_trap)
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ldw r24, -4(ea) /* instruction that caused the exception */
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srli r24, r24, 4
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andi r24, r24, 0x7c
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movia r9,trap_table
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add r24, r24, r9
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ldw r24, 0(r24)
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jmp r24
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/***********************************************************************
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* Handle system calls
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***********************************************************************
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*/
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ENTRY(handle_system_call)
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/* Enable interrupts */
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rdctl r10, status
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ori r10, r10, STATUS_PIE
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wrctl status, r10
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/* Reload registers destroyed by common code. */
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ldw r4, PT_R4(sp)
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ldw r5, PT_R5(sp)
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local_restart:
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/* Check that the requested system call is within limits */
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movui r1, __NR_syscalls
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bgeu r2, r1, ret_invsyscall
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slli r1, r2, 2
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movhi r11, %hiadj(sys_call_table)
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add r1, r1, r11
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ldw r1, %lo(sys_call_table)(r1)
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beq r1, r0, ret_invsyscall
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/* Check if we are being traced */
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GET_THREAD_INFO r11
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ldw r11,TI_FLAGS(r11)
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BTBNZ r11,r11,TIF_SYSCALL_TRACE,traced_system_call
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/* Execute the system call */
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callr r1
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/* If the syscall returns a negative result:
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* Set r7 to 1 to indicate error,
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* Negate r2 to get a positive error code
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* If the syscall returns zero or a positive value:
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* Set r7 to 0.
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* The sigreturn system calls will skip the code below by
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* adding to register ra. To avoid destroying registers
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*/
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translate_rc_and_ret:
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movi r1, 0
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bge r2, zero, 3f
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sub r2, zero, r2
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movi r1, 1
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3:
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stw r2, PT_R2(sp)
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stw r1, PT_R7(sp)
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end_translate_rc_and_ret:
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ret_from_exception:
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ldw r1, PT_ESTATUS(sp)
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/* if so, skip resched, signals */
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TSTBNZ r1, r1, ESTATUS_EU, Luser_return
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restore_all:
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rdctl r10, status /* disable intrs */
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andi r10, r10, %lo(~STATUS_PIE)
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wrctl status, r10
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RESTORE_ALL
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eret
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/* If the syscall number was invalid return ENOSYS */
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ret_invsyscall:
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movi r2, -ENOSYS
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br translate_rc_and_ret
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/* This implements the same as above, except it calls
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* do_syscall_trace_enter and do_syscall_trace_exit before and after the
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* syscall in order for utilities like strace and gdb to work.
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*/
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traced_system_call:
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SAVE_SWITCH_STACK
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call do_syscall_trace_enter
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RESTORE_SWITCH_STACK
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/* Create system call register arguments. The 5th and 6th
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arguments on stack are already in place at the beginning
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of pt_regs. */
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ldw r2, PT_R2(sp)
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ldw r4, PT_R4(sp)
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ldw r5, PT_R5(sp)
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ldw r6, PT_R6(sp)
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ldw r7, PT_R7(sp)
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/* Fetch the syscall function, we don't need to check the boundaries
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* since this is already done.
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*/
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slli r1, r2, 2
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movhi r11,%hiadj(sys_call_table)
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add r1, r1, r11
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ldw r1, %lo(sys_call_table)(r1)
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callr r1
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/* If the syscall returns a negative result:
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* Set r7 to 1 to indicate error,
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* Negate r2 to get a positive error code
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* If the syscall returns zero or a positive value:
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* Set r7 to 0.
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* The sigreturn system calls will skip the code below by
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* adding to register ra. To avoid destroying registers
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*/
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translate_rc_and_ret2:
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movi r1, 0
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bge r2, zero, 4f
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sub r2, zero, r2
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movi r1, 1
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4:
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stw r2, PT_R2(sp)
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stw r1, PT_R7(sp)
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end_translate_rc_and_ret2:
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SAVE_SWITCH_STACK
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call do_syscall_trace_exit
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RESTORE_SWITCH_STACK
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br ret_from_exception
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Luser_return:
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GET_THREAD_INFO r11 /* get thread_info pointer */
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ldw r10, TI_FLAGS(r11) /* get thread_info->flags */
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ANDI32 r11, r10, _TIF_WORK_MASK
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beq r11, r0, restore_all /* Nothing to do */
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BTBZ r1, r10, TIF_NEED_RESCHED, Lsignal_return
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/* Reschedule work */
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call schedule
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br ret_from_exception
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Lsignal_return:
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ANDI32 r1, r10, _TIF_SIGPENDING | _TIF_NOTIFY_RESUME
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beq r1, r0, restore_all
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mov r4, sp /* pt_regs */
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SAVE_SWITCH_STACK
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call do_notify_resume
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beq r2, r0, no_work_pending
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RESTORE_SWITCH_STACK
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/* prepare restart syscall here without leaving kernel */
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ldw r2, PT_R2(sp) /* reload syscall number in r2 */
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ldw r4, PT_R4(sp) /* reload syscall arguments r4-r9 */
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ldw r5, PT_R5(sp)
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ldw r6, PT_R6(sp)
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ldw r7, PT_R7(sp)
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ldw r8, PT_R8(sp)
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ldw r9, PT_R9(sp)
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br local_restart /* restart syscall */
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no_work_pending:
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RESTORE_SWITCH_STACK
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br ret_from_exception
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/***********************************************************************
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* Handle external interrupts.
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***********************************************************************
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*/
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/*
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* This is the generic interrupt handler (for all hardware interrupt
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* sources). It figures out the vector number and calls the appropriate
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* interrupt service routine directly.
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*/
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external_interrupt:
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rdctl r12, ipending
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rdctl r9, ienable
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and r12, r12, r9
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/* skip if no interrupt is pending */
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beq r12, r0, ret_from_interrupt
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movi r24, -1
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stw r24, PT_ORIG_R2(sp)
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/*
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* Process an external hardware interrupt.
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*/
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addi ea, ea, -4 /* re-issue the interrupted instruction */
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stw ea, PT_EA(sp)
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2: movi r4, %lo(-1) /* Start from bit position 0,
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highest priority */
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/* This is the IRQ # for handler call */
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1: andi r10, r12, 1 /* Isolate bit we are interested in */
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srli r12, r12, 1 /* shift count is costly without hardware
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multiplier */
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addi r4, r4, 1
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beq r10, r0, 1b
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mov r5, sp /* Setup pt_regs pointer for handler call */
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call do_IRQ
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rdctl r12, ipending /* check again if irq still pending */
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rdctl r9, ienable /* Isolate possible interrupts */
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and r12, r12, r9
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bne r12, r0, 2b
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/* br ret_from_interrupt */ /* fall through to ret_from_interrupt */
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ENTRY(ret_from_interrupt)
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ldw r1, PT_ESTATUS(sp) /* check if returning to kernel */
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TSTBNZ r1, r1, ESTATUS_EU, Luser_return
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#ifdef CONFIG_PREEMPT
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GET_THREAD_INFO r1
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ldw r4, TI_PREEMPT_COUNT(r1)
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bne r4, r0, restore_all
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need_resched:
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ldw r4, TI_FLAGS(r1) /* ? Need resched set */
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BTBZ r10, r4, TIF_NEED_RESCHED, restore_all
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ldw r4, PT_ESTATUS(sp) /* ? Interrupts off */
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andi r10, r4, ESTATUS_EPIE
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beq r10, r0, restore_all
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movia r4, PREEMPT_ACTIVE
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stw r4, TI_PREEMPT_COUNT(r1)
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rdctl r10, status /* enable intrs again */
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ori r10, r10 ,STATUS_PIE
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wrctl status, r10
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PUSH r1
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call schedule
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POP r1
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mov r4, r0
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stw r4, TI_PREEMPT_COUNT(r1)
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rdctl r10, status /* disable intrs */
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andi r10, r10, %lo(~STATUS_PIE)
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wrctl status, r10
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br need_resched
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#else
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br restore_all
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#endif
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/***********************************************************************
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* A few syscall wrappers
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***********************************************************************
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*/
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/*
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* int clone(unsigned long clone_flags, unsigned long newsp,
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* int __user * parent_tidptr, int __user * child_tidptr,
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* int tls_val)
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*/
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ENTRY(sys_clone)
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SAVE_SWITCH_STACK
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addi sp, sp, -4
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stw r7, 0(sp) /* Pass 5th arg thru stack */
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mov r7, r6 /* 4th arg is 3rd of clone() */
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mov r6, zero /* 3rd arg always 0 */
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call do_fork
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addi sp, sp, 4
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RESTORE_SWITCH_STACK
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ret
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ENTRY(sys_rt_sigreturn)
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SAVE_SWITCH_STACK
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mov r4, sp
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call do_rt_sigreturn
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RESTORE_SWITCH_STACK
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addi ra, ra, (end_translate_rc_and_ret - translate_rc_and_ret)
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ret
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/***********************************************************************
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* A few other wrappers and stubs
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***********************************************************************
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*/
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protection_exception_pte:
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rdctl r6, pteaddr
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slli r6, r6, 10
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call do_page_fault
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br ret_from_exception
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protection_exception_ba:
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rdctl r6, badaddr
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call do_page_fault
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br ret_from_exception
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protection_exception_instr:
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call handle_supervisor_instr
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br ret_from_exception
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handle_breakpoint:
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call breakpoint_c
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br ret_from_exception
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#ifdef CONFIG_NIOS2_ALIGNMENT_TRAP
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handle_unaligned:
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SAVE_SWITCH_STACK
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call handle_unaligned_c
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RESTORE_SWITCH_STACK
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br ret_from_exception
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#else
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handle_unaligned:
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call handle_unaligned_c
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br ret_from_exception
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#endif
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handle_illegal:
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call handle_illegal_c
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br ret_from_exception
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handle_diverror:
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call handle_diverror_c
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br ret_from_exception
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/*
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* Beware - when entering resume, prev (the current task) is
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* in r4, next (the new task) is in r5, don't change these
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* registers.
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*/
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ENTRY(resume)
|
||||
|
||||
rdctl r7, status /* save thread status reg */
|
||||
stw r7, TASK_THREAD + THREAD_KPSR(r4)
|
||||
|
||||
andi r7, r7, %lo(~STATUS_PIE) /* disable interrupts */
|
||||
wrctl status, r7
|
||||
|
||||
SAVE_SWITCH_STACK
|
||||
stw sp, TASK_THREAD + THREAD_KSP(r4)/* save kernel stack pointer */
|
||||
ldw sp, TASK_THREAD + THREAD_KSP(r5)/* restore new thread stack */
|
||||
movia r24, _current_thread /* save thread */
|
||||
GET_THREAD_INFO r1
|
||||
stw r1, 0(r24)
|
||||
RESTORE_SWITCH_STACK
|
||||
|
||||
ldw r7, TASK_THREAD + THREAD_KPSR(r5)/* restore thread status reg */
|
||||
wrctl status, r7
|
||||
ret
|
||||
|
||||
ENTRY(ret_from_fork)
|
||||
call schedule_tail
|
||||
br ret_from_exception
|
||||
|
||||
ENTRY(ret_from_kernel_thread)
|
||||
call schedule_tail
|
||||
mov r4,r17 /* arg */
|
||||
callr r16 /* function */
|
||||
br ret_from_exception
|
||||
|
||||
/*
|
||||
* Kernel user helpers.
|
||||
*
|
||||
* Each segment is 64-byte aligned and will be mapped to the <User space>.
|
||||
* New segments (if ever needed) must be added after the existing ones.
|
||||
* This mechanism should be used only for things that are really small and
|
||||
* justified, and not be abused freely.
|
||||
*
|
||||
*/
|
||||
|
||||
/* Filling pads with undefined instructions. */
|
||||
.macro kuser_pad sym size
|
||||
.if ((. - \sym) & 3)
|
||||
.rept (4 - (. - \sym) & 3)
|
||||
.byte 0
|
||||
.endr
|
||||
.endif
|
||||
.rept ((\size - (. - \sym)) / 4)
|
||||
.word 0xdeadbeef
|
||||
.endr
|
||||
.endm
|
||||
|
||||
.align 6
|
||||
.globl __kuser_helper_start
|
||||
__kuser_helper_start:
|
||||
|
||||
__kuser_helper_version: /* @ 0x1000 */
|
||||
.word ((__kuser_helper_end - __kuser_helper_start) >> 6)
|
||||
|
||||
__kuser_cmpxchg: /* @ 0x1004 */
|
||||
/*
|
||||
* r4 pointer to exchange variable
|
||||
* r5 old value
|
||||
* r6 new value
|
||||
*/
|
||||
cmpxchg_ldw:
|
||||
ldw r2, 0(r4) /* load current value */
|
||||
sub r2, r2, r5 /* compare with old value */
|
||||
bne r2, zero, cmpxchg_ret
|
||||
|
||||
/* We had a match, store the new value */
|
||||
cmpxchg_stw:
|
||||
stw r6, 0(r4)
|
||||
cmpxchg_ret:
|
||||
ret
|
||||
|
||||
kuser_pad __kuser_cmpxchg, 64
|
||||
|
||||
.globl __kuser_sigtramp
|
||||
__kuser_sigtramp:
|
||||
movi r2, __NR_rt_sigreturn
|
||||
trap
|
||||
|
||||
kuser_pad __kuser_sigtramp, 64
|
||||
|
||||
.globl __kuser_helper_end
|
||||
__kuser_helper_end:
|
||||
256
arch/nios2/kernel/misaligned.c
Normal file
256
arch/nios2/kernel/misaligned.c
Normal file
@ -0,0 +1,256 @@
|
||||
/*
|
||||
* linux/arch/nios2/kernel/misaligned.c
|
||||
*
|
||||
* basic emulation for mis-aligned accesses on the NIOS II cpu
|
||||
* modelled after the version for arm in arm/alignment.c
|
||||
*
|
||||
* Brad Parker <brad@heeltoe.com>
|
||||
* Copyright (C) 2010 Ambient Corporation
|
||||
* Copyright (c) 2010 Altera Corporation, San Jose, California, USA.
|
||||
* Copyright (c) 2010 Arrow Electronics, Inc.
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU General
|
||||
* Public License. See the file COPYING in the main directory of
|
||||
* this archive for more details.
|
||||
*/
|
||||
|
||||
#include <linux/errno.h>
|
||||
#include <linux/string.h>
|
||||
#include <linux/proc_fs.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/sched.h>
|
||||
#include <linux/uaccess.h>
|
||||
#include <linux/seq_file.h>
|
||||
|
||||
#include <asm/traps.h>
|
||||
#include <asm/unaligned.h>
|
||||
|
||||
/* instructions we emulate */
|
||||
#define INST_LDHU 0x0b
|
||||
#define INST_STH 0x0d
|
||||
#define INST_LDH 0x0f
|
||||
#define INST_STW 0x15
|
||||
#define INST_LDW 0x17
|
||||
|
||||
static unsigned long ma_user, ma_kern, ma_skipped, ma_half, ma_word;
|
||||
|
||||
static unsigned int ma_usermode;
|
||||
#define UM_WARN 0x01
|
||||
#define UM_FIXUP 0x02
|
||||
#define UM_SIGNAL 0x04
|
||||
#define KM_WARN 0x08
|
||||
|
||||
/* see arch/nios2/include/asm/ptrace.h */
|
||||
static u8 sys_stack_frame_reg_offset[] = {
|
||||
/* struct pt_regs */
|
||||
8, 9, 10, 11, 12, 13, 14, 15, 1, 2, 3, 4, 5, 6, 7, 0,
|
||||
/* struct switch_stack */
|
||||
16, 17, 18, 19, 20, 21, 22, 23, 0, 0, 0, 0, 0, 0, 0, 0
|
||||
};
|
||||
|
||||
static int reg_offsets[32];
|
||||
|
||||
static inline u32 get_reg_val(struct pt_regs *fp, int reg)
|
||||
{
|
||||
u8 *p = ((u8 *)fp) + reg_offsets[reg];
|
||||
|
||||
return *(u32 *)p;
|
||||
}
|
||||
|
||||
static inline void put_reg_val(struct pt_regs *fp, int reg, u32 val)
|
||||
{
|
||||
u8 *p = ((u8 *)fp) + reg_offsets[reg];
|
||||
*(u32 *)p = val;
|
||||
}
|
||||
|
||||
/*
|
||||
* (mis)alignment handler
|
||||
*/
|
||||
asmlinkage void handle_unaligned_c(struct pt_regs *fp, int cause)
|
||||
{
|
||||
u32 isn, addr, val;
|
||||
int in_kernel;
|
||||
u8 a, b, d0, d1, d2, d3;
|
||||
u16 imm16;
|
||||
unsigned int fault;
|
||||
|
||||
/* back up one instruction */
|
||||
fp->ea -= 4;
|
||||
|
||||
if (fixup_exception(fp)) {
|
||||
ma_skipped++;
|
||||
return;
|
||||
}
|
||||
|
||||
in_kernel = !user_mode(fp);
|
||||
|
||||
isn = *(unsigned long *)(fp->ea);
|
||||
|
||||
fault = 0;
|
||||
|
||||
/* do fixup if in kernel or mode turned on */
|
||||
if (in_kernel || (ma_usermode & UM_FIXUP)) {
|
||||
/* decompose instruction */
|
||||
a = (isn >> 27) & 0x1f;
|
||||
b = (isn >> 22) & 0x1f;
|
||||
imm16 = (isn >> 6) & 0xffff;
|
||||
addr = get_reg_val(fp, a) + imm16;
|
||||
|
||||
/* do fixup to saved registers */
|
||||
switch (isn & 0x3f) {
|
||||
case INST_LDHU:
|
||||
fault |= __get_user(d0, (u8 *)(addr+0));
|
||||
fault |= __get_user(d1, (u8 *)(addr+1));
|
||||
val = (d1 << 8) | d0;
|
||||
put_reg_val(fp, b, val);
|
||||
ma_half++;
|
||||
break;
|
||||
case INST_STH:
|
||||
val = get_reg_val(fp, b);
|
||||
d1 = val >> 8;
|
||||
d0 = val >> 0;
|
||||
|
||||
pr_debug("sth: ra=%d (%08x) rb=%d (%08x), imm16 %04x addr %08x val %08x\n",
|
||||
a, get_reg_val(fp, a),
|
||||
b, get_reg_val(fp, b),
|
||||
imm16, addr, val);
|
||||
|
||||
if (in_kernel) {
|
||||
*(u8 *)(addr+0) = d0;
|
||||
*(u8 *)(addr+1) = d1;
|
||||
} else {
|
||||
fault |= __put_user(d0, (u8 *)(addr+0));
|
||||
fault |= __put_user(d1, (u8 *)(addr+1));
|
||||
}
|
||||
ma_half++;
|
||||
break;
|
||||
case INST_LDH:
|
||||
fault |= __get_user(d0, (u8 *)(addr+0));
|
||||
fault |= __get_user(d1, (u8 *)(addr+1));
|
||||
val = (short)((d1 << 8) | d0);
|
||||
put_reg_val(fp, b, val);
|
||||
ma_half++;
|
||||
break;
|
||||
case INST_STW:
|
||||
val = get_reg_val(fp, b);
|
||||
d3 = val >> 24;
|
||||
d2 = val >> 16;
|
||||
d1 = val >> 8;
|
||||
d0 = val >> 0;
|
||||
if (in_kernel) {
|
||||
*(u8 *)(addr+0) = d0;
|
||||
*(u8 *)(addr+1) = d1;
|
||||
*(u8 *)(addr+2) = d2;
|
||||
*(u8 *)(addr+3) = d3;
|
||||
} else {
|
||||
fault |= __put_user(d0, (u8 *)(addr+0));
|
||||
fault |= __put_user(d1, (u8 *)(addr+1));
|
||||
fault |= __put_user(d2, (u8 *)(addr+2));
|
||||
fault |= __put_user(d3, (u8 *)(addr+3));
|
||||
}
|
||||
ma_word++;
|
||||
break;
|
||||
case INST_LDW:
|
||||
fault |= __get_user(d0, (u8 *)(addr+0));
|
||||
fault |= __get_user(d1, (u8 *)(addr+1));
|
||||
fault |= __get_user(d2, (u8 *)(addr+2));
|
||||
fault |= __get_user(d3, (u8 *)(addr+3));
|
||||
val = (d3 << 24) | (d2 << 16) | (d1 << 8) | d0;
|
||||
put_reg_val(fp, b, val);
|
||||
ma_word++;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
addr = RDCTL(CTL_BADADDR);
|
||||
cause >>= 2;
|
||||
|
||||
if (fault) {
|
||||
if (in_kernel) {
|
||||
pr_err("fault during kernel misaligned fixup @ %#lx; addr 0x%08x; isn=0x%08x\n",
|
||||
fp->ea, (unsigned int)addr,
|
||||
(unsigned int)isn);
|
||||
} else {
|
||||
pr_err("fault during user misaligned fixup @ %#lx; isn=%08x addr=0x%08x sp=0x%08lx pid=%d\n",
|
||||
fp->ea,
|
||||
(unsigned int)isn, addr, fp->sp,
|
||||
current->pid);
|
||||
|
||||
_exception(SIGSEGV, fp, SEGV_MAPERR, fp->ea);
|
||||
return;
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* kernel mode -
|
||||
* note exception and skip bad instruction (return)
|
||||
*/
|
||||
if (in_kernel) {
|
||||
ma_kern++;
|
||||
fp->ea += 4;
|
||||
|
||||
if (ma_usermode & KM_WARN) {
|
||||
pr_err("kernel unaligned access @ %#lx; BADADDR 0x%08x; cause=%d, isn=0x%08x\n",
|
||||
fp->ea,
|
||||
(unsigned int)addr, cause,
|
||||
(unsigned int)isn);
|
||||
/* show_regs(fp); */
|
||||
}
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
ma_user++;
|
||||
|
||||
/*
|
||||
* user mode -
|
||||
* possibly warn,
|
||||
* possibly send SIGBUS signal to process
|
||||
*/
|
||||
if (ma_usermode & UM_WARN) {
|
||||
pr_err("user unaligned access @ %#lx; isn=0x%08lx ea=0x%08lx ra=0x%08lx sp=0x%08lx\n",
|
||||
(unsigned long)addr, (unsigned long)isn,
|
||||
fp->ea, fp->ra, fp->sp);
|
||||
}
|
||||
|
||||
if (ma_usermode & UM_SIGNAL)
|
||||
_exception(SIGBUS, fp, BUS_ADRALN, fp->ea);
|
||||
else
|
||||
fp->ea += 4; /* else advance */
|
||||
}
|
||||
|
||||
static void __init misaligned_calc_reg_offsets(void)
|
||||
{
|
||||
int i, r, offset;
|
||||
|
||||
/* pre-calc offsets of registers on sys call stack frame */
|
||||
offset = 0;
|
||||
|
||||
/* struct pt_regs */
|
||||
for (i = 0; i < 16; i++) {
|
||||
r = sys_stack_frame_reg_offset[i];
|
||||
reg_offsets[r] = offset;
|
||||
offset += 4;
|
||||
}
|
||||
|
||||
/* struct switch_stack */
|
||||
offset = -sizeof(struct switch_stack);
|
||||
for (i = 16; i < 32; i++) {
|
||||
r = sys_stack_frame_reg_offset[i];
|
||||
reg_offsets[r] = offset;
|
||||
offset += 4;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
static int __init misaligned_init(void)
|
||||
{
|
||||
/* default mode - silent fix */
|
||||
ma_usermode = UM_FIXUP | KM_WARN;
|
||||
|
||||
misaligned_calc_reg_offsets();
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
fs_initcall(misaligned_init);
|
||||
Loading…
Reference in New Issue
Block a user