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regulator: bd71837: Disable voltage monitoring for LDO3/4
There is a HW quirk in BD71837. The shutdown sequence timings for bucks/LDOs which are enabled via register interface are changed. At PMIC poweroff the voltage for BUCK6/7 is cut immediately at the beginning of shut-down sequence. This causes LDO5/6 voltage monitoring to detect under voltage and force PMIC to emergency state instead of poweroff. Disable voltage monitoring for LDO5 and LDO6 at probe to avoid this. Signed-off-by: Matti Vaittinen <matti.vaittinen@fi.rohmeurope.com> Signed-off-by: Mark Brown <broonie@kernel.org> Cc: stable@vger.kernel.org
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@ -569,6 +569,25 @@ static int bd71837_probe(struct platform_device *pdev)
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BD71837_REG_REGLOCK);
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}
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/*
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* There is a HW quirk in BD71837. The shutdown sequence timings for
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* bucks/LDOs which are controlled via register interface are changed.
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* At PMIC poweroff the voltage for BUCK6/7 is cut immediately at the
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* beginning of shut-down sequence. As bucks 6 and 7 are parent
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* supplies for LDO5 and LDO6 - this causes LDO5/6 voltage
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* monitoring to errorneously detect under voltage and force PMIC to
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* emergency state instead of poweroff. In order to avoid this we
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* disable voltage monitoring for LDO5 and LDO6
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*/
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err = regmap_update_bits(pmic->mfd->regmap, BD718XX_REG_MVRFLTMASK2,
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BD718XX_LDO5_VRMON80 | BD718XX_LDO6_VRMON80,
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BD718XX_LDO5_VRMON80 | BD718XX_LDO6_VRMON80);
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if (err) {
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dev_err(&pmic->pdev->dev,
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"Failed to disable voltage monitoring\n");
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goto err;
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}
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for (i = 0; i < ARRAY_SIZE(pmic_regulator_inits); i++) {
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struct regulator_desc *desc;
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@ -78,9 +78,9 @@ enum {
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BD71837_REG_TRANS_COND0 = 0x1F,
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BD71837_REG_TRANS_COND1 = 0x20,
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BD71837_REG_VRFAULTEN = 0x21,
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BD71837_REG_MVRFLTMASK0 = 0x22,
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BD71837_REG_MVRFLTMASK1 = 0x23,
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BD71837_REG_MVRFLTMASK2 = 0x24,
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BD718XX_REG_MVRFLTMASK0 = 0x22,
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BD718XX_REG_MVRFLTMASK1 = 0x23,
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BD718XX_REG_MVRFLTMASK2 = 0x24,
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BD71837_REG_RCVCFG = 0x25,
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BD71837_REG_RCVNUM = 0x26,
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BD71837_REG_PWRONCONFIG0 = 0x27,
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@ -159,6 +159,33 @@ enum {
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#define BUCK8_MASK 0x3F
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#define BUCK8_DEFAULT 0x1E
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/* BD718XX Voltage monitoring masks */
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#define BD718XX_BUCK1_VRMON80 0x1
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#define BD718XX_BUCK1_VRMON130 0x2
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#define BD718XX_BUCK2_VRMON80 0x4
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#define BD718XX_BUCK2_VRMON130 0x8
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#define BD718XX_1ST_NODVS_BUCK_VRMON80 0x1
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#define BD718XX_1ST_NODVS_BUCK_VRMON130 0x2
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#define BD718XX_2ND_NODVS_BUCK_VRMON80 0x4
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#define BD718XX_2ND_NODVS_BUCK_VRMON130 0x8
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#define BD718XX_3RD_NODVS_BUCK_VRMON80 0x10
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#define BD718XX_3RD_NODVS_BUCK_VRMON130 0x20
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#define BD718XX_4TH_NODVS_BUCK_VRMON80 0x40
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#define BD718XX_4TH_NODVS_BUCK_VRMON130 0x80
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#define BD718XX_LDO1_VRMON80 0x1
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#define BD718XX_LDO2_VRMON80 0x2
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#define BD718XX_LDO3_VRMON80 0x4
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#define BD718XX_LDO4_VRMON80 0x8
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#define BD718XX_LDO5_VRMON80 0x10
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#define BD718XX_LDO6_VRMON80 0x20
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/* BD71837 specific voltage monitoring masks */
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#define BD71837_BUCK3_VRMON80 0x10
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#define BD71837_BUCK3_VRMON130 0x20
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#define BD71837_BUCK4_VRMON80 0x40
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#define BD71837_BUCK4_VRMON130 0x80
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#define BD71837_LDO7_VRMON80 0x40
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/* BD71837_REG_IRQ bits */
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#define IRQ_SWRST 0x40
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#define IRQ_PWRON_S 0x20
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