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sh-pfc: r8a7740: Add bias (pull-up/down) pinconf support
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
This commit is contained in:
Laurent Pinchart
Simon Horman
parent
f92e1360b4
commit
80da8e02d2
@ -18,10 +18,14 @@
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <linux/io.h>
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#include <linux/kernel.h>
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#include <linux/pinctrl/pinconf-generic.h>
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#include <mach/r8a7740.h>
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#include <mach/irqs.h>
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#include "core.h"
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#include "sh_pfc.h"
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#define CPU_ALL_PORT(fn, pfx, sfx) \
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@ -66,16 +70,6 @@ enum {
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PORT_ALL(IN),
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PINMUX_INPUT_END,
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/* PORT0_IN_PU -> PORT211_IN_PU */
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PINMUX_INPUT_PULLUP_BEGIN,
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PORT_ALL(IN_PU),
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PINMUX_INPUT_PULLUP_END,
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/* PORT0_IN_PD -> PORT211_IN_PD */
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PINMUX_INPUT_PULLDOWN_BEGIN,
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PORT_ALL(IN_PD),
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PINMUX_INPUT_PULLDOWN_END,
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/* PORT0_OUT -> PORT211_OUT */
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PINMUX_OUTPUT_BEGIN,
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PORT_ALL(OUT),
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@ -596,137 +590,11 @@ enum {
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PINMUX_MARK_END,
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};
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#define _PORT_DATA(pfx, sfx) PORT_DATA_IO(pfx)
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#define PINMUX_DATA_GP_ALL() CPU_ALL_PORT(_PORT_DATA, , unused)
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static const pinmux_enum_t pinmux_data[] = {
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/* specify valid pin states for each pin in GPIO mode */
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/* I/O and Pull U/D */
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PORT_DATA_IO_PD(0), PORT_DATA_IO_PD(1),
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PORT_DATA_IO_PD(2), PORT_DATA_IO_PD(3),
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PORT_DATA_IO_PD(4), PORT_DATA_IO_PD(5),
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PORT_DATA_IO_PD(6), PORT_DATA_IO(7),
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PORT_DATA_IO(8), PORT_DATA_IO(9),
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PORT_DATA_IO_PD(10), PORT_DATA_IO_PD(11),
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PORT_DATA_IO_PD(12), PORT_DATA_IO_PU_PD(13),
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PORT_DATA_IO_PD(14), PORT_DATA_IO_PD(15),
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PORT_DATA_IO_PD(16), PORT_DATA_IO_PD(17),
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PORT_DATA_IO(18), PORT_DATA_IO_PU(19),
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PORT_DATA_IO_PU_PD(20), PORT_DATA_IO_PD(21),
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PORT_DATA_IO_PU_PD(22), PORT_DATA_IO(23),
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PORT_DATA_IO_PU(24), PORT_DATA_IO_PU(25),
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PORT_DATA_IO_PU(26), PORT_DATA_IO_PU(27),
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PORT_DATA_IO_PU(28), PORT_DATA_IO_PU(29),
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PORT_DATA_IO_PU(30), PORT_DATA_IO_PD(31),
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PORT_DATA_IO_PD(32), PORT_DATA_IO_PD(33),
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PORT_DATA_IO_PD(34), PORT_DATA_IO_PU(35),
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PORT_DATA_IO_PU(36), PORT_DATA_IO_PD(37),
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PORT_DATA_IO_PU(38), PORT_DATA_IO_PD(39),
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PORT_DATA_IO_PU_PD(40), PORT_DATA_IO_PD(41),
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PORT_DATA_IO_PD(42), PORT_DATA_IO_PU_PD(43),
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PORT_DATA_IO_PU_PD(44), PORT_DATA_IO_PU_PD(45),
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PORT_DATA_IO_PU_PD(46), PORT_DATA_IO_PU_PD(47),
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PORT_DATA_IO_PU_PD(48), PORT_DATA_IO_PU_PD(49),
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PORT_DATA_IO_PU_PD(50), PORT_DATA_IO_PD(51),
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PORT_DATA_IO_PD(52), PORT_DATA_IO_PD(53),
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PORT_DATA_IO_PD(54), PORT_DATA_IO_PU_PD(55),
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PORT_DATA_IO_PU_PD(56), PORT_DATA_IO_PU_PD(57),
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PORT_DATA_IO_PU_PD(58), PORT_DATA_IO_PU_PD(59),
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PORT_DATA_IO_PU_PD(60), PORT_DATA_IO_PD(61),
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PORT_DATA_IO_PD(62), PORT_DATA_IO_PD(63),
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PORT_DATA_IO_PD(64), PORT_DATA_IO_PD(65),
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PORT_DATA_IO_PU_PD(66), PORT_DATA_IO_PU_PD(67),
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PORT_DATA_IO_PU_PD(68), PORT_DATA_IO_PU_PD(69),
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PORT_DATA_IO_PU_PD(70), PORT_DATA_IO_PU_PD(71),
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PORT_DATA_IO_PU_PD(72), PORT_DATA_IO_PU_PD(73),
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PORT_DATA_IO_PU_PD(74), PORT_DATA_IO_PU_PD(75),
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PORT_DATA_IO_PU_PD(76), PORT_DATA_IO_PU_PD(77),
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PORT_DATA_IO_PU_PD(78), PORT_DATA_IO_PU_PD(79),
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PORT_DATA_IO_PU_PD(80), PORT_DATA_IO_PU_PD(81),
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PORT_DATA_IO(82), PORT_DATA_IO_PU_PD(83),
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PORT_DATA_IO(84), PORT_DATA_IO_PD(85),
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PORT_DATA_IO_PD(86), PORT_DATA_IO_PD(87),
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PORT_DATA_IO_PD(88), PORT_DATA_IO_PD(89),
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PORT_DATA_IO_PD(90), PORT_DATA_IO_PU_PD(91),
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PORT_DATA_IO_PU_PD(92), PORT_DATA_IO_PU_PD(93),
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PORT_DATA_IO_PU_PD(94), PORT_DATA_IO_PU_PD(95),
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PORT_DATA_IO_PU_PD(96), PORT_DATA_IO_PU_PD(97),
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PORT_DATA_IO_PU_PD(98), PORT_DATA_IO_PU_PD(99),
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PORT_DATA_IO_PU_PD(100), PORT_DATA_IO(101),
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PORT_DATA_IO_PU(102), PORT_DATA_IO_PU_PD(103),
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PORT_DATA_IO_PU(104), PORT_DATA_IO_PU(105),
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PORT_DATA_IO_PU_PD(106), PORT_DATA_IO(107),
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PORT_DATA_IO(108), PORT_DATA_IO(109),
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PORT_DATA_IO(110), PORT_DATA_IO(111),
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PORT_DATA_IO(112), PORT_DATA_IO(113),
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PORT_DATA_IO_PU_PD(114), PORT_DATA_IO(115),
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PORT_DATA_IO_PD(116), PORT_DATA_IO_PD(117),
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PORT_DATA_IO_PD(118), PORT_DATA_IO_PD(119),
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PORT_DATA_IO_PD(120), PORT_DATA_IO_PD(121),
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PORT_DATA_IO_PD(122), PORT_DATA_IO_PD(123),
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PORT_DATA_IO_PD(124), PORT_DATA_IO(125),
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PORT_DATA_IO(126), PORT_DATA_IO(127),
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PORT_DATA_IO(128), PORT_DATA_IO(129),
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PORT_DATA_IO(130), PORT_DATA_IO(131),
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PORT_DATA_IO(132), PORT_DATA_IO(133),
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PORT_DATA_IO(134), PORT_DATA_IO(135),
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PORT_DATA_IO(136), PORT_DATA_IO(137),
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PORT_DATA_IO(138), PORT_DATA_IO(139),
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PORT_DATA_IO(140), PORT_DATA_IO(141),
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PORT_DATA_IO_PU(142), PORT_DATA_IO_PU(143),
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PORT_DATA_IO_PU(144), PORT_DATA_IO_PU(145),
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PORT_DATA_IO_PU(146), PORT_DATA_IO_PU(147),
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PORT_DATA_IO_PU(148), PORT_DATA_IO_PU(149),
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PORT_DATA_IO_PU(150), PORT_DATA_IO_PU(151),
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PORT_DATA_IO_PU(152), PORT_DATA_IO_PU(153),
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PORT_DATA_IO_PU(154), PORT_DATA_IO_PU(155),
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PORT_DATA_IO_PU(156), PORT_DATA_IO_PU(157),
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PORT_DATA_IO_PD(158), PORT_DATA_IO_PD(159),
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PORT_DATA_IO_PU_PD(160), PORT_DATA_IO_PD(161),
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PORT_DATA_IO_PD(162), PORT_DATA_IO_PD(163),
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PORT_DATA_IO_PD(164), PORT_DATA_IO_PD(165),
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PORT_DATA_IO_PU(166), PORT_DATA_IO_PU(167),
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PORT_DATA_IO_PU(168), PORT_DATA_IO_PU(169),
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PORT_DATA_IO_PU(170), PORT_DATA_IO_PU(171),
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PORT_DATA_IO_PD(172), PORT_DATA_IO_PD(173),
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PORT_DATA_IO_PD(174), PORT_DATA_IO_PD(175),
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PORT_DATA_IO_PU(176), PORT_DATA_IO_PU_PD(177),
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PORT_DATA_IO_PU(178), PORT_DATA_IO_PD(179),
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PORT_DATA_IO_PD(180), PORT_DATA_IO_PU(181),
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PORT_DATA_IO_PU(182), PORT_DATA_IO(183),
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PORT_DATA_IO_PD(184), PORT_DATA_IO_PD(185),
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PORT_DATA_IO_PD(186), PORT_DATA_IO_PD(187),
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PORT_DATA_IO_PD(188), PORT_DATA_IO_PD(189),
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PORT_DATA_IO_PD(190), PORT_DATA_IO_PD(191),
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PORT_DATA_IO_PD(192), PORT_DATA_IO_PU_PD(193),
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PORT_DATA_IO_PU_PD(194), PORT_DATA_IO_PD(195),
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PORT_DATA_IO_PU_PD(196), PORT_DATA_IO_PD(197),
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PORT_DATA_IO_PU_PD(198), PORT_DATA_IO_PU_PD(199),
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PORT_DATA_IO_PU_PD(200), PORT_DATA_IO_PU(201),
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PORT_DATA_IO_PU_PD(202), PORT_DATA_IO(203),
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PORT_DATA_IO_PU_PD(204), PORT_DATA_IO_PU_PD(205),
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PORT_DATA_IO_PU_PD(206), PORT_DATA_IO_PU_PD(207),
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PORT_DATA_IO_PU_PD(208), PORT_DATA_IO_PD(209),
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PORT_DATA_IO_PD(210), PORT_DATA_IO_PD(211),
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PINMUX_DATA_GP_ALL(),
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/* Port0 */
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PINMUX_DATA(DBGMDT2_MARK, PORT0_FN1),
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@ -1669,8 +1537,138 @@ static const pinmux_enum_t pinmux_data[] = {
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PINMUX_DATA(TRACEAUD_FROM_MEMC_MARK, MSEL5CR_30_1, MSEL5CR_29_0),
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};
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#define R8A7740_PIN(pin, cfgs) \
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{ \
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.name = __stringify(PORT##pin), \
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.enum_id = PORT##pin##_DATA, \
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.configs = cfgs, \
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}
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#define __I (SH_PFC_PIN_CFG_INPUT)
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#define __O (SH_PFC_PIN_CFG_OUTPUT)
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#define __IO (SH_PFC_PIN_CFG_INPUT | SH_PFC_PIN_CFG_OUTPUT)
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#define __PD (SH_PFC_PIN_CFG_PULL_DOWN)
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#define __PU (SH_PFC_PIN_CFG_PULL_UP)
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#define __PUD (SH_PFC_PIN_CFG_PULL_DOWN | SH_PFC_PIN_CFG_PULL_UP)
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#define R8A7740_PIN_I_PD(pin) R8A7740_PIN(pin, __I | __PD)
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#define R8A7740_PIN_I_PU(pin) R8A7740_PIN(pin, __I | __PU)
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#define R8A7740_PIN_I_PU_PD(pin) R8A7740_PIN(pin, __I | __PUD)
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#define R8A7740_PIN_IO(pin) R8A7740_PIN(pin, __IO)
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#define R8A7740_PIN_IO_PD(pin) R8A7740_PIN(pin, __IO | __PD)
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#define R8A7740_PIN_IO_PU(pin) R8A7740_PIN(pin, __IO | __PU)
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#define R8A7740_PIN_IO_PU_PD(pin) R8A7740_PIN(pin, __IO | __PUD)
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#define R8A7740_PIN_O(pin) R8A7740_PIN(pin, __O)
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#define R8A7740_PIN_O_PU_PD(pin) R8A7740_PIN(pin, __O | __PUD)
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static struct sh_pfc_pin pinmux_pins[] = {
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GPIO_PORT_ALL(),
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/* Table 56-1 (I/O and Pull U/D) */
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R8A7740_PIN_IO_PD(0), R8A7740_PIN_IO_PD(1),
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R8A7740_PIN_IO_PD(2), R8A7740_PIN_IO_PD(3),
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R8A7740_PIN_IO_PD(4), R8A7740_PIN_IO_PD(5),
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R8A7740_PIN_IO_PD(6), R8A7740_PIN_IO(7),
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R8A7740_PIN_IO(8), R8A7740_PIN_IO(9),
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R8A7740_PIN_IO_PD(10), R8A7740_PIN_IO_PD(11),
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R8A7740_PIN_IO_PD(12), R8A7740_PIN_IO_PU_PD(13),
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R8A7740_PIN_IO_PD(14), R8A7740_PIN_IO_PD(15),
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R8A7740_PIN_IO_PD(16), R8A7740_PIN_IO_PD(17),
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R8A7740_PIN_IO(18), R8A7740_PIN_IO_PU(19),
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R8A7740_PIN_IO_PU_PD(20), R8A7740_PIN_IO_PD(21),
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R8A7740_PIN_IO_PU_PD(22), R8A7740_PIN_IO(23),
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R8A7740_PIN_IO_PU(24), R8A7740_PIN_IO_PU(25),
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R8A7740_PIN_IO_PU(26), R8A7740_PIN_IO_PU(27),
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R8A7740_PIN_IO_PU(28), R8A7740_PIN_IO_PU(29),
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R8A7740_PIN_IO_PU(30), R8A7740_PIN_IO_PD(31),
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R8A7740_PIN_IO_PD(32), R8A7740_PIN_IO_PD(33),
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R8A7740_PIN_IO_PD(34), R8A7740_PIN_IO_PU(35),
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R8A7740_PIN_IO_PU(36), R8A7740_PIN_IO_PD(37),
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R8A7740_PIN_IO_PU(38), R8A7740_PIN_IO_PD(39),
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R8A7740_PIN_IO_PU_PD(40), R8A7740_PIN_IO_PD(41),
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R8A7740_PIN_IO_PD(42), R8A7740_PIN_IO_PU_PD(43),
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R8A7740_PIN_IO_PU_PD(44), R8A7740_PIN_IO_PU_PD(45),
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R8A7740_PIN_IO_PU_PD(46), R8A7740_PIN_IO_PU_PD(47),
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R8A7740_PIN_IO_PU_PD(48), R8A7740_PIN_IO_PU_PD(49),
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R8A7740_PIN_IO_PU_PD(50), R8A7740_PIN_IO_PD(51),
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R8A7740_PIN_IO_PD(52), R8A7740_PIN_IO_PD(53),
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R8A7740_PIN_IO_PD(54), R8A7740_PIN_IO_PU_PD(55),
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R8A7740_PIN_IO_PU_PD(56), R8A7740_PIN_IO_PU_PD(57),
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R8A7740_PIN_IO_PU_PD(58), R8A7740_PIN_IO_PU_PD(59),
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R8A7740_PIN_IO_PU_PD(60), R8A7740_PIN_IO_PD(61),
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R8A7740_PIN_IO_PD(62), R8A7740_PIN_IO_PD(63),
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R8A7740_PIN_IO_PD(64), R8A7740_PIN_IO_PD(65),
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R8A7740_PIN_IO_PU_PD(66), R8A7740_PIN_IO_PU_PD(67),
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R8A7740_PIN_IO_PU_PD(68), R8A7740_PIN_IO_PU_PD(69),
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R8A7740_PIN_IO_PU_PD(70), R8A7740_PIN_IO_PU_PD(71),
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R8A7740_PIN_IO_PU_PD(72), R8A7740_PIN_IO_PU_PD(73),
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R8A7740_PIN_IO_PU_PD(74), R8A7740_PIN_IO_PU_PD(75),
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R8A7740_PIN_IO_PU_PD(76), R8A7740_PIN_IO_PU_PD(77),
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R8A7740_PIN_IO_PU_PD(78), R8A7740_PIN_IO_PU_PD(79),
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R8A7740_PIN_IO_PU_PD(80), R8A7740_PIN_IO_PU_PD(81),
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R8A7740_PIN_IO(82), R8A7740_PIN_IO_PU_PD(83),
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R8A7740_PIN_IO(84), R8A7740_PIN_IO_PD(85),
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R8A7740_PIN_IO_PD(86), R8A7740_PIN_IO_PD(87),
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R8A7740_PIN_IO_PD(88), R8A7740_PIN_IO_PD(89),
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R8A7740_PIN_IO_PD(90), R8A7740_PIN_IO_PU_PD(91),
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R8A7740_PIN_IO_PU_PD(92), R8A7740_PIN_IO_PU_PD(93),
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R8A7740_PIN_IO_PU_PD(94), R8A7740_PIN_IO_PU_PD(95),
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R8A7740_PIN_IO_PU_PD(96), R8A7740_PIN_IO_PU_PD(97),
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R8A7740_PIN_IO_PU_PD(98), R8A7740_PIN_IO_PU_PD(99),
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R8A7740_PIN_IO_PU_PD(100), R8A7740_PIN_IO(101),
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R8A7740_PIN_IO_PU(102), R8A7740_PIN_IO_PU_PD(103),
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R8A7740_PIN_IO_PU(104), R8A7740_PIN_IO_PU(105),
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R8A7740_PIN_IO_PU_PD(106), R8A7740_PIN_IO(107),
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R8A7740_PIN_IO(108), R8A7740_PIN_IO(109),
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R8A7740_PIN_IO(110), R8A7740_PIN_IO(111),
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R8A7740_PIN_IO(112), R8A7740_PIN_IO(113),
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R8A7740_PIN_IO_PU_PD(114), R8A7740_PIN_IO(115),
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R8A7740_PIN_IO_PD(116), R8A7740_PIN_IO_PD(117),
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R8A7740_PIN_IO_PD(118), R8A7740_PIN_IO_PD(119),
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R8A7740_PIN_IO_PD(120), R8A7740_PIN_IO_PD(121),
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R8A7740_PIN_IO_PD(122), R8A7740_PIN_IO_PD(123),
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R8A7740_PIN_IO_PD(124), R8A7740_PIN_IO(125),
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R8A7740_PIN_IO(126), R8A7740_PIN_IO(127),
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R8A7740_PIN_IO(128), R8A7740_PIN_IO(129),
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R8A7740_PIN_IO(130), R8A7740_PIN_IO(131),
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R8A7740_PIN_IO(132), R8A7740_PIN_IO(133),
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R8A7740_PIN_IO(134), R8A7740_PIN_IO(135),
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R8A7740_PIN_IO(136), R8A7740_PIN_IO(137),
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R8A7740_PIN_IO(138), R8A7740_PIN_IO(139),
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R8A7740_PIN_IO(140), R8A7740_PIN_IO(141),
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R8A7740_PIN_IO_PU(142), R8A7740_PIN_IO_PU(143),
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R8A7740_PIN_IO_PU(144), R8A7740_PIN_IO_PU(145),
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R8A7740_PIN_IO_PU(146), R8A7740_PIN_IO_PU(147),
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R8A7740_PIN_IO_PU(148), R8A7740_PIN_IO_PU(149),
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R8A7740_PIN_IO_PU(150), R8A7740_PIN_IO_PU(151),
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R8A7740_PIN_IO_PU(152), R8A7740_PIN_IO_PU(153),
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R8A7740_PIN_IO_PU(154), R8A7740_PIN_IO_PU(155),
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R8A7740_PIN_IO_PU(156), R8A7740_PIN_IO_PU(157),
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R8A7740_PIN_IO_PD(158), R8A7740_PIN_IO_PD(159),
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R8A7740_PIN_IO_PU_PD(160), R8A7740_PIN_IO_PD(161),
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R8A7740_PIN_IO_PD(162), R8A7740_PIN_IO_PD(163),
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R8A7740_PIN_IO_PD(164), R8A7740_PIN_IO_PD(165),
|
||||
R8A7740_PIN_IO_PU(166), R8A7740_PIN_IO_PU(167),
|
||||
R8A7740_PIN_IO_PU(168), R8A7740_PIN_IO_PU(169),
|
||||
R8A7740_PIN_IO_PU(170), R8A7740_PIN_IO_PU(171),
|
||||
R8A7740_PIN_IO_PD(172), R8A7740_PIN_IO_PD(173),
|
||||
R8A7740_PIN_IO_PD(174), R8A7740_PIN_IO_PD(175),
|
||||
R8A7740_PIN_IO_PU(176), R8A7740_PIN_IO_PU_PD(177),
|
||||
R8A7740_PIN_IO_PU(178), R8A7740_PIN_IO_PD(179),
|
||||
R8A7740_PIN_IO_PD(180), R8A7740_PIN_IO_PU(181),
|
||||
R8A7740_PIN_IO_PU(182), R8A7740_PIN_IO(183),
|
||||
R8A7740_PIN_IO_PD(184), R8A7740_PIN_IO_PD(185),
|
||||
R8A7740_PIN_IO_PD(186), R8A7740_PIN_IO_PD(187),
|
||||
R8A7740_PIN_IO_PD(188), R8A7740_PIN_IO_PD(189),
|
||||
R8A7740_PIN_IO_PD(190), R8A7740_PIN_IO_PD(191),
|
||||
R8A7740_PIN_IO_PD(192), R8A7740_PIN_IO_PU_PD(193),
|
||||
R8A7740_PIN_IO_PU_PD(194), R8A7740_PIN_IO_PD(195),
|
||||
R8A7740_PIN_IO_PU_PD(196), R8A7740_PIN_IO_PD(197),
|
||||
R8A7740_PIN_IO_PU_PD(198), R8A7740_PIN_IO_PU_PD(199),
|
||||
R8A7740_PIN_IO_PU_PD(200), R8A7740_PIN_IO_PU(201),
|
||||
R8A7740_PIN_IO_PU_PD(202), R8A7740_PIN_IO(203),
|
||||
R8A7740_PIN_IO_PU_PD(204), R8A7740_PIN_IO_PU_PD(205),
|
||||
R8A7740_PIN_IO_PU_PD(206), R8A7740_PIN_IO_PU_PD(207),
|
||||
R8A7740_PIN_IO_PU_PD(208), R8A7740_PIN_IO_PD(209),
|
||||
R8A7740_PIN_IO_PD(210), R8A7740_PIN_IO_PD(211),
|
||||
};
|
||||
|
||||
/* - BSC -------------------------------------------------------------------- */
|
||||
@ -3204,6 +3202,17 @@ static const struct sh_pfc_function pinmux_functions[] = {
|
||||
SH_PFC_FUNCTION(sdhi2),
|
||||
};
|
||||
|
||||
#undef PORTCR
|
||||
#define PORTCR(nr, reg) \
|
||||
{ \
|
||||
PINMUX_CFG_REG("PORT" nr "CR", reg, 8, 4) { \
|
||||
_PCRH(PORT##nr##_IN, 0, 0, PORT##nr##_OUT), \
|
||||
PORT##nr##_FN0, PORT##nr##_FN1, \
|
||||
PORT##nr##_FN2, PORT##nr##_FN3, \
|
||||
PORT##nr##_FN4, PORT##nr##_FN5, \
|
||||
PORT##nr##_FN6, PORT##nr##_FN7 } \
|
||||
}
|
||||
|
||||
static const struct pinmux_cfg_reg pinmux_config_regs[] = {
|
||||
PORTCR(0, 0xe6050000), /* PORT0CR */
|
||||
PORTCR(1, 0xe6050001), /* PORT1CR */
|
||||
@ -3657,14 +3666,80 @@ static const struct pinmux_irq pinmux_irqs[] = {
|
||||
PINMUX_IRQ(irq_pin(31), 41, 167), /* IRQ31A */
|
||||
};
|
||||
|
||||
#define PORTnCR_PULMD_OFF (0 << 6)
|
||||
#define PORTnCR_PULMD_DOWN (2 << 6)
|
||||
#define PORTnCR_PULMD_UP (3 << 6)
|
||||
#define PORTnCR_PULMD_MASK (3 << 6)
|
||||
|
||||
struct r8a7740_portcr_group {
|
||||
unsigned int end_pin;
|
||||
unsigned int offset;
|
||||
};
|
||||
|
||||
static const struct r8a7740_portcr_group r8a7740_portcr_offsets[] = {
|
||||
{ 83, 0x0000 }, { 114, 0x1000 }, { 209, 0x2000 }, { 211, 0x3000 },
|
||||
};
|
||||
|
||||
static void __iomem *r8a7740_pinmux_portcr(struct sh_pfc *pfc, unsigned int pin)
|
||||
{
|
||||
unsigned int i;
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(r8a7740_portcr_offsets); ++i) {
|
||||
const struct r8a7740_portcr_group *group =
|
||||
&r8a7740_portcr_offsets[i];
|
||||
|
||||
if (i <= group->end_pin)
|
||||
return pfc->window->virt + group->offset + pin;
|
||||
}
|
||||
|
||||
return NULL;
|
||||
}
|
||||
|
||||
static unsigned int r8a7740_pinmux_get_bias(struct sh_pfc *pfc, unsigned int pin)
|
||||
{
|
||||
void __iomem *addr = r8a7740_pinmux_portcr(pfc, pin);
|
||||
u32 value = ioread8(addr) & PORTnCR_PULMD_MASK;
|
||||
|
||||
switch (value) {
|
||||
case PORTnCR_PULMD_UP:
|
||||
return PIN_CONFIG_BIAS_PULL_UP;
|
||||
case PORTnCR_PULMD_DOWN:
|
||||
return PIN_CONFIG_BIAS_PULL_DOWN;
|
||||
case PORTnCR_PULMD_OFF:
|
||||
default:
|
||||
return PIN_CONFIG_BIAS_DISABLE;
|
||||
}
|
||||
}
|
||||
|
||||
static void r8a7740_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
|
||||
unsigned int bias)
|
||||
{
|
||||
void __iomem *addr = r8a7740_pinmux_portcr(pfc, pin);
|
||||
u32 value = ioread8(addr) & ~PORTnCR_PULMD_MASK;
|
||||
|
||||
switch (bias) {
|
||||
case PIN_CONFIG_BIAS_PULL_UP:
|
||||
value |= PORTnCR_PULMD_UP;
|
||||
break;
|
||||
case PIN_CONFIG_BIAS_PULL_DOWN:
|
||||
value |= PORTnCR_PULMD_DOWN;
|
||||
break;
|
||||
}
|
||||
|
||||
iowrite8(value, addr);
|
||||
}
|
||||
|
||||
static const struct sh_pfc_soc_operations r8a7740_pinmux_ops = {
|
||||
.get_bias = r8a7740_pinmux_get_bias,
|
||||
.set_bias = r8a7740_pinmux_set_bias,
|
||||
};
|
||||
|
||||
const struct sh_pfc_soc_info r8a7740_pinmux_info = {
|
||||
.name = "r8a7740_pfc",
|
||||
.ops = &r8a7740_pinmux_ops,
|
||||
|
||||
.input = { PINMUX_INPUT_BEGIN,
|
||||
PINMUX_INPUT_END },
|
||||
.input_pu = { PINMUX_INPUT_PULLUP_BEGIN,
|
||||
PINMUX_INPUT_PULLUP_END },
|
||||
.input_pd = { PINMUX_INPUT_PULLDOWN_BEGIN,
|
||||
PINMUX_INPUT_PULLDOWN_END },
|
||||
.output = { PINMUX_OUTPUT_BEGIN,
|
||||
PINMUX_OUTPUT_END },
|
||||
.function = { PINMUX_FUNCTION_BEGIN,
|
||||
|
||||
Loading…
Reference in New Issue
Block a user