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[PATCH] ppc: L2 cache prefetch fixes on 745x

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We run into problems if we blindly enable L2 prefetching without
checking that the L2 cache is actually enabled.  Additionaly, if we
disable the L2 cache we need to ensure that we disable L2 prefetching.

Signed-off-by: Kumar Gala <kumar.gala@freescale.com>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
This commit is contained in:
Kumar Gala 2005-08-31 14:54:47 +10:00 committed by Linus Torvalds
parent 8085ce084c
commit 80ac2912f8
2 changed files with 34 additions and 2 deletions
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5
arch/ppc/kernel/cpu_setup_6xx.S
View File

@ -249,8 +249,11 @@ END_FTR_SECTION_IFSET(CPU_FTR_NO_DPM)
sync
isync
/* Enable L2 HW prefetch
/* Enable L2 HW prefetch, if L2 is enabled
*/
mfspr r3,SPRN_L2CR
andis. r3,r3,L2CR_L2E@h
beqlr
mfspr r3,SPRN_MSSCR0
ori r3,r3,3
sync

31
arch/ppc/kernel/l2cr.S
View File

@ -156,6 +156,26 @@ END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
The bit moved on the 7450.....
****/
BEGIN_FTR_SECTION
/* Disable L2 prefetch on some 745x and try to ensure
* L2 prefetch engines are idle. As explained by errata
* text, we can't be sure they are, we just hope very hard
* that well be enough (sic !). At least I noticed Apple
* doesn't even bother doing the dcbf's here...
*/
mfspr r4,SPRN_MSSCR0
rlwinm r4,r4,0,0,29
sync
mtspr SPRN_MSSCR0,r4
sync
isync
lis r4,KERNELBASE@h
dcbf 0,r4
dcbf 0,r4
dcbf 0,r4
dcbf 0,r4
END_FTR_SECTION_IFSET(CPU_FTR_SPEC7450)
/* TODO: use HW flush assist when available */
lis r4,0x0002
@ -230,7 +250,16 @@ END_FTR_SECTION_IFSET(CPU_FTR_SPEC7450)
oris r3,r3,0x8000
mtspr SPRN_L2CR,r3
sync
/* Enable L2 HW prefetch on 744x/745x */
BEGIN_FTR_SECTION
mfspr r3,SPRN_MSSCR0
ori r3,r3,3
sync
mtspr SPRN_MSSCR0,r3
sync
isync
END_FTR_SECTION_IFSET(CPU_FTR_SPEC7450)
4:
/* Restore HID0[DPM] to whatever it was before */