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ata: ahci_imx: Enlarge RX water mark for i.MX8QM SATA

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The RXWM(RxWaterMark) sets the minimum number of free location within
the RX FIFO before the watermark is exceeded which in turn will cause
the Transport Layer to instruct the Link Layer to transmit HOLDS to the
transmitting end.

Based on the default RXWM value 0x20, RX FIFO overflow might be observed
on i.MX8QM MEK board, when some Gen3 SATA disks are used.

The FIFO overflow will result in CRC error, internal error and protocol
error, then the SATA link is not stable anymore.

To fix this issue, enlarge RX water mark setting from 0x20 to 0x29.

Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Link: https://lore.kernel.org/r/1723428055-27021-5-git-send-email-hongxing.zhu@nxp.com
Signed-off-by: Niklas Cassel <cassel@kernel.org>
This commit is contained in:
Richard Zhu 2024-08-12 10:00:54 +08:00 committed by Niklas Cassel
parent 3156e1b2c0
commit 803f9fb819
1 changed files with 10 additions and 0 deletions
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10
drivers/ata/ahci_imx.c
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@ -45,6 +45,10 @@ enum {
/* Clock Reset Register */
IMX_CLOCK_RESET = 0x7f3f,
IMX_CLOCK_RESET_RESET = 1 << 0,
/* IMX8QM SATA specific control registers */
IMX8QM_SATA_AHCI_PTC = 0xc8,
IMX8QM_SATA_AHCI_PTC_RXWM_MASK = GENMASK(6, 0),
IMX8QM_SATA_AHCI_PTC_RXWM = 0x29,
};
enum ahci_imx_type {
@ -466,6 +470,12 @@ static int imx8_sata_enable(struct ahci_host_priv *hpriv)
phy_power_off(imxpriv->cali_phy0);
phy_exit(imxpriv->cali_phy0);
/* RxWaterMark setting */
val = readl(hpriv->mmio + IMX8QM_SATA_AHCI_PTC);
val &= ~IMX8QM_SATA_AHCI_PTC_RXWM_MASK;
val |= IMX8QM_SATA_AHCI_PTC_RXWM;
writel(val, hpriv->mmio + IMX8QM_SATA_AHCI_PTC);
return 0;
err_sata_phy_exit: