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scsi: mpt3sas: Handle RDPQ DMA allocation in same 4G region
For INVADER_SERIES, each set of 8 reply queues (0 - 7, 8 - 15,..), and for VENTURA_SERIES, each set of 16 reply queues (0 - 15, 16 - 31,..) need to be within the same 4 GB boundary. Driver uses limitation of VENTURA_SERIES to manage INVADER_SERIES as well. The driver is allocating the DMA able memory for RDPQs accordingly. 1) At driver load, set DMA mask to 64 and allocate memory for RDPQs 2) Check if allocated resources for RDPQ are in the same 4GB range 3) If #2 is true, continue with 64 bit DMA and go to #6 4) If #2 is false, then free all the resources from #1 5) Set DMA mask to 32 and allocate RDPQs 6) Proceed with driver loading and other allocations Link: https://lore.kernel.org/r/1587626596-1044-5-git-send-email-suganath-prabu.subramani@broadcom.com Reviewed-by: Christoph Hellwig <hch@lst.de> Signed-off-by: Suganath Prabu <suganath-prabu.subramani@broadcom.com> Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
This commit is contained in:
Suganath Prabu
Martin K. Petersen
parent
85896421df
commit
8012209eb2
@ -2810,7 +2810,7 @@ _base_config_dma_addressing(struct MPT3SAS_ADAPTER *ioc, struct pci_dev *pdev)
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int dma_mask;
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if (ioc->is_mcpu_endpoint ||
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sizeof(dma_addr_t) == 4 ||
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sizeof(dma_addr_t) == 4 || ioc->use_32bit_dma ||
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dma_get_required_mask(&pdev->dev) <= 32)
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dma_mask = 32;
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/* Set 63 bit DMA mask for all SAS3 and SAS35 controllers */
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@ -4807,8 +4807,8 @@ _base_release_memory_pools(struct MPT3SAS_ADAPTER *ioc)
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{
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int i = 0;
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int j = 0;
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int dma_alloc_count = 0;
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struct chain_tracker *ct;
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struct reply_post_struct *rps;
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dexitprintk(ioc, ioc_info(ioc, "%s\n", __func__));
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@ -4850,29 +4850,34 @@ _base_release_memory_pools(struct MPT3SAS_ADAPTER *ioc)
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}
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if (ioc->reply_post) {
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do {
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rps = &ioc->reply_post[i];
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if (rps->reply_post_free) {
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dma_pool_free(
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ioc->reply_post_free_dma_pool,
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rps->reply_post_free,
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rps->reply_post_free_dma);
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dexitprintk(ioc,
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ioc_info(ioc, "reply_post_free_pool(0x%p): free\n",
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rps->reply_post_free));
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rps->reply_post_free = NULL;
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dma_alloc_count = DIV_ROUND_UP(ioc->reply_queue_count,
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RDPQ_MAX_INDEX_IN_ONE_CHUNK);
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for (i = 0; i < ioc->reply_queue_count; i++) {
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if (i % RDPQ_MAX_INDEX_IN_ONE_CHUNK == 0
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&& dma_alloc_count) {
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if (ioc->reply_post[i].reply_post_free) {
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dma_pool_free(
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ioc->reply_post_free_dma_pool,
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ioc->reply_post[i].reply_post_free,
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ioc->reply_post[i].reply_post_free_dma);
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dexitprintk(ioc, ioc_info(ioc,
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"reply_post_free_pool(0x%p): free\n",
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ioc->reply_post[i].reply_post_free));
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ioc->reply_post[i].reply_post_free =
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NULL;
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}
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--dma_alloc_count;
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}
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} while (ioc->rdpq_array_enable &&
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(++i < ioc->reply_queue_count));
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}
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dma_pool_destroy(ioc->reply_post_free_dma_pool);
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if (ioc->reply_post_free_array &&
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ioc->rdpq_array_enable) {
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dma_pool_free(ioc->reply_post_free_array_dma_pool,
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ioc->reply_post_free_array,
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ioc->reply_post_free_array_dma);
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ioc->reply_post_free_array,
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ioc->reply_post_free_array_dma);
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ioc->reply_post_free_array = NULL;
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}
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dma_pool_destroy(ioc->reply_post_free_array_dma_pool);
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dma_pool_destroy(ioc->reply_post_free_dma_pool);
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kfree(ioc->reply_post);
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}
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@ -4948,36 +4953,75 @@ mpt3sas_check_same_4gb_region(long reply_pool_start_address, u32 pool_sz)
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static int
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base_alloc_rdpq_dma_pool(struct MPT3SAS_ADAPTER *ioc, int sz)
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{
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int i;
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int i = 0;
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u32 dma_alloc_count = 0;
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int reply_post_free_sz = ioc->reply_post_queue_depth *
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sizeof(Mpi2DefaultReplyDescriptor_t);
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int count = ioc->rdpq_array_enable ? ioc->reply_queue_count : 1;
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ioc->reply_post = kcalloc(count, sizeof(struct reply_post_struct),
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GFP_KERNEL);
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if (!ioc->reply_post)
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return -ENOMEM;
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/*
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* For INVADER_SERIES each set of 8 reply queues(0-7, 8-15, ..) and
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* VENTURA_SERIES each set of 16 reply queues(0-15, 16-31, ..) should
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* be within 4GB boundary i.e reply queues in a set must have same
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* upper 32-bits in their memory address. so here driver is allocating
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* the DMA'able memory for reply queues according.
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* Driver uses limitation of
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* VENTURA_SERIES to manage INVADER_SERIES as well.
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*/
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dma_alloc_count = DIV_ROUND_UP(ioc->reply_queue_count,
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RDPQ_MAX_INDEX_IN_ONE_CHUNK);
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ioc->reply_post_free_dma_pool =
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dma_pool_create("reply_post_free pool",
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&ioc->pdev->dev, sz, 16, 0);
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dma_pool_create("reply_post_free pool",
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&ioc->pdev->dev, sz, 16, 0);
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if (!ioc->reply_post_free_dma_pool)
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return -ENOMEM;
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i = 0;
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do {
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ioc->reply_post[i].reply_post_free =
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dma_pool_zalloc(ioc->reply_post_free_dma_pool,
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GFP_KERNEL,
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&ioc->reply_post[i].reply_post_free_dma);
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if (!ioc->reply_post[i].reply_post_free)
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return -ENOMEM;
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dinitprintk(ioc,
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ioc_info(ioc, "reply post free pool (0x%p): depth(%d),"
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"element_size(%d), pool_size(%d kB)\n",
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ioc->reply_post[i].reply_post_free,
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ioc->reply_post_queue_depth, 8, sz / 1024));
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dinitprintk(ioc,
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ioc_info(ioc, "reply_post_free_dma = (0x%llx)\n",
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(u64)ioc->reply_post[i].reply_post_free_dma));
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for (i = 0; i < ioc->reply_queue_count; i++) {
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if ((i % RDPQ_MAX_INDEX_IN_ONE_CHUNK == 0) && dma_alloc_count) {
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ioc->reply_post[i].reply_post_free =
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dma_pool_alloc(ioc->reply_post_free_dma_pool,
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GFP_KERNEL,
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&ioc->reply_post[i].reply_post_free_dma);
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if (!ioc->reply_post[i].reply_post_free)
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return -ENOMEM;
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/*
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* Each set of RDPQ pool must satisfy 4gb boundary
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* restriction.
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* 1) Check if allocated resources for RDPQ pool are in
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* the same 4GB range.
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* 2) If #1 is true, continue with 64 bit DMA.
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* 3) If #1 is false, return 1. which means free all the
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* resources and set DMA mask to 32 and allocate.
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*/
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if (!mpt3sas_check_same_4gb_region(
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(long)ioc->reply_post[i].reply_post_free, sz)) {
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dinitprintk(ioc,
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ioc_err(ioc, "bad Replypost free pool(0x%p)"
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"reply_post_free_dma = (0x%llx)\n",
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ioc->reply_post[i].reply_post_free,
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(unsigned long long)
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ioc->reply_post[i].reply_post_free_dma));
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return -EAGAIN;
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}
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memset(ioc->reply_post[i].reply_post_free, 0,
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RDPQ_MAX_INDEX_IN_ONE_CHUNK *
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reply_post_free_sz);
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dma_alloc_count--;
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} while (ioc->rdpq_array_enable && ++i < ioc->reply_queue_count);
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} else {
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ioc->reply_post[i].reply_post_free =
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(Mpi2ReplyDescriptorsUnion_t *)
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((long)ioc->reply_post[i-1].reply_post_free
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+ reply_post_free_sz);
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ioc->reply_post[i].reply_post_free_dma =
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(dma_addr_t)
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(ioc->reply_post[i-1].reply_post_free_dma +
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reply_post_free_sz);
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}
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}
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return 0;
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}
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@ -4995,10 +5039,12 @@ _base_allocate_memory_pools(struct MPT3SAS_ADAPTER *ioc)
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u16 chains_needed_per_io;
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u32 sz, total_sz, reply_post_free_sz, reply_post_free_array_sz;
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u32 retry_sz;
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u32 rdpq_sz = 0;
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u16 max_request_credit, nvme_blocks_needed;
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unsigned short sg_tablesize;
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u16 sge_size;
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int i, j;
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int ret = 0;
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struct chain_tracker *ct;
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dinitprintk(ioc, ioc_info(ioc, "%s\n", __func__));
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@ -5152,14 +5198,28 @@ _base_allocate_memory_pools(struct MPT3SAS_ADAPTER *ioc)
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/* reply post queue, 16 byte align */
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reply_post_free_sz = ioc->reply_post_queue_depth *
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sizeof(Mpi2DefaultReplyDescriptor_t);
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sz = reply_post_free_sz;
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rdpq_sz = reply_post_free_sz * RDPQ_MAX_INDEX_IN_ONE_CHUNK;
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if (_base_is_controller_msix_enabled(ioc) && !ioc->rdpq_array_enable)
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sz *= ioc->reply_queue_count;
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if (base_alloc_rdpq_dma_pool(ioc, sz))
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goto out;
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total_sz += sz * (!ioc->rdpq_array_enable ? 1 : ioc->reply_queue_count);
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rdpq_sz = reply_post_free_sz * ioc->reply_queue_count;
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ret = base_alloc_rdpq_dma_pool(ioc, rdpq_sz);
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if (ret == -EAGAIN) {
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/*
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* Free allocated bad RDPQ memory pools.
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* Change dma coherent mask to 32 bit and reallocate RDPQ
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*/
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_base_release_memory_pools(ioc);
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ioc->use_32bit_dma = true;
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if (_base_config_dma_addressing(ioc, ioc->pdev) != 0) {
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ioc_err(ioc,
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"32 DMA mask failed %s\n", pci_name(ioc->pdev));
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return -ENODEV;
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}
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if (base_alloc_rdpq_dma_pool(ioc, rdpq_sz))
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return -ENOMEM;
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} else if (ret == -ENOMEM)
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return -ENOMEM;
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total_sz = rdpq_sz * (!ioc->rdpq_array_enable ? 1 :
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DIV_ROUND_UP(ioc->reply_queue_count, RDPQ_MAX_INDEX_IN_ONE_CHUNK));
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ioc->scsiio_depth = ioc->hba_queue_depth -
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ioc->hi_priority_depth - ioc->internal_depth;
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@ -5171,7 +5231,6 @@ _base_allocate_memory_pools(struct MPT3SAS_ADAPTER *ioc)
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ioc_info(ioc, "scsi host: can_queue depth (%d)\n",
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ioc->shost->can_queue));
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/* contiguous pool for request and chains, 16 byte align, one extra "
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* "frame for smid=0
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*/
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@ -7141,6 +7200,7 @@ mpt3sas_base_attach(struct MPT3SAS_ADAPTER *ioc)
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ioc->smp_affinity_enable = smp_affinity_enable;
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ioc->rdpq_array_enable_assigned = 0;
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ioc->use_32bit_dma = 0;
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if (ioc->is_aero_ioc)
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ioc->base_readl = &_base_readl_aero;
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else
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@ -367,6 +367,7 @@ struct mpt3sas_nvme_cmd {
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#define MPT3SAS_HIGH_IOPS_REPLY_QUEUES 8
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#define MPT3SAS_HIGH_IOPS_BATCH_COUNT 16
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#define MPT3SAS_GEN35_MAX_MSIX_QUEUES 128
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#define RDPQ_MAX_INDEX_IN_ONE_CHUNK 16
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/* OEM Specific Flags will come from OEM specific header files */
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struct Mpi2ManufacturingPage10_t {
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@ -1063,6 +1064,7 @@ typedef void (*MPT3SAS_FLUSH_RUNNING_CMDS)(struct MPT3SAS_ADAPTER *ioc);
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* @thresh_hold: Max number of reply descriptors processed
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* before updating Host Index
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* @drv_support_bitmap: driver's supported feature bit map
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* @use_32bit_dma: Flag to use 32 bit consistent dma mask
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* @scsi_io_cb_idx: shost generated commands
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* @tm_cb_idx: task management commands
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* @scsih_cb_idx: scsih internal commands
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@ -1252,6 +1254,7 @@ struct MPT3SAS_ADAPTER {
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u8 high_iops_queues;
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u32 drv_support_bitmap;
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bool enable_sdev_max_qd;
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bool use_32bit_dma;
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/* internal commands, callback index */
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u8 scsi_io_cb_idx;
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