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dmaengine: ioatdma: remove ioatdma v2 registration
Removal of support for ioatdma v2 device support. Signed-off-by: Dave Jiang <dave.jiang@intel.com> Acked-by: Dan Williams <dan.j.williams@intel.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
This commit is contained in:
Dave Jiang
Vinod Koul
parent
85596a1947
commit
7f832645d0
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@ -118,30 +118,6 @@ struct ioat_dca_priv {
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struct ioat_dca_slot req_slots[0];
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};
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static u8 ioat_dca_get_tag(struct dca_provider *dca,
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struct device *dev,
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int cpu)
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{
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struct ioat_dca_priv *ioatdca = dca_priv(dca);
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int i, apic_id, bit, value;
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u8 entry, tag;
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tag = 0;
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apic_id = cpu_physical_id(cpu);
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for (i = 0; i < IOAT_TAG_MAP_LEN; i++) {
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entry = ioatdca->tag_map[i];
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if (entry & DCA_TAG_MAP_VALID) {
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bit = entry & ~DCA_TAG_MAP_VALID;
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value = (apic_id & (1 << bit)) ? 1 : 0;
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} else {
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value = entry ? 1 : 0;
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}
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tag |= (value << i);
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}
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return tag;
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}
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static int ioat_dca_dev_managed(struct dca_provider *dca,
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struct device *dev)
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{
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@ -157,182 +133,6 @@ static int ioat_dca_dev_managed(struct dca_provider *dca,
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return 0;
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}
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static int ioat2_dca_add_requester(struct dca_provider *dca, struct device *dev)
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{
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struct ioat_dca_priv *ioatdca = dca_priv(dca);
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struct pci_dev *pdev;
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int i;
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u16 id;
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u16 global_req_table;
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/* This implementation only supports PCI-Express */
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if (!dev_is_pci(dev))
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return -ENODEV;
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pdev = to_pci_dev(dev);
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id = dcaid_from_pcidev(pdev);
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if (ioatdca->requester_count == ioatdca->max_requesters)
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return -ENODEV;
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for (i = 0; i < ioatdca->max_requesters; i++) {
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if (ioatdca->req_slots[i].pdev == NULL) {
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/* found an empty slot */
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ioatdca->requester_count++;
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ioatdca->req_slots[i].pdev = pdev;
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ioatdca->req_slots[i].rid = id;
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global_req_table =
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readw(ioatdca->dca_base + IOAT_DCA_GREQID_OFFSET);
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writel(id | IOAT_DCA_GREQID_VALID,
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ioatdca->iobase + global_req_table + (i * 4));
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return i;
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}
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}
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/* Error, ioatdma->requester_count is out of whack */
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return -EFAULT;
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}
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static int ioat2_dca_remove_requester(struct dca_provider *dca,
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struct device *dev)
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{
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struct ioat_dca_priv *ioatdca = dca_priv(dca);
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struct pci_dev *pdev;
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int i;
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u16 global_req_table;
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/* This implementation only supports PCI-Express */
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if (!dev_is_pci(dev))
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return -ENODEV;
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pdev = to_pci_dev(dev);
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for (i = 0; i < ioatdca->max_requesters; i++) {
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if (ioatdca->req_slots[i].pdev == pdev) {
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global_req_table =
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readw(ioatdca->dca_base + IOAT_DCA_GREQID_OFFSET);
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writel(0, ioatdca->iobase + global_req_table + (i * 4));
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ioatdca->req_slots[i].pdev = NULL;
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ioatdca->req_slots[i].rid = 0;
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ioatdca->requester_count--;
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return i;
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}
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}
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return -ENODEV;
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}
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static u8 ioat2_dca_get_tag(struct dca_provider *dca,
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struct device *dev,
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int cpu)
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{
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u8 tag;
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tag = ioat_dca_get_tag(dca, dev, cpu);
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tag = (~tag) & 0x1F;
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return tag;
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}
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static struct dca_ops ioat2_dca_ops = {
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.add_requester = ioat2_dca_add_requester,
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.remove_requester = ioat2_dca_remove_requester,
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.get_tag = ioat2_dca_get_tag,
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.dev_managed = ioat_dca_dev_managed,
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};
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static int ioat2_dca_count_dca_slots(void __iomem *iobase, u16 dca_offset)
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{
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int slots = 0;
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u32 req;
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u16 global_req_table;
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global_req_table = readw(iobase + dca_offset + IOAT_DCA_GREQID_OFFSET);
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if (global_req_table == 0)
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return 0;
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do {
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req = readl(iobase + global_req_table + (slots * sizeof(u32)));
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slots++;
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} while ((req & IOAT_DCA_GREQID_LASTID) == 0);
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return slots;
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}
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struct dca_provider *ioat2_dca_init(struct pci_dev *pdev, void __iomem *iobase)
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{
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struct dca_provider *dca;
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struct ioat_dca_priv *ioatdca;
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int slots;
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int i;
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int err;
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u32 tag_map;
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u16 dca_offset;
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u16 csi_fsb_control;
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u16 pcie_control;
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u8 bit;
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if (!system_has_dca_enabled(pdev))
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return NULL;
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dca_offset = readw(iobase + IOAT_DCAOFFSET_OFFSET);
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if (dca_offset == 0)
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return NULL;
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slots = ioat2_dca_count_dca_slots(iobase, dca_offset);
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if (slots == 0)
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return NULL;
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dca = alloc_dca_provider(&ioat2_dca_ops,
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sizeof(*ioatdca)
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+ (sizeof(struct ioat_dca_slot) * slots));
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if (!dca)
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return NULL;
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ioatdca = dca_priv(dca);
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ioatdca->iobase = iobase;
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ioatdca->dca_base = iobase + dca_offset;
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ioatdca->max_requesters = slots;
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/* some bios might not know to turn these on */
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csi_fsb_control = readw(ioatdca->dca_base + IOAT_FSB_CAP_ENABLE_OFFSET);
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if ((csi_fsb_control & IOAT_FSB_CAP_ENABLE_PREFETCH) == 0) {
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csi_fsb_control |= IOAT_FSB_CAP_ENABLE_PREFETCH;
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writew(csi_fsb_control,
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ioatdca->dca_base + IOAT_FSB_CAP_ENABLE_OFFSET);
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}
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pcie_control = readw(ioatdca->dca_base + IOAT_PCI_CAP_ENABLE_OFFSET);
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if ((pcie_control & IOAT_PCI_CAP_ENABLE_MEMWR) == 0) {
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pcie_control |= IOAT_PCI_CAP_ENABLE_MEMWR;
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writew(pcie_control,
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ioatdca->dca_base + IOAT_PCI_CAP_ENABLE_OFFSET);
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}
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/* TODO version, compatibility and configuration checks */
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/* copy out the APIC to DCA tag map */
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tag_map = readl(ioatdca->dca_base + IOAT_APICID_TAG_MAP_OFFSET);
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for (i = 0; i < 5; i++) {
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bit = (tag_map >> (4 * i)) & 0x0f;
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if (bit < 8)
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ioatdca->tag_map[i] = bit | DCA_TAG_MAP_VALID;
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else
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ioatdca->tag_map[i] = 0;
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}
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if (!dca2_tag_map_valid(ioatdca->tag_map)) {
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WARN_TAINT_ONCE(1, TAINT_FIRMWARE_WORKAROUND,
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"%s %s: APICID_TAG_MAP set incorrectly by BIOS, disabling DCA\n",
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dev_driver_string(&pdev->dev),
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dev_name(&pdev->dev));
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free_dca_provider(dca);
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return NULL;
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}
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err = register_dca_provider(dca, &pdev->dev);
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if (err) {
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free_dca_provider(dca);
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return NULL;
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}
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return dca;
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}
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static int ioat3_dca_add_requester(struct dca_provider *dca, struct device *dev)
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{
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struct ioat_dca_priv *ioatdca = dca_priv(dca);
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@ -31,7 +31,6 @@
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#include <linux/dma-mapping.h>
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#include <linux/workqueue.h>
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#include <linux/prefetch.h>
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#include <linux/i7300_idle.h>
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#include "dma.h"
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#include "registers.h"
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#include "hw.h"
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@ -31,7 +31,6 @@
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#include <linux/dma-mapping.h>
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#include <linux/workqueue.h>
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#include <linux/prefetch.h>
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#include <linux/i7300_idle.h>
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#include "dma.h"
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#include "dma_v2.h"
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#include "registers.h"
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@ -124,76 +123,6 @@ static void ioat2_start_null_desc(struct ioat2_dma_chan *ioat)
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spin_unlock_bh(&ioat->prep_lock);
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}
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static void __cleanup(struct ioat2_dma_chan *ioat, dma_addr_t phys_complete)
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{
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struct ioat_chan_common *chan = &ioat->base;
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struct dma_async_tx_descriptor *tx;
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struct ioat_ring_ent *desc;
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bool seen_current = false;
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u16 active;
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int idx = ioat->tail, i;
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dev_dbg(to_dev(chan), "%s: head: %#x tail: %#x issued: %#x\n",
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__func__, ioat->head, ioat->tail, ioat->issued);
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active = ioat2_ring_active(ioat);
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for (i = 0; i < active && !seen_current; i++) {
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smp_read_barrier_depends();
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prefetch(ioat2_get_ring_ent(ioat, idx + i + 1));
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desc = ioat2_get_ring_ent(ioat, idx + i);
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tx = &desc->txd;
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dump_desc_dbg(ioat, desc);
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if (tx->cookie) {
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dma_descriptor_unmap(tx);
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dma_cookie_complete(tx);
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if (tx->callback) {
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tx->callback(tx->callback_param);
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tx->callback = NULL;
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}
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}
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if (tx->phys == phys_complete)
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seen_current = true;
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}
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smp_mb(); /* finish all descriptor reads before incrementing tail */
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ioat->tail = idx + i;
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BUG_ON(active && !seen_current); /* no active descs have written a completion? */
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chan->last_completion = phys_complete;
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if (active - i == 0) {
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dev_dbg(to_dev(chan), "%s: cancel completion timeout\n",
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__func__);
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clear_bit(IOAT_COMPLETION_PENDING, &chan->state);
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mod_timer(&chan->timer, jiffies + IDLE_TIMEOUT);
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}
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}
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/**
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* ioat2_cleanup - clean finished descriptors (advance tail pointer)
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* @chan: ioat channel to be cleaned up
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*/
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static void ioat2_cleanup(struct ioat2_dma_chan *ioat)
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{
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struct ioat_chan_common *chan = &ioat->base;
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dma_addr_t phys_complete;
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spin_lock_bh(&chan->cleanup_lock);
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if (ioat_cleanup_preamble(chan, &phys_complete))
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__cleanup(ioat, phys_complete);
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spin_unlock_bh(&chan->cleanup_lock);
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}
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void ioat2_cleanup_event(unsigned long data)
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{
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struct ioat2_dma_chan *ioat = to_ioat2_chan((void *) data);
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struct ioat_chan_common *chan = &ioat->base;
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ioat2_cleanup(ioat);
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if (!test_bit(IOAT_RUN, &chan->state))
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return;
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writew(IOAT_CHANCTRL_RUN, ioat->base.reg_base + IOAT_CHANCTRL_OFFSET);
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}
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void __ioat2_restart_chan(struct ioat2_dma_chan *ioat)
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{
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struct ioat_chan_common *chan = &ioat->base;
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@ -256,110 +185,6 @@ int ioat2_reset_sync(struct ioat_chan_common *chan, unsigned long tmo)
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return err;
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}
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static void ioat2_restart_channel(struct ioat2_dma_chan *ioat)
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{
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struct ioat_chan_common *chan = &ioat->base;
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dma_addr_t phys_complete;
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ioat2_quiesce(chan, 0);
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if (ioat_cleanup_preamble(chan, &phys_complete))
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__cleanup(ioat, phys_complete);
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__ioat2_restart_chan(ioat);
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}
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static void check_active(struct ioat2_dma_chan *ioat)
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{
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struct ioat_chan_common *chan = &ioat->base;
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if (ioat2_ring_active(ioat)) {
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mod_timer(&chan->timer, jiffies + COMPLETION_TIMEOUT);
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return;
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}
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if (test_and_clear_bit(IOAT_CHAN_ACTIVE, &chan->state))
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mod_timer(&chan->timer, jiffies + IDLE_TIMEOUT);
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else if (ioat->alloc_order > ioat_get_alloc_order()) {
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/* if the ring is idle, empty, and oversized try to step
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* down the size
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*/
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reshape_ring(ioat, ioat->alloc_order - 1);
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/* keep shrinking until we get back to our minimum
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* default size
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*/
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if (ioat->alloc_order > ioat_get_alloc_order())
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mod_timer(&chan->timer, jiffies + IDLE_TIMEOUT);
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}
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}
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void ioat2_timer_event(unsigned long data)
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{
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struct ioat2_dma_chan *ioat = to_ioat2_chan((void *) data);
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struct ioat_chan_common *chan = &ioat->base;
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dma_addr_t phys_complete;
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u64 status;
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status = ioat_chansts(chan);
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/* when halted due to errors check for channel
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* programming errors before advancing the completion state
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*/
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if (is_ioat_halted(status)) {
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u32 chanerr;
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chanerr = readl(chan->reg_base + IOAT_CHANERR_OFFSET);
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dev_err(to_dev(chan), "%s: Channel halted (%x)\n",
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__func__, chanerr);
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if (test_bit(IOAT_RUN, &chan->state))
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BUG_ON(is_ioat_bug(chanerr));
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else /* we never got off the ground */
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return;
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}
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/* if we haven't made progress and we have already
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* acknowledged a pending completion once, then be more
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* forceful with a restart
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*/
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spin_lock_bh(&chan->cleanup_lock);
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if (ioat_cleanup_preamble(chan, &phys_complete))
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__cleanup(ioat, phys_complete);
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else if (test_bit(IOAT_COMPLETION_ACK, &chan->state)) {
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spin_lock_bh(&ioat->prep_lock);
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ioat2_restart_channel(ioat);
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spin_unlock_bh(&ioat->prep_lock);
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spin_unlock_bh(&chan->cleanup_lock);
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return;
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} else {
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set_bit(IOAT_COMPLETION_ACK, &chan->state);
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mod_timer(&chan->timer, jiffies + COMPLETION_TIMEOUT);
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}
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if (ioat2_ring_active(ioat))
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mod_timer(&chan->timer, jiffies + COMPLETION_TIMEOUT);
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else {
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spin_lock_bh(&ioat->prep_lock);
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check_active(ioat);
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spin_unlock_bh(&ioat->prep_lock);
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}
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spin_unlock_bh(&chan->cleanup_lock);
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}
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static int ioat2_reset_hw(struct ioat_chan_common *chan)
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{
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/* throw away whatever the channel was doing and get it initialized */
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u32 chanerr;
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ioat2_quiesce(chan, msecs_to_jiffies(100));
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chanerr = readl(chan->reg_base + IOAT_CHANERR_OFFSET);
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writel(chanerr, chan->reg_base + IOAT_CHANERR_OFFSET);
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return ioat2_reset_sync(chan, msecs_to_jiffies(200));
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}
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/**
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* ioat2_enumerate_channels - find and initialize the device's channels
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* @device: the device to be enumerated
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@ -386,11 +211,6 @@ int ioat2_enumerate_channels(struct ioatdma_device *device)
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return 0;
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dev_dbg(dev, "%s: xfercap = %d\n", __func__, 1 << xfercap_log);
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/* FIXME which i/oat version is i7300? */
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#ifdef CONFIG_I7300_IDLE_IOAT_CHANNEL
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if (i7300_idle_platform_probe(NULL, NULL, 1) == 0)
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dma->chancnt--;
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#endif
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for (i = 0; i < dma->chancnt; i++) {
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ioat = devm_kzalloc(dev, sizeof(*ioat), GFP_KERNEL);
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if (!ioat)
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@ -872,45 +692,3 @@ struct kobj_type ioat2_ktype = {
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.sysfs_ops = &ioat_sysfs_ops,
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.default_attrs = ioat2_attrs,
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};
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|
||||
int ioat2_dma_probe(struct ioatdma_device *device, int dca)
|
||||
{
|
||||
struct pci_dev *pdev = device->pdev;
|
||||
struct dma_device *dma;
|
||||
struct dma_chan *c;
|
||||
struct ioat_chan_common *chan;
|
||||
int err;
|
||||
|
||||
device->enumerate_channels = ioat2_enumerate_channels;
|
||||
device->reset_hw = ioat2_reset_hw;
|
||||
device->cleanup_fn = ioat2_cleanup_event;
|
||||
device->timer_fn = ioat2_timer_event;
|
||||
device->self_test = ioat_dma_self_test;
|
||||
dma = &device->common;
|
||||
dma->device_prep_dma_memcpy = ioat2_dma_prep_memcpy_lock;
|
||||
dma->device_issue_pending = ioat2_issue_pending;
|
||||
dma->device_alloc_chan_resources = ioat2_alloc_chan_resources;
|
||||
dma->device_free_chan_resources = ioat2_free_chan_resources;
|
||||
dma->device_tx_status = ioat_dma_tx_status;
|
||||
|
||||
err = ioat_probe(device);
|
||||
if (err)
|
||||
return err;
|
||||
|
||||
list_for_each_entry(c, &dma->channels, device_node) {
|
||||
chan = to_chan_common(c);
|
||||
writel(IOAT_DCACTRL_CMPL_WRITE_ENABLE | IOAT_DMA_DCA_ANY_CPU,
|
||||
chan->reg_base + IOAT_DCACTRL_OFFSET);
|
||||
}
|
||||
|
||||
err = ioat_register(device);
|
||||
if (err)
|
||||
return err;
|
||||
|
||||
ioat_kobject_add(device, &ioat2_ktype);
|
||||
|
||||
if (dca)
|
||||
device->dca = ioat2_dca_init(pdev, device->reg_base);
|
||||
|
||||
return err;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -153,7 +153,6 @@ static inline void ioat2_set_chainaddr(struct ioat2_dma_chan *ioat, u64 addr)
|
|||
|
||||
int ioat2_dma_probe(struct ioatdma_device *dev, int dca);
|
||||
int ioat3_dma_probe(struct ioatdma_device *dev, int dca);
|
||||
struct dca_provider *ioat2_dca_init(struct pci_dev *pdev, void __iomem *iobase);
|
||||
struct dca_provider *ioat3_dca_init(struct pci_dev *pdev, void __iomem *iobase);
|
||||
int ioat2_check_space_lock(struct ioat2_dma_chan *ioat, int num_descs);
|
||||
int ioat2_enumerate_channels(struct ioatdma_device *device);
|
||||
|
|
@ -166,7 +165,6 @@ void ioat2_free_chan_resources(struct dma_chan *c);
|
|||
void __ioat2_restart_chan(struct ioat2_dma_chan *ioat);
|
||||
bool reshape_ring(struct ioat2_dma_chan *ioat, int order);
|
||||
void __ioat2_issue_pending(struct ioat2_dma_chan *ioat);
|
||||
void ioat2_cleanup_event(unsigned long data);
|
||||
void ioat2_timer_event(unsigned long data);
|
||||
int ioat2_quiesce(struct ioat_chan_common *chan, unsigned long tmo);
|
||||
int ioat2_reset_sync(struct ioat_chan_common *chan, unsigned long tmo);
|
||||
|
|
|
|||
|
|
@ -210,9 +210,7 @@ static int ioat_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
|
|||
pci_set_drvdata(pdev, device);
|
||||
|
||||
device->version = readb(device->reg_base + IOAT_VER_OFFSET);
|
||||
if (device->version == IOAT_VER_2_0)
|
||||
err = ioat2_dma_probe(device, ioat_dca_enabled);
|
||||
else if (device->version >= IOAT_VER_3_0)
|
||||
if (device->version >= IOAT_VER_3_0)
|
||||
err = ioat3_dma_probe(device, ioat_dca_enabled);
|
||||
else
|
||||
return -ENODEV;
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user