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soc/tegra: Move Tegra flowctrl driver

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The flowctrl driver is required for both ARM and ARM64 Tegra devices
and in order to enable support for it for ARM64, move the Tegra flowctrl
driver into drivers/soc/tegra.

By moving the flowctrl driver, tegra_flowctrl_init() is now called by
via an early initcall and to prevent this function from attempting to
mapping IO space for a non-Tegra device, a test for 'soc_is_tegra()'
is also added.

Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
This commit is contained in:
Jon Hunter 2017-03-28 13:42:54 +01:00 committed by Thierry Reding
parent 07d76e953b
commit 7e10cf7436
12 changed files with 61 additions and 22 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
arch/arm/mach-tegra/Makefile
View File

@ -2,7 +2,6 @@ asflags-y += -march=armv7-a
obj-y += io.o
obj-y += irq.o
obj-y += flowctrl.o
obj-y += pm.o
obj-y += reset.o
obj-y += reset-handler.o

3
arch/arm/mach-tegra/cpuidle-tegra20.c
View File

@ -26,12 +26,13 @@
#include <linux/kernel.h>
#include <linux/module.h>
#include <soc/tegra/flowctrl.h>
#include <asm/cpuidle.h>
#include <asm/smp_plat.h>
#include <asm/suspend.h>
#include "cpuidle.h"
#include "flowctrl.h"
#include "iomap.h"
#include "irq.h"
#include "pm.h"

2
arch/arm/mach-tegra/platsmp.c
View File

@ -21,6 +21,7 @@
#include <linux/jiffies.h>
#include <linux/smp.h>
#include <soc/tegra/flowctrl.h>
#include <soc/tegra/fuse.h>
#include <soc/tegra/pmc.h>
@ -30,7 +31,6 @@
#include <asm/smp_scu.h>
#include "common.h"
#include "flowctrl.h"
#include "iomap.h"
#include "reset.h"

2
arch/arm/mach-tegra/pm.c
View File

@ -27,6 +27,7 @@
#include <linux/spinlock.h>
#include <linux/suspend.h>
#include <soc/tegra/flowctrl.h>
#include <soc/tegra/fuse.h>
#include <soc/tegra/pm.h>
#include <soc/tegra/pmc.h>
@ -38,7 +39,6 @@
#include <asm/suspend.h>
#include <asm/tlbflush.h>
#include "flowctrl.h"
#include "iomap.h"
#include "pm.h"
#include "reset.h"

2
arch/arm/mach-tegra/reset-handler.S
View File

@ -17,12 +17,12 @@
#include <linux/init.h>
#include <linux/linkage.h>
#include <soc/tegra/flowctrl.h>
#include <soc/tegra/fuse.h>
#include <asm/asm-offsets.h>
#include <asm/cache.h>
#include "flowctrl.h"
#include "iomap.h"
#include "reset.h"
#include "sleep.h"

3
arch/arm/mach-tegra/sleep-tegra20.S
View File

@ -20,6 +20,8 @@
#include <linux/linkage.h>
#include <soc/tegra/flowctrl.h>
#include <asm/assembler.h>
#include <asm/proc-fns.h>
#include <asm/cp15.h>
@ -27,7 +29,6 @@
#include "irammap.h"
#include "sleep.h"
#include "flowctrl.h"
#define EMC_CFG 0xc
#define EMC_ADR_CFG 0x10

2
arch/arm/mach-tegra/sleep-tegra30.S
View File

@ -16,13 +16,13 @@
#include <linux/linkage.h>
#include <soc/tegra/flowctrl.h>
#include <soc/tegra/fuse.h>
#include <asm/asm-offsets.h>
#include <asm/assembler.h>
#include <asm/cache.h>
#include "flowctrl.h"
#include "irammap.h"
#include "sleep.h"

2
arch/arm/mach-tegra/tegra.c
View File

@ -48,7 +48,6 @@
#include "board.h"
#include "common.h"
#include "cpuidle.h"
#include "flowctrl.h"
#include "iomap.h"
#include "irq.h"
#include "pm.h"
@ -75,7 +74,6 @@ static void __init tegra_init_early(void)
{
of_register_trusted_foundations();
tegra_cpu_reset_handler_init();
tegra_flowctrl_init();
}
static void __init tegra_dt_init_irq(void)

7
drivers/soc/tegra/Kconfig
View File

@ -12,6 +12,7 @@ config ARCH_TEGRA_2x_SOC
select PINCTRL_TEGRA20
select PL310_ERRATA_727915 if CACHE_L2X0
select PL310_ERRATA_769419 if CACHE_L2X0
select SOC_TEGRA_FLOWCTRL
select SOC_TEGRA_PMC
select TEGRA_TIMER
help
@ -24,6 +25,7 @@ config ARCH_TEGRA_3x_SOC
select ARM_ERRATA_764369 if SMP
select PINCTRL_TEGRA30
select PL310_ERRATA_769419 if CACHE_L2X0
select SOC_TEGRA_FLOWCTRL
select SOC_TEGRA_PMC
select TEGRA_TIMER
help
@ -35,6 +37,7 @@ config ARCH_TEGRA_114_SOC
select ARM_ERRATA_798181 if SMP
select HAVE_ARM_ARCH_TIMER
select PINCTRL_TEGRA114
select SOC_TEGRA_FLOWCTRL
select SOC_TEGRA_PMC
select TEGRA_TIMER
help
@ -45,6 +48,7 @@ config ARCH_TEGRA_124_SOC
bool "Enable support for Tegra124 family"
select HAVE_ARM_ARCH_TIMER
select PINCTRL_TEGRA124
select SOC_TEGRA_FLOWCTRL
select SOC_TEGRA_PMC
select TEGRA_TIMER
help
@ -101,6 +105,9 @@ config ARCH_TEGRA_186_SOC
endif
endif
config SOC_TEGRA_FLOWCTRL
bool
config SOC_TEGRA_PMC
bool

1
drivers/soc/tegra/Makefile
View File

@ -1,5 +1,6 @@
obj-y += fuse/
obj-y += common.o
obj-$(CONFIG_SOC_TEGRA_FLOWCTRL) += flowctrl.o
obj-$(CONFIG_SOC_TEGRA_PMC) += pmc.o
obj-$(CONFIG_SOC_TEGRA_PMC_TEGRA186) += pmc-tegra186.o

26
arch/arm/mach-tegra/flowctrl.c → drivers/soc/tegra/flowctrl.c
View File

@ -1,7 +1,7 @@
/*
* arch/arm/mach-tegra/flowctrl.c
* drivers/soc/tegra/flowctrl.c
*
* functions and macros to control the flowcontroller
* Functions and macros to control the flowcontroller
*
* Copyright (c) 2010-2012, NVIDIA Corporation. All rights reserved.
*
@ -25,10 +25,10 @@
#include <linux/of.h>
#include <linux/of_address.h>
#include <soc/tegra/common.h>
#include <soc/tegra/flowctrl.h>
#include <soc/tegra/fuse.h>
#include "flowctrl.h"
static u8 flowctrl_offset_halt_cpu[] = {
FLOW_CTRL_HALT_CPU0_EVENTS,
FLOW_CTRL_HALT_CPU1_EVENTS,
@ -47,6 +47,10 @@ static void __iomem *tegra_flowctrl_base;
static void flowctrl_update(u8 offset, u32 value)
{
if (WARN_ONCE(!tegra_flowctrl_base,
"Tegra flowctrl not initialised!\n"))
return;
writel(value, tegra_flowctrl_base + offset);
/* ensure the update has reached the flow controller */
@ -58,6 +62,10 @@ u32 flowctrl_read_cpu_csr(unsigned int cpuid)
{
u8 offset = flowctrl_offset_cpu_csr[cpuid];
if (WARN_ONCE(!tegra_flowctrl_base,
"Tegra flowctrl not initialised!\n"))
return 0;
return readl(tegra_flowctrl_base + offset);
}
@ -148,13 +156,16 @@ static const struct of_device_id matches[] __initconst = {
{ }
};
void __init tegra_flowctrl_init(void)
static int __init tegra_flowctrl_init(void)
{
/* hardcoded fallback if device tree node is missing */
unsigned long base = 0x60007000;
unsigned long size = SZ_4K;
struct device_node *np;
if (!soc_is_tegra())
return 0;
np = of_find_matching_node(NULL, matches);
if (np) {
struct resource res;
@ -168,4 +179,9 @@ void __init tegra_flowctrl_init(void)
}
tegra_flowctrl_base = ioremap_nocache(base, size);
if (!tegra_flowctrl_base)
return -ENXIO;
return 0;
}
early_initcall(tegra_flowctrl_init);

32
arch/arm/mach-tegra/flowctrl.h → include/soc/tegra/flowctrl.h
View File

@ -1,7 +1,5 @@
/*
* arch/arm/mach-tegra/flowctrl.h
*
* functions and macros to control the flowcontroller
* Functions and macros to control the flowcontroller
*
* Copyright (c) 2010-2012, NVIDIA Corporation. All rights reserved.
*
@ -18,8 +16,8 @@
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef __MACH_TEGRA_FLOWCTRL_H
#define __MACH_TEGRA_FLOWCTRL_H
#ifndef __SOC_TEGRA_FLOWCTRL_H__
#define __SOC_TEGRA_FLOWCTRL_H__
#define FLOW_CTRL_HALT_CPU0_EVENTS 0x0
#define FLOW_CTRL_WAITEVENT (2 << 29)
@ -53,14 +51,32 @@
#define TEGRA30_FLOW_CTRL_CSR_WFI_BITMAP (0xF << 8)
#ifndef __ASSEMBLY__
#ifdef CONFIG_SOC_TEGRA_FLOWCTRL
u32 flowctrl_read_cpu_csr(unsigned int cpuid);
void flowctrl_write_cpu_csr(unsigned int cpuid, u32 value);
void flowctrl_write_cpu_halt(unsigned int cpuid, u32 value);
void flowctrl_cpu_suspend_enter(unsigned int cpuid);
void flowctrl_cpu_suspend_exit(unsigned int cpuid);
#else
static inline u32 flowctrl_read_cpu_csr(unsigned int cpuid)
{
return 0;
}
void tegra_flowctrl_init(void);
#endif
static inline void flowctrl_write_cpu_csr(unsigned int cpuid, u32 value)
{
}
#endif
static inline void flowctrl_write_cpu_halt(unsigned int cpuid, u32 value) {}
static inline void flowctrl_cpu_suspend_enter(unsigned int cpuid)
{
}
static inline void flowctrl_cpu_suspend_exit(unsigned int cpuid)
{
}
#endif /* CONFIG_SOC_TEGRA_FLOWCTRL */
#endif /* __ASSEMBLY */
#endif /* __SOC_TEGRA_FLOWCTRL_H__ */