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* use 'unsigned long' as address supplied to au_write[bwl]()
* remove two already unused and commented structures * added an ULL suffix to several address constants that use bits 35-32 Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Pete Popov
Ralf Baechle
parent
9447cbfc7a
commit
7de8d23287
@ -60,34 +60,34 @@ void static inline au_sync_delay(int ms)
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mdelay(ms);
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}
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void static inline au_writeb(u8 val, int reg)
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void static inline au_writeb(u8 val, unsigned long reg)
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{
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*(volatile u8 *)(reg) = val;
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}
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void static inline au_writew(u16 val, int reg)
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void static inline au_writew(u16 val, unsigned long reg)
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{
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*(volatile u16 *)(reg) = val;
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}
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void static inline au_writel(u32 val, int reg)
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void static inline au_writel(u32 val, unsigned long reg)
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{
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*(volatile u32 *)(reg) = val;
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}
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static inline u8 au_readb(unsigned long port)
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static inline u8 au_readb(unsigned long reg)
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{
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return (*(volatile u8 *)port);
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return (*(volatile u8 *)reg);
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}
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static inline u16 au_readw(unsigned long port)
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static inline u16 au_readw(unsigned long reg)
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{
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return (*(volatile u16 *)port);
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return (*(volatile u16 *)reg);
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}
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static inline u32 au_readl(unsigned long port)
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static inline u32 au_readl(unsigned long reg)
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{
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return (*(volatile u32 *)port);
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return (*(volatile u32 *)reg);
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}
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/* These next three functions should be a generic part of the MIPS
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@ -181,26 +181,6 @@ extern au1xxx_irq_map_t au1xxx_irq_map[];
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#define MEM_SDSLEEP (0x0030)
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#define MEM_SDSMCKE (0x0034)
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#ifndef ASSEMBLER
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/*typedef volatile struct
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{
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uint32 sdmode0;
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uint32 sdmode1;
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uint32 sdmode2;
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uint32 sdaddr0;
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uint32 sdaddr1;
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uint32 sdaddr2;
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uint32 sdrefcfg;
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uint32 sdautoref;
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uint32 sdwrmd0;
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uint32 sdwrmd1;
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uint32 sdwrmd2;
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uint32 sdsleep;
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uint32 sdsmcke;
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} AU1X00_SDRAM;*/
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#endif
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/*
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* MEM_SDMODE register content definitions
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*/
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@ -286,49 +266,6 @@ extern au1xxx_irq_map_t au1xxx_irq_map[];
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#define MEM_SDSREF (0x08D0)
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#define MEM_SDSLEEP MEM_SDSREF
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#ifndef ASSEMBLER
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/*typedef volatile struct
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{
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uint32 sdmode0;
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uint32 reserved0;
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uint32 sdmode1;
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uint32 reserved1;
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uint32 sdmode2;
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uint32 reserved2[3];
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uint32 sdaddr0;
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uint32 reserved3;
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uint32 sdaddr1;
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uint32 reserved4;
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uint32 sdaddr2;
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uint32 reserved5[3];
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uint32 sdconfiga;
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uint32 reserved6;
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uint32 sdconfigb;
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uint32 reserved7;
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uint32 sdstat;
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uint32 reserved8;
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uint32 sderraddr;
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uint32 reserved9;
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uint32 sdstride0;
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uint32 reserved10;
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uint32 sdstride1;
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uint32 reserved11;
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uint32 sdstride2;
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uint32 reserved12[3];
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uint32 sdwrmd0;
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uint32 reserved13;
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uint32 sdwrmd1;
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uint32 reserved14;
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uint32 sdwrmd2;
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uint32 reserved15[11];
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uint32 sdprecmd;
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uint32 reserved16;
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uint32 sdautoref;
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uint32 reserved17;
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uint32 sdsref;
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} AU1550_SDRAM;*/
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#endif
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#endif
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/*
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@ -365,9 +302,9 @@ extern au1xxx_irq_map_t au1xxx_irq_map[];
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#define SSI0_PHYS_ADDR 0x11600000
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#define SSI1_PHYS_ADDR 0x11680000
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#define SYS_PHYS_ADDR 0x11900000
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#define PCMCIA_IO_PHYS_ADDR 0xF00000000
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#define PCMCIA_ATTR_PHYS_ADDR 0xF40000000
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#define PCMCIA_MEM_PHYS_ADDR 0xF80000000
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#define PCMCIA_IO_PHYS_ADDR 0xF00000000ULL
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#define PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL
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#define PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL
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#endif
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/********************************************************************/
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@ -399,13 +336,13 @@ extern au1xxx_irq_map_t au1xxx_irq_map[];
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#define UART3_PHYS_ADDR 0x11400000
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#define GPIO2_PHYS_ADDR 0x11700000
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#define SYS_PHYS_ADDR 0x11900000
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#define PCI_MEM_PHYS_ADDR 0x400000000
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#define PCI_IO_PHYS_ADDR 0x500000000
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#define PCI_CONFIG0_PHYS_ADDR 0x600000000
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#define PCI_CONFIG1_PHYS_ADDR 0x680000000
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#define PCMCIA_IO_PHYS_ADDR 0xF00000000
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#define PCMCIA_ATTR_PHYS_ADDR 0xF40000000
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#define PCMCIA_MEM_PHYS_ADDR 0xF80000000
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#define PCI_MEM_PHYS_ADDR 0x400000000ULL
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#define PCI_IO_PHYS_ADDR 0x500000000ULL
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#define PCI_CONFIG0_PHYS_ADDR 0x600000000ULL
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#define PCI_CONFIG1_PHYS_ADDR 0x680000000ULL
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#define PCMCIA_IO_PHYS_ADDR 0xF00000000ULL
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#define PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL
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#define PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL
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#endif
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/********************************************************************/
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@ -442,9 +379,9 @@ extern au1xxx_irq_map_t au1xxx_irq_map[];
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#define GPIO2_PHYS_ADDR 0x11700000
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#define SYS_PHYS_ADDR 0x11900000
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#define LCD_PHYS_ADDR 0x15000000
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#define PCMCIA_IO_PHYS_ADDR 0xF00000000
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#define PCMCIA_ATTR_PHYS_ADDR 0xF40000000
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#define PCMCIA_MEM_PHYS_ADDR 0xF80000000
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#define PCMCIA_IO_PHYS_ADDR 0xF00000000ULL
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#define PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL
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#define PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL
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#endif
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/***********************************************************************/
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@ -473,13 +410,13 @@ extern au1xxx_irq_map_t au1xxx_irq_map[];
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#define PSC1_PHYS_ADDR 0x11B00000
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#define PSC2_PHYS_ADDR 0x10A00000
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#define PSC3_PHYS_ADDR 0x10B00000
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#define PCI_MEM_PHYS_ADDR 0x400000000
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#define PCI_IO_PHYS_ADDR 0x500000000
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#define PCI_CONFIG0_PHYS_ADDR 0x600000000
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#define PCI_CONFIG1_PHYS_ADDR 0x680000000
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#define PCMCIA_IO_PHYS_ADDR 0xF00000000
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#define PCMCIA_ATTR_PHYS_ADDR 0xF40000000
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#define PCMCIA_MEM_PHYS_ADDR 0xF80000000
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#define PCI_MEM_PHYS_ADDR 0x400000000ULL
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#define PCI_IO_PHYS_ADDR 0x500000000ULL
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#define PCI_CONFIG0_PHYS_ADDR 0x600000000ULL
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#define PCI_CONFIG1_PHYS_ADDR 0x680000000ULL
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#define PCMCIA_IO_PHYS_ADDR 0xF00000000ULL
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#define PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL
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#define PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL
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#endif
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/***********************************************************************/
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@ -500,15 +437,15 @@ extern au1xxx_irq_map_t au1xxx_irq_map[];
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#define DDMA_PHYS_ADDR 0x14002000
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#define PSC0_PHYS_ADDR 0x11A00000
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#define PSC1_PHYS_ADDR 0x11B00000
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#define PCMCIA_IO_PHYS_ADDR 0xF00000000
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#define PCMCIA_ATTR_PHYS_ADDR 0xF40000000
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#define PCMCIA_MEM_PHYS_ADDR 0xF80000000
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#define SD0_PHYS_ADDR 0x10600000
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#define SD1_PHYS_ADDR 0x10680000
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#define LCD_PHYS_ADDR 0x15000000
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#define SWCNT_PHYS_ADDR 0x1110010C
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#define MAEFE_PHYS_ADDR 0x14012000
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#define MAEBE_PHYS_ADDR 0x14010000
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#define PCMCIA_IO_PHYS_ADDR 0xF00000000ULL
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#define PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL
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#define PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL
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#endif
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