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nvc0/vp: initial implementation of engine
Will allow use of the engine if firmware (nvXX_fuc085) provided. Signed-off-by: Maarten Lankhorst <maarten.lankhorst@canonical.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
This commit is contained in:
Maarten Lankhorst
Ben Skeggs
parent
23c14ed2ec
commit
7d8bd91bf4
@ -185,6 +185,7 @@ nouveau-y += core/engine/software/nv10.o
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nouveau-y += core/engine/software/nv50.o
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nouveau-y += core/engine/software/nvc0.o
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nouveau-y += core/engine/vp/nv84.o
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nouveau-y += core/engine/vp/nvc0.o
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nouveau-y += core/engine/vp/nve0.o
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# drm/core
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110
drivers/gpu/drm/nouveau/core/engine/vp/nvc0.c
Normal file
110
drivers/gpu/drm/nouveau/core/engine/vp/nvc0.c
Normal file
@ -0,0 +1,110 @@
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/*
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* Copyright 2012 Maarten Lankhorst
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Maarten Lankhorst
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*/
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#include <core/falcon.h>
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#include <engine/vp.h>
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struct nvc0_vp_priv {
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struct nouveau_falcon base;
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};
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/*******************************************************************************
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* VP object classes
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******************************************************************************/
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static struct nouveau_oclass
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nvc0_vp_sclass[] = {
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{ 0x90b2, &nouveau_object_ofuncs },
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{},
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};
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/*******************************************************************************
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* PVP context
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******************************************************************************/
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static struct nouveau_oclass
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nvc0_vp_cclass = {
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.handle = NV_ENGCTX(VP, 0xc0),
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.ofuncs = &(struct nouveau_ofuncs) {
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.ctor = _nouveau_falcon_context_ctor,
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.dtor = _nouveau_falcon_context_dtor,
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.init = _nouveau_falcon_context_init,
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.fini = _nouveau_falcon_context_fini,
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.rd32 = _nouveau_falcon_context_rd32,
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.wr32 = _nouveau_falcon_context_wr32,
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},
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};
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/*******************************************************************************
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* PVP engine/subdev functions
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******************************************************************************/
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static int
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nvc0_vp_init(struct nouveau_object *object)
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{
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struct nvc0_vp_priv *priv = (void *)object;
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int ret;
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ret = nouveau_falcon_init(&priv->base);
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if (ret)
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return ret;
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nv_wr32(priv, 0x085010, 0x0000fff2);
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nv_wr32(priv, 0x08501c, 0x0000fff2);
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return 0;
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}
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static int
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nvc0_vp_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
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struct nouveau_oclass *oclass, void *data, u32 size,
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struct nouveau_object **pobject)
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{
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struct nvc0_vp_priv *priv;
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int ret;
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ret = nouveau_falcon_create(parent, engine, oclass, 0x085000, true,
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"PVP", "vp", &priv);
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*pobject = nv_object(priv);
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if (ret)
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return ret;
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nv_subdev(priv)->unit = 0x00020000;
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nv_engine(priv)->cclass = &nvc0_vp_cclass;
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nv_engine(priv)->sclass = nvc0_vp_sclass;
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return 0;
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}
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struct nouveau_oclass
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nvc0_vp_oclass = {
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.handle = NV_ENGINE(VP, 0xc0),
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.ofuncs = &(struct nouveau_ofuncs) {
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.ctor = nvc0_vp_ctor,
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.dtor = _nouveau_falcon_dtor,
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.init = nvc0_vp_init,
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.fini = _nouveau_falcon_fini,
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.rd32 = _nouveau_falcon_rd32,
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.wr32 = _nouveau_falcon_wr32,
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},
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};
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@ -2,6 +2,7 @@
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#define __NOUVEAU_VP_H__
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extern struct nouveau_oclass nv84_vp_oclass;
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extern struct nouveau_oclass nvc0_vp_oclass;
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extern struct nouveau_oclass nve0_vp_oclass;
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#endif
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@ -74,7 +74,7 @@ nvc0_identify(struct nouveau_device *device)
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device->oclass[NVDEV_ENGINE_FIFO ] = &nvc0_fifo_oclass;
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device->oclass[NVDEV_ENGINE_SW ] = &nvc0_software_oclass;
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device->oclass[NVDEV_ENGINE_GR ] = &nvc0_graph_oclass;
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device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass;
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device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass;
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device->oclass[NVDEV_ENGINE_BSP ] = &nvc0_bsp_oclass;
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device->oclass[NVDEV_ENGINE_PPP ] = &nv98_ppp_oclass;
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device->oclass[NVDEV_ENGINE_COPY0 ] = &nvc0_copy0_oclass;
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@ -102,7 +102,7 @@ nvc0_identify(struct nouveau_device *device)
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device->oclass[NVDEV_ENGINE_FIFO ] = &nvc0_fifo_oclass;
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device->oclass[NVDEV_ENGINE_SW ] = &nvc0_software_oclass;
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device->oclass[NVDEV_ENGINE_GR ] = &nvc0_graph_oclass;
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device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass;
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device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass;
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device->oclass[NVDEV_ENGINE_BSP ] = &nvc0_bsp_oclass;
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device->oclass[NVDEV_ENGINE_PPP ] = &nv98_ppp_oclass;
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device->oclass[NVDEV_ENGINE_COPY0 ] = &nvc0_copy0_oclass;
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@ -130,7 +130,7 @@ nvc0_identify(struct nouveau_device *device)
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device->oclass[NVDEV_ENGINE_FIFO ] = &nvc0_fifo_oclass;
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device->oclass[NVDEV_ENGINE_SW ] = &nvc0_software_oclass;
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device->oclass[NVDEV_ENGINE_GR ] = &nvc0_graph_oclass;
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device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass;
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device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass;
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device->oclass[NVDEV_ENGINE_BSP ] = &nvc0_bsp_oclass;
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device->oclass[NVDEV_ENGINE_PPP ] = &nv98_ppp_oclass;
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device->oclass[NVDEV_ENGINE_COPY0 ] = &nvc0_copy0_oclass;
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@ -158,7 +158,7 @@ nvc0_identify(struct nouveau_device *device)
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device->oclass[NVDEV_ENGINE_FIFO ] = &nvc0_fifo_oclass;
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device->oclass[NVDEV_ENGINE_SW ] = &nvc0_software_oclass;
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device->oclass[NVDEV_ENGINE_GR ] = &nvc0_graph_oclass;
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device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass;
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device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass;
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device->oclass[NVDEV_ENGINE_BSP ] = &nvc0_bsp_oclass;
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device->oclass[NVDEV_ENGINE_PPP ] = &nv98_ppp_oclass;
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device->oclass[NVDEV_ENGINE_COPY0 ] = &nvc0_copy0_oclass;
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@ -186,7 +186,7 @@ nvc0_identify(struct nouveau_device *device)
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device->oclass[NVDEV_ENGINE_FIFO ] = &nvc0_fifo_oclass;
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device->oclass[NVDEV_ENGINE_SW ] = &nvc0_software_oclass;
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device->oclass[NVDEV_ENGINE_GR ] = &nvc0_graph_oclass;
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device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass;
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device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass;
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device->oclass[NVDEV_ENGINE_BSP ] = &nvc0_bsp_oclass;
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device->oclass[NVDEV_ENGINE_PPP ] = &nv98_ppp_oclass;
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device->oclass[NVDEV_ENGINE_COPY0 ] = &nvc0_copy0_oclass;
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@ -214,7 +214,7 @@ nvc0_identify(struct nouveau_device *device)
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device->oclass[NVDEV_ENGINE_FIFO ] = &nvc0_fifo_oclass;
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device->oclass[NVDEV_ENGINE_SW ] = &nvc0_software_oclass;
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device->oclass[NVDEV_ENGINE_GR ] = &nvc0_graph_oclass;
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device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass;
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device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass;
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device->oclass[NVDEV_ENGINE_BSP ] = &nvc0_bsp_oclass;
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device->oclass[NVDEV_ENGINE_PPP ] = &nv98_ppp_oclass;
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device->oclass[NVDEV_ENGINE_COPY0 ] = &nvc0_copy0_oclass;
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@ -242,7 +242,7 @@ nvc0_identify(struct nouveau_device *device)
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device->oclass[NVDEV_ENGINE_FIFO ] = &nvc0_fifo_oclass;
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device->oclass[NVDEV_ENGINE_SW ] = &nvc0_software_oclass;
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device->oclass[NVDEV_ENGINE_GR ] = &nvc0_graph_oclass;
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device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass;
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device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass;
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device->oclass[NVDEV_ENGINE_BSP ] = &nvc0_bsp_oclass;
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device->oclass[NVDEV_ENGINE_PPP ] = &nv98_ppp_oclass;
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device->oclass[NVDEV_ENGINE_COPY0 ] = &nvc0_copy0_oclass;
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@ -270,7 +270,7 @@ nvc0_identify(struct nouveau_device *device)
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device->oclass[NVDEV_ENGINE_FIFO ] = &nvc0_fifo_oclass;
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device->oclass[NVDEV_ENGINE_SW ] = &nvc0_software_oclass;
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device->oclass[NVDEV_ENGINE_GR ] = &nvc0_graph_oclass;
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device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass;
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device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass;
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device->oclass[NVDEV_ENGINE_BSP ] = &nvc0_bsp_oclass;
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device->oclass[NVDEV_ENGINE_PPP ] = &nv98_ppp_oclass;
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device->oclass[NVDEV_ENGINE_COPY0 ] = &nvc0_copy0_oclass;
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