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[POWERPC] cell: Generalize io-workarounds code
This splits cell io-workaround code into spider-pci dependent code and a generic part, and also moves io-workarounds initialization into cell_setup_phb. Signed-off-by: Kou Ishizaki <kou.ishizaki@toshiba.co.jp> Acked-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
This commit is contained in:
Ishizaki Kou
Paul Mackerras
parent
36f8a2c4c6
commit
7cfb62a2e8
@ -275,6 +275,8 @@ static int __devinit of_pci_phb_probe(struct of_device *dev,
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/* Scan the bus */
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scan_phb(phb);
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if (phb->bus == NULL)
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return -ENXIO;
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/* Claim resources. This might need some rework as well depending
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* wether we are doing probe-only or not, like assigning unassigned
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@ -1,6 +1,7 @@
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obj-$(CONFIG_PPC_CELL_NATIVE) += interrupt.o iommu.o setup.o \
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cbe_regs.o spider-pic.o \
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pervasive.o pmu.o io-workarounds.o
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pervasive.o pmu.o io-workarounds.o \
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spider-pci.o
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obj-$(CONFIG_CBE_RAS) += ras.o
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obj-$(CONFIG_CBE_THERM) += cbe_thermal.o
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@ -1,6 +1,9 @@
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/*
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* Support PCI IO workaround
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*
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* Copyright (C) 2006 Benjamin Herrenschmidt <benh@kernel.crashing.org>
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* IBM, Corp.
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* (C) Copyright 2007-2008 TOSHIBA CORPORATION
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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@ -9,335 +12,174 @@
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#undef DEBUG
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#include <linux/kernel.h>
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#include <linux/mm.h>
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#include <linux/pci.h>
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#include <asm/io.h>
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#include <asm/machdep.h>
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#include <asm/pci-bridge.h>
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#include <asm/pgtable.h>
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#include <asm/ppc-pci.h>
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#include "io-workarounds.h"
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#define SPIDER_PCI_REG_BASE 0xd000
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#define SPIDER_PCI_VCI_CNTL_STAT 0x0110
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#define SPIDER_PCI_DUMMY_READ 0x0810
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#define SPIDER_PCI_DUMMY_READ_BASE 0x0814
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#define IOWA_MAX_BUS 8
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/* Undefine that to re-enable bogus prefetch
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*
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* Without that workaround, the chip will do bogus prefetch past
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* page boundary from system memory. This setting will disable that,
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* though the documentation is unclear as to the consequences of doing
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* so, either purely performances, or possible misbehaviour... It's not
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* clear wether the chip can handle unaligned accesses at all without
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* prefetching enabled.
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*
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* For now, things appear to be behaving properly with that prefetching
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* disabled and IDE, possibly because IDE isn't doing any unaligned
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* access.
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*/
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#define SPIDER_DISABLE_PREFETCH
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static struct iowa_bus iowa_busses[IOWA_MAX_BUS];
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static unsigned int iowa_bus_count;
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#define MAX_SPIDERS 3
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static struct spider_pci_bus {
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void __iomem *regs;
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unsigned long mmio_start;
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unsigned long mmio_end;
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unsigned long pio_vstart;
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unsigned long pio_vend;
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} spider_pci_busses[MAX_SPIDERS];
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static int spider_pci_count;
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static struct spider_pci_bus *spider_pci_find(unsigned long vaddr,
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unsigned long paddr)
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static struct iowa_bus *iowa_pci_find(unsigned long vaddr, unsigned long paddr)
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{
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int i;
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int i, j;
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struct resource *res;
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unsigned long vstart, vend;
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for (i = 0; i < spider_pci_count; i++) {
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struct spider_pci_bus *bus = &spider_pci_busses[i];
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if (paddr && paddr >= bus->mmio_start && paddr < bus->mmio_end)
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return bus;
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if (vaddr && vaddr >= bus->pio_vstart && vaddr < bus->pio_vend)
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return bus;
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for (i = 0; i < iowa_bus_count; i++) {
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struct iowa_bus *bus = &iowa_busses[i];
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struct pci_controller *phb = bus->phb;
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if (vaddr) {
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vstart = (unsigned long)phb->io_base_virt;
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vend = vstart + phb->pci_io_size - 1;
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if ((vaddr >= vstart) && (vaddr <= vend))
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return bus;
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}
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if (paddr)
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for (j = 0; j < 3; j++) {
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res = &phb->mem_resources[j];
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if (paddr >= res->start && paddr <= res->end)
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return bus;
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}
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}
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return NULL;
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}
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static void spider_io_flush(const volatile void __iomem *addr)
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struct iowa_bus *iowa_mem_find_bus(const PCI_IO_ADDR addr)
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{
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struct spider_pci_bus *bus;
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struct iowa_bus *bus;
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int token;
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/* Get platform token (set by ioremap) from address */
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token = PCI_GET_ADDR_TOKEN(addr);
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/* Fast path if we have a non-0 token, it indicates which bus we
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* are on.
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*
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* If the token is 0, that means either that the ioremap was done
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* before we initialized this layer, or it's a PIO operation. We
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* fallback to a low path in this case. Hopefully, internal devices
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* which are ioremap'ed early should use in_XX/out_XX functions
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* instead of the PCI ones and thus not suffer from the slowdown.
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*
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* Also note that currently, the workaround will not work for areas
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* that are not mapped with PTEs (bolted in the hash table). This
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* is the case for ioremaps done very early at boot (before
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* mem_init_done) and includes the mapping of the ISA IO space.
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*
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* Fortunately, none of the affected devices is expected to do DMA
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* and thus there should be no problem in practice.
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*
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* In order to improve performances, we only do the PTE search for
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* addresses falling in the PHB IO space area. That means it will
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* not work for hotplug'ed PHBs but those don't exist with Spider.
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*/
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if (token && token <= spider_pci_count)
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bus = &spider_pci_busses[token - 1];
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if (token && token <= iowa_bus_count)
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bus = &iowa_busses[token - 1];
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else {
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unsigned long vaddr, paddr;
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pte_t *ptep;
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/* Fixup physical address */
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vaddr = (unsigned long)PCI_FIX_ADDR(addr);
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if (vaddr < PHB_IO_BASE || vaddr >= PHB_IO_END)
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return NULL;
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/* Check if it's in allowed range for PIO */
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if (vaddr < PHB_IO_BASE || vaddr > PHB_IO_END)
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return;
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/* Try to find a PTE. If not, clear the paddr, we'll do
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* a vaddr only lookup (PIO only)
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*/
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ptep = find_linux_pte(init_mm.pgd, vaddr);
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if (ptep == NULL)
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paddr = 0;
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else
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paddr = pte_pfn(*ptep) << PAGE_SHIFT;
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bus = iowa_pci_find(vaddr, paddr);
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bus = spider_pci_find(vaddr, paddr);
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if (bus == NULL)
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return;
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return NULL;
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}
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/* Now do the workaround
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*/
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(void)in_be32(bus->regs + SPIDER_PCI_DUMMY_READ);
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return bus;
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}
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static u8 spider_readb(const volatile void __iomem *addr)
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struct iowa_bus *iowa_pio_find_bus(unsigned long port)
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{
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u8 val = __do_readb(addr);
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spider_io_flush(addr);
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return val;
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}
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static u16 spider_readw(const volatile void __iomem *addr)
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{
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u16 val = __do_readw(addr);
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spider_io_flush(addr);
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return val;
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}
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static u32 spider_readl(const volatile void __iomem *addr)
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{
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u32 val = __do_readl(addr);
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spider_io_flush(addr);
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return val;
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}
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static u64 spider_readq(const volatile void __iomem *addr)
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{
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u64 val = __do_readq(addr);
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spider_io_flush(addr);
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return val;
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}
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static u16 spider_readw_be(const volatile void __iomem *addr)
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{
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u16 val = __do_readw_be(addr);
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spider_io_flush(addr);
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return val;
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}
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static u32 spider_readl_be(const volatile void __iomem *addr)
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{
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u32 val = __do_readl_be(addr);
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spider_io_flush(addr);
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return val;
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}
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static u64 spider_readq_be(const volatile void __iomem *addr)
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{
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u64 val = __do_readq_be(addr);
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spider_io_flush(addr);
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return val;
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}
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static void spider_readsb(const volatile void __iomem *addr, void *buf,
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unsigned long count)
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{
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__do_readsb(addr, buf, count);
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spider_io_flush(addr);
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}
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static void spider_readsw(const volatile void __iomem *addr, void *buf,
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unsigned long count)
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{
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__do_readsw(addr, buf, count);
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spider_io_flush(addr);
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}
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static void spider_readsl(const volatile void __iomem *addr, void *buf,
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unsigned long count)
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{
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__do_readsl(addr, buf, count);
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spider_io_flush(addr);
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}
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static void spider_memcpy_fromio(void *dest, const volatile void __iomem *src,
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unsigned long n)
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{
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__do_memcpy_fromio(dest, src, n);
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spider_io_flush(src);
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unsigned long vaddr = (unsigned long)pci_io_base + port;
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return iowa_pci_find(vaddr, 0);
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}
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static void __iomem * spider_ioremap(unsigned long addr, unsigned long size,
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unsigned long flags)
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#define DEF_PCI_AC_RET(name, ret, at, al, space, aa) \
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static ret iowa_##name at \
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{ \
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struct iowa_bus *bus; \
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bus = iowa_##space##_find_bus(aa); \
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if (bus && bus->ops && bus->ops->name) \
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return bus->ops->name al; \
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return __do_##name al; \
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}
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#define DEF_PCI_AC_NORET(name, at, al, space, aa) \
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static void iowa_##name at \
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{ \
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struct iowa_bus *bus; \
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bus = iowa_##space##_find_bus(aa); \
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if (bus && bus->ops && bus->ops->name) { \
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bus->ops->name al; \
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return; \
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} \
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__do_##name al; \
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}
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#include <asm/io-defs.h>
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#undef DEF_PCI_AC_RET
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#undef DEF_PCI_AC_NORET
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static struct ppc_pci_io __initdata iowa_pci_io = {
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#define DEF_PCI_AC_RET(name, ret, at, al, space, aa) .name = iowa_##name,
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#define DEF_PCI_AC_NORET(name, at, al, space, aa) .name = iowa_##name,
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#include <asm/io-defs.h>
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#undef DEF_PCI_AC_RET
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#undef DEF_PCI_AC_NORET
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};
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static void __iomem *iowa_ioremap(unsigned long addr, unsigned long size,
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unsigned long flags)
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{
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struct spider_pci_bus *bus;
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struct iowa_bus *bus;
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void __iomem *res = __ioremap(addr, size, flags);
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int busno;
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pr_debug("spider_ioremap(0x%lx, 0x%lx, 0x%lx) -> 0x%p\n",
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addr, size, flags, res);
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bus = spider_pci_find(0, addr);
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bus = iowa_pci_find(0, addr);
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if (bus != NULL) {
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busno = bus - spider_pci_busses;
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pr_debug(" found bus %d, setting token\n", busno);
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busno = bus - iowa_busses;
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PCI_SET_ADDR_TOKEN(res, busno + 1);
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}
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pr_debug(" result=0x%p\n", res);
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return res;
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}
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static void __init spider_pci_setup_chip(struct spider_pci_bus *bus)
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/* Regist new bus to support workaround */
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void __init iowa_register_bus(struct pci_controller *phb,
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struct ppc_pci_io *ops,
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int (*initfunc)(struct iowa_bus *, void *), void *data)
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{
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#ifdef SPIDER_DISABLE_PREFETCH
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u32 val = in_be32(bus->regs + SPIDER_PCI_VCI_CNTL_STAT);
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pr_debug(" PVCI_Control_Status was 0x%08x\n", val);
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out_be32(bus->regs + SPIDER_PCI_VCI_CNTL_STAT, val | 0x8);
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#endif
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/* Configure the dummy address for the workaround */
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out_be32(bus->regs + SPIDER_PCI_DUMMY_READ_BASE, 0x80000000);
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}
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static void __init spider_pci_add_one(struct pci_controller *phb)
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{
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struct spider_pci_bus *bus = &spider_pci_busses[spider_pci_count];
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struct iowa_bus *bus;
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struct device_node *np = phb->dn;
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struct resource rsrc;
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void __iomem *regs;
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if (spider_pci_count >= MAX_SPIDERS) {
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printk(KERN_ERR "Too many spider bridges, workarounds"
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" disabled for %s\n", np->full_name);
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if (iowa_bus_count >= IOWA_MAX_BUS) {
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pr_err("IOWA:Too many pci bridges, "
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"workarounds disabled for %s\n", np->full_name);
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return;
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}
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/* Get the registers for the beast */
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if (of_address_to_resource(np, 0, &rsrc)) {
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printk(KERN_ERR "Failed to get registers for spider %s"
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" workarounds disabled\n", np->full_name);
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return;
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}
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bus = &iowa_busses[iowa_bus_count];
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bus->phb = phb;
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bus->ops = ops;
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/* Mask out some useless bits in there to get to the base of the
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* spider chip
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*/
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rsrc.start &= ~0xfffffffful;
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if (initfunc)
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if ((*initfunc)(bus, data))
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return;
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/* Map them */
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regs = ioremap(rsrc.start + SPIDER_PCI_REG_BASE, 0x1000);
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if (regs == NULL) {
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printk(KERN_ERR "Failed to map registers for spider %s"
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" workarounds disabled\n", np->full_name);
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return;
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}
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iowa_bus_count++;
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spider_pci_count++;
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/* We assume spiders only have one MMIO resource */
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bus->mmio_start = phb->mem_resources[0].start;
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bus->mmio_end = phb->mem_resources[0].end + 1;
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bus->pio_vstart = (unsigned long)phb->io_base_virt;
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bus->pio_vend = bus->pio_vstart + phb->pci_io_size;
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bus->regs = regs;
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printk(KERN_INFO "PCI: Spider MMIO workaround for %s\n",np->full_name);
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pr_debug(" mmio (P) = 0x%016lx..0x%016lx\n",
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bus->mmio_start, bus->mmio_end);
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pr_debug(" pio (V) = 0x%016lx..0x%016lx\n",
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bus->pio_vstart, bus->pio_vend);
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pr_debug(" regs (P) = 0x%016lx (V) = 0x%p\n",
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rsrc.start + SPIDER_PCI_REG_BASE, bus->regs);
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spider_pci_setup_chip(bus);
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pr_debug("IOWA:[%d]Add bus, %s.\n", iowa_bus_count-1, np->full_name);
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}
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static struct ppc_pci_io __initdata spider_pci_io = {
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.readb = spider_readb,
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.readw = spider_readw,
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.readl = spider_readl,
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.readq = spider_readq,
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.readw_be = spider_readw_be,
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.readl_be = spider_readl_be,
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.readq_be = spider_readq_be,
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.readsb = spider_readsb,
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.readsw = spider_readsw,
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.readsl = spider_readsl,
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.memcpy_fromio = spider_memcpy_fromio,
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};
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static int __init spider_pci_workaround_init(void)
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/* enable IO workaround */
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void __init io_workaround_init(void)
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{
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struct pci_controller *phb;
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static int io_workaround_inited;
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/* Find spider bridges. We assume they have been all probed
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* in setup_arch(). If that was to change, we would need to
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* update this code to cope with dynamically added busses
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*/
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list_for_each_entry(phb, &hose_list, list_node) {
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struct device_node *np = phb->dn;
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const char *model = of_get_property(np, "model", NULL);
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/* If no model property or name isn't exactly "pci", skip */
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if (model == NULL || strcmp(np->name, "pci"))
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continue;
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/* If model is not "Spider", skip */
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if (strcmp(model, "Spider"))
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||||
continue;
|
||||
spider_pci_add_one(phb);
|
||||
}
|
||||
|
||||
/* No Spider PCI found, exit */
|
||||
if (spider_pci_count == 0)
|
||||
return 0;
|
||||
|
||||
/* Setup IO callbacks. We only setup MMIO reads. PIO reads will
|
||||
* fallback to MMIO reads (though without a token, thus slower)
|
||||
*/
|
||||
ppc_pci_io = spider_pci_io;
|
||||
|
||||
/* Setup ioremap callback */
|
||||
ppc_md.ioremap = spider_ioremap;
|
||||
|
||||
return 0;
|
||||
if (io_workaround_inited)
|
||||
return;
|
||||
ppc_pci_io = iowa_pci_io;
|
||||
ppc_md.ioremap = iowa_ioremap;
|
||||
io_workaround_inited = 1;
|
||||
}
|
||||
machine_arch_initcall(cell, spider_pci_workaround_init);
|
||||
|
||||
49
arch/powerpc/platforms/cell/io-workarounds.h
Normal file
49
arch/powerpc/platforms/cell/io-workarounds.h
Normal file
@ -0,0 +1,49 @@
|
||||
/*
|
||||
* Support PCI IO workaround
|
||||
*
|
||||
* (C) Copyright 2007-2008 TOSHIBA CORPORATION
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along
|
||||
* with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
|
||||
*/
|
||||
|
||||
#ifndef _IO_WORKAROUNDS_H
|
||||
#define _IO_WORKAROUNDS_H
|
||||
|
||||
#include <linux/io.h>
|
||||
#include <asm/pci-bridge.h>
|
||||
|
||||
/* Bus info */
|
||||
struct iowa_bus {
|
||||
struct pci_controller *phb;
|
||||
struct ppc_pci_io *ops;
|
||||
void *private;
|
||||
};
|
||||
|
||||
void __init io_workaround_init(void);
|
||||
void __init iowa_register_bus(struct pci_controller *, struct ppc_pci_io *,
|
||||
int (*)(struct iowa_bus *, void *), void *);
|
||||
struct iowa_bus *iowa_mem_find_bus(const PCI_IO_ADDR);
|
||||
struct iowa_bus *iowa_pio_find_bus(unsigned long);
|
||||
|
||||
extern struct ppc_pci_io spiderpci_ops;
|
||||
extern int spiderpci_iowa_init(struct iowa_bus *, void *);
|
||||
|
||||
#define SPIDER_PCI_REG_BASE 0xd000
|
||||
#define SPIDER_PCI_REG_SIZE 0x1000
|
||||
#define SPIDER_PCI_VCI_CNTL_STAT 0x0110
|
||||
#define SPIDER_PCI_DUMMY_READ 0x0810
|
||||
#define SPIDER_PCI_DUMMY_READ_BASE 0x0814
|
||||
|
||||
#endif /* _IO_WORKAROUNDS_H */
|
||||
@ -57,6 +57,7 @@
|
||||
#include "interrupt.h"
|
||||
#include "pervasive.h"
|
||||
#include "ras.h"
|
||||
#include "io-workarounds.h"
|
||||
|
||||
#ifdef DEBUG
|
||||
#define DBG(fmt...) udbg_printf(fmt)
|
||||
@ -117,13 +118,50 @@ static void cell_fixup_pcie_rootcomplex(struct pci_dev *dev)
|
||||
}
|
||||
DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, cell_fixup_pcie_rootcomplex);
|
||||
|
||||
static int __devinit cell_setup_phb(struct pci_controller *phb)
|
||||
{
|
||||
const char *model;
|
||||
struct device_node *np;
|
||||
|
||||
int rc = rtas_setup_phb(phb);
|
||||
if (rc)
|
||||
return rc;
|
||||
|
||||
np = phb->dn;
|
||||
model = of_get_property(np, "model", NULL);
|
||||
if (model == NULL || strcmp(np->name, "pci"))
|
||||
return 0;
|
||||
|
||||
/* Setup workarounds for spider */
|
||||
if (strcmp(model, "Spider"))
|
||||
return 0;
|
||||
|
||||
iowa_register_bus(phb, &spiderpci_ops, &spiderpci_iowa_init,
|
||||
(void *)SPIDER_PCI_REG_BASE);
|
||||
io_workaround_init();
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int __init cell_publish_devices(void)
|
||||
{
|
||||
struct device_node *root = of_find_node_by_path("/");
|
||||
struct device_node *np;
|
||||
int node;
|
||||
|
||||
/* Publish OF platform devices for southbridge IOs */
|
||||
of_platform_bus_probe(NULL, NULL, NULL);
|
||||
|
||||
/* On spider based blades, we need to manually create the OF
|
||||
* platform devices for the PCI host bridges
|
||||
*/
|
||||
for_each_child_of_node(root, np) {
|
||||
if (np->type == NULL || (strcmp(np->type, "pci") != 0 &&
|
||||
strcmp(np->type, "pciex") != 0))
|
||||
continue;
|
||||
of_platform_device_create(np, NULL, NULL);
|
||||
}
|
||||
|
||||
/* There is no device for the MIC memory controller, thus we create
|
||||
* a platform device for it to attach the EDAC driver to.
|
||||
*/
|
||||
@ -132,6 +170,7 @@ static int __init cell_publish_devices(void)
|
||||
continue;
|
||||
platform_device_register_simple("cbe-mic", node, NULL, 0);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
machine_subsys_initcall(cell, cell_publish_devices);
|
||||
@ -213,7 +252,7 @@ static void __init cell_setup_arch(void)
|
||||
|
||||
/* Find and initialize PCI host bridges */
|
||||
init_pci_config_tokens();
|
||||
find_and_init_phbs();
|
||||
|
||||
cbe_pervasive_init();
|
||||
#ifdef CONFIG_DUMMY_CONSOLE
|
||||
conswitchp = &dummy_con;
|
||||
@ -249,7 +288,7 @@ define_machine(cell) {
|
||||
.calibrate_decr = generic_calibrate_decr,
|
||||
.progress = cell_progress,
|
||||
.init_IRQ = cell_init_irq,
|
||||
.pci_setup_phb = rtas_setup_phb,
|
||||
.pci_setup_phb = cell_setup_phb,
|
||||
#ifdef CONFIG_KEXEC
|
||||
.machine_kexec = default_machine_kexec,
|
||||
.machine_kexec_prepare = default_machine_kexec_prepare,
|
||||
|
||||
184
arch/powerpc/platforms/cell/spider-pci.c
Normal file
184
arch/powerpc/platforms/cell/spider-pci.c
Normal file
@ -0,0 +1,184 @@
|
||||
/*
|
||||
* IO workarounds for PCI on Celleb/Cell platform
|
||||
*
|
||||
* (C) Copyright 2006-2007 TOSHIBA CORPORATION
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along
|
||||
* with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
|
||||
*/
|
||||
|
||||
#undef DEBUG
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/of_platform.h>
|
||||
#include <linux/io.h>
|
||||
|
||||
#include <asm/ppc-pci.h>
|
||||
#include <asm/pci-bridge.h>
|
||||
|
||||
#include "io-workarounds.h"
|
||||
|
||||
#define SPIDER_PCI_DISABLE_PREFETCH
|
||||
|
||||
struct spiderpci_iowa_private {
|
||||
void __iomem *regs;
|
||||
};
|
||||
|
||||
static void spiderpci_io_flush(struct iowa_bus *bus)
|
||||
{
|
||||
struct spiderpci_iowa_private *priv;
|
||||
u32 val;
|
||||
|
||||
priv = bus->private;
|
||||
val = in_be32(priv->regs + SPIDER_PCI_DUMMY_READ);
|
||||
iosync();
|
||||
}
|
||||
|
||||
#define SPIDER_PCI_MMIO_READ(name, ret) \
|
||||
static ret spiderpci_##name(const PCI_IO_ADDR addr) \
|
||||
{ \
|
||||
ret val = __do_##name(addr); \
|
||||
spiderpci_io_flush(iowa_mem_find_bus(addr)); \
|
||||
return val; \
|
||||
}
|
||||
|
||||
#define SPIDER_PCI_MMIO_READ_STR(name) \
|
||||
static void spiderpci_##name(const PCI_IO_ADDR addr, void *buf, \
|
||||
unsigned long count) \
|
||||
{ \
|
||||
__do_##name(addr, buf, count); \
|
||||
spiderpci_io_flush(iowa_mem_find_bus(addr)); \
|
||||
}
|
||||
|
||||
SPIDER_PCI_MMIO_READ(readb, u8)
|
||||
SPIDER_PCI_MMIO_READ(readw, u16)
|
||||
SPIDER_PCI_MMIO_READ(readl, u32)
|
||||
SPIDER_PCI_MMIO_READ(readq, u64)
|
||||
SPIDER_PCI_MMIO_READ(readw_be, u16)
|
||||
SPIDER_PCI_MMIO_READ(readl_be, u32)
|
||||
SPIDER_PCI_MMIO_READ(readq_be, u64)
|
||||
SPIDER_PCI_MMIO_READ_STR(readsb)
|
||||
SPIDER_PCI_MMIO_READ_STR(readsw)
|
||||
SPIDER_PCI_MMIO_READ_STR(readsl)
|
||||
|
||||
static void spiderpci_memcpy_fromio(void *dest, const PCI_IO_ADDR src,
|
||||
unsigned long n)
|
||||
{
|
||||
__do_memcpy_fromio(dest, src, n);
|
||||
spiderpci_io_flush(iowa_mem_find_bus(src));
|
||||
}
|
||||
|
||||
static int __init spiderpci_pci_setup_chip(struct pci_controller *phb,
|
||||
void __iomem *regs)
|
||||
{
|
||||
void *dummy_page_va;
|
||||
dma_addr_t dummy_page_da;
|
||||
|
||||
#ifdef SPIDER_PCI_DISABLE_PREFETCH
|
||||
u32 val = in_be32(regs + SPIDER_PCI_VCI_CNTL_STAT);
|
||||
pr_debug("SPIDER_IOWA:PVCI_Control_Status was 0x%08x\n", val);
|
||||
out_be32(regs + SPIDER_PCI_VCI_CNTL_STAT, val | 0x8);
|
||||
#endif /* SPIDER_PCI_DISABLE_PREFETCH */
|
||||
|
||||
/* setup dummy read */
|
||||
/*
|
||||
* On CellBlade, we can't know that which XDR memory is used by
|
||||
* kmalloc() to allocate dummy_page_va.
|
||||
* In order to imporve the performance, the XDR which is used to
|
||||
* allocate dummy_page_va is the nearest the spider-pci.
|
||||
* We have to select the CBE which is the nearest the spider-pci
|
||||
* to allocate memory from the best XDR, but I don't know that
|
||||
* how to do.
|
||||
*
|
||||
* Celleb does not have this problem, because it has only one XDR.
|
||||
*/
|
||||
dummy_page_va = kmalloc(PAGE_SIZE, GFP_KERNEL);
|
||||
if (!dummy_page_va) {
|
||||
pr_err("SPIDERPCI-IOWA:Alloc dummy_page_va failed.\n");
|
||||
return -1;
|
||||
}
|
||||
|
||||
dummy_page_da = dma_map_single(phb->parent, dummy_page_va,
|
||||
PAGE_SIZE, DMA_FROM_DEVICE);
|
||||
if (dma_mapping_error(dummy_page_da)) {
|
||||
pr_err("SPIDER-IOWA:Map dummy page filed.\n");
|
||||
kfree(dummy_page_va);
|
||||
return -1;
|
||||
}
|
||||
|
||||
out_be32(regs + SPIDER_PCI_DUMMY_READ_BASE, dummy_page_da);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int __init spiderpci_iowa_init(struct iowa_bus *bus, void *data)
|
||||
{
|
||||
void __iomem *regs = NULL;
|
||||
struct spiderpci_iowa_private *priv;
|
||||
struct device_node *np = bus->phb->dn;
|
||||
struct resource r;
|
||||
unsigned long offset = (unsigned long)data;
|
||||
|
||||
pr_debug("SPIDERPCI-IOWA:Bus initialize for spider(%s)\n",
|
||||
np->full_name);
|
||||
|
||||
priv = kzalloc(sizeof(struct spiderpci_iowa_private), GFP_KERNEL);
|
||||
if (!priv) {
|
||||
pr_err("SPIDERPCI-IOWA:"
|
||||
"Can't allocate struct spiderpci_iowa_private");
|
||||
return -1;
|
||||
}
|
||||
|
||||
if (of_address_to_resource(np, 0, &r)) {
|
||||
pr_err("SPIDERPCI-IOWA:Can't get resource.\n");
|
||||
goto error;
|
||||
}
|
||||
|
||||
regs = ioremap(r.start + offset, SPIDER_PCI_REG_SIZE);
|
||||
if (!regs) {
|
||||
pr_err("SPIDERPCI-IOWA:ioremap failed.\n");
|
||||
goto error;
|
||||
}
|
||||
priv->regs = regs;
|
||||
bus->private = priv;
|
||||
|
||||
if (spiderpci_pci_setup_chip(bus->phb, regs))
|
||||
goto error;
|
||||
|
||||
return 0;
|
||||
|
||||
error:
|
||||
kfree(priv);
|
||||
bus->private = NULL;
|
||||
|
||||
if (regs)
|
||||
iounmap(regs);
|
||||
|
||||
return -1;
|
||||
}
|
||||
|
||||
struct ppc_pci_io spiderpci_ops = {
|
||||
.readb = spiderpci_readb,
|
||||
.readw = spiderpci_readw,
|
||||
.readl = spiderpci_readl,
|
||||
.readq = spiderpci_readq,
|
||||
.readw_be = spiderpci_readw_be,
|
||||
.readl_be = spiderpci_readl_be,
|
||||
.readq_be = spiderpci_readq_be,
|
||||
.readsb = spiderpci_readsb,
|
||||
.readsw = spiderpci_readsw,
|
||||
.readsl = spiderpci_readsl,
|
||||
.memcpy_fromio = spiderpci_memcpy_fromio,
|
||||
};
|
||||
|
||||
@ -1,59 +1,60 @@
|
||||
/* This file is meant to be include multiple times by other headers */
|
||||
/* last 2 argments are used by platforms/cell/io-workarounds.[ch] */
|
||||
|
||||
DEF_PCI_AC_RET(readb, u8, (const PCI_IO_ADDR addr), (addr))
|
||||
DEF_PCI_AC_RET(readw, u16, (const PCI_IO_ADDR addr), (addr))
|
||||
DEF_PCI_AC_RET(readl, u32, (const PCI_IO_ADDR addr), (addr))
|
||||
DEF_PCI_AC_RET(readw_be, u16, (const PCI_IO_ADDR addr), (addr))
|
||||
DEF_PCI_AC_RET(readl_be, u32, (const PCI_IO_ADDR addr), (addr))
|
||||
DEF_PCI_AC_NORET(writeb, (u8 val, PCI_IO_ADDR addr), (val, addr))
|
||||
DEF_PCI_AC_NORET(writew, (u16 val, PCI_IO_ADDR addr), (val, addr))
|
||||
DEF_PCI_AC_NORET(writel, (u32 val, PCI_IO_ADDR addr), (val, addr))
|
||||
DEF_PCI_AC_NORET(writew_be, (u16 val, PCI_IO_ADDR addr), (val, addr))
|
||||
DEF_PCI_AC_NORET(writel_be, (u32 val, PCI_IO_ADDR addr), (val, addr))
|
||||
DEF_PCI_AC_RET(readb, u8, (const PCI_IO_ADDR addr), (addr), mem, addr)
|
||||
DEF_PCI_AC_RET(readw, u16, (const PCI_IO_ADDR addr), (addr), mem, addr)
|
||||
DEF_PCI_AC_RET(readl, u32, (const PCI_IO_ADDR addr), (addr), mem, addr)
|
||||
DEF_PCI_AC_RET(readw_be, u16, (const PCI_IO_ADDR addr), (addr), mem, addr)
|
||||
DEF_PCI_AC_RET(readl_be, u32, (const PCI_IO_ADDR addr), (addr), mem, addr)
|
||||
DEF_PCI_AC_NORET(writeb, (u8 val, PCI_IO_ADDR addr), (val, addr), mem, addr)
|
||||
DEF_PCI_AC_NORET(writew, (u16 val, PCI_IO_ADDR addr), (val, addr), mem, addr)
|
||||
DEF_PCI_AC_NORET(writel, (u32 val, PCI_IO_ADDR addr), (val, addr), mem, addr)
|
||||
DEF_PCI_AC_NORET(writew_be, (u16 val, PCI_IO_ADDR addr), (val, addr), mem, addr)
|
||||
DEF_PCI_AC_NORET(writel_be, (u32 val, PCI_IO_ADDR addr), (val, addr), mem, addr)
|
||||
|
||||
#ifdef __powerpc64__
|
||||
DEF_PCI_AC_RET(readq, u64, (const PCI_IO_ADDR addr), (addr))
|
||||
DEF_PCI_AC_RET(readq_be, u64, (const PCI_IO_ADDR addr), (addr))
|
||||
DEF_PCI_AC_NORET(writeq, (u64 val, PCI_IO_ADDR addr), (val, addr))
|
||||
DEF_PCI_AC_NORET(writeq_be, (u64 val, PCI_IO_ADDR addr), (val, addr))
|
||||
DEF_PCI_AC_RET(readq, u64, (const PCI_IO_ADDR addr), (addr), mem, addr)
|
||||
DEF_PCI_AC_RET(readq_be, u64, (const PCI_IO_ADDR addr), (addr), mem, addr)
|
||||
DEF_PCI_AC_NORET(writeq, (u64 val, PCI_IO_ADDR addr), (val, addr), mem, addr)
|
||||
DEF_PCI_AC_NORET(writeq_be, (u64 val, PCI_IO_ADDR addr), (val, addr), mem, addr)
|
||||
#endif /* __powerpc64__ */
|
||||
|
||||
DEF_PCI_AC_RET(inb, u8, (unsigned long port), (port))
|
||||
DEF_PCI_AC_RET(inw, u16, (unsigned long port), (port))
|
||||
DEF_PCI_AC_RET(inl, u32, (unsigned long port), (port))
|
||||
DEF_PCI_AC_NORET(outb, (u8 val, unsigned long port), (val, port))
|
||||
DEF_PCI_AC_NORET(outw, (u16 val, unsigned long port), (val, port))
|
||||
DEF_PCI_AC_NORET(outl, (u32 val, unsigned long port), (val, port))
|
||||
DEF_PCI_AC_RET(inb, u8, (unsigned long port), (port), pio, port)
|
||||
DEF_PCI_AC_RET(inw, u16, (unsigned long port), (port), pio, port)
|
||||
DEF_PCI_AC_RET(inl, u32, (unsigned long port), (port), pio, port)
|
||||
DEF_PCI_AC_NORET(outb, (u8 val, unsigned long port), (val, port), pio, port)
|
||||
DEF_PCI_AC_NORET(outw, (u16 val, unsigned long port), (val, port), pio, port)
|
||||
DEF_PCI_AC_NORET(outl, (u32 val, unsigned long port), (val, port), pio, port)
|
||||
|
||||
DEF_PCI_AC_NORET(readsb, (const PCI_IO_ADDR a, void *b, unsigned long c), \
|
||||
(a, b, c))
|
||||
DEF_PCI_AC_NORET(readsw, (const PCI_IO_ADDR a, void *b, unsigned long c), \
|
||||
(a, b, c))
|
||||
DEF_PCI_AC_NORET(readsl, (const PCI_IO_ADDR a, void *b, unsigned long c), \
|
||||
(a, b, c))
|
||||
DEF_PCI_AC_NORET(writesb, (PCI_IO_ADDR a, const void *b, unsigned long c), \
|
||||
(a, b, c))
|
||||
DEF_PCI_AC_NORET(writesw, (PCI_IO_ADDR a, const void *b, unsigned long c), \
|
||||
(a, b, c))
|
||||
DEF_PCI_AC_NORET(writesl, (PCI_IO_ADDR a, const void *b, unsigned long c), \
|
||||
(a, b, c))
|
||||
DEF_PCI_AC_NORET(readsb, (const PCI_IO_ADDR a, void *b, unsigned long c),
|
||||
(a, b, c), mem, a)
|
||||
DEF_PCI_AC_NORET(readsw, (const PCI_IO_ADDR a, void *b, unsigned long c),
|
||||
(a, b, c), mem, a)
|
||||
DEF_PCI_AC_NORET(readsl, (const PCI_IO_ADDR a, void *b, unsigned long c),
|
||||
(a, b, c), mem, a)
|
||||
DEF_PCI_AC_NORET(writesb, (PCI_IO_ADDR a, const void *b, unsigned long c),
|
||||
(a, b, c), mem, a)
|
||||
DEF_PCI_AC_NORET(writesw, (PCI_IO_ADDR a, const void *b, unsigned long c),
|
||||
(a, b, c), mem, a)
|
||||
DEF_PCI_AC_NORET(writesl, (PCI_IO_ADDR a, const void *b, unsigned long c),
|
||||
(a, b, c), mem, a)
|
||||
|
||||
DEF_PCI_AC_NORET(insb, (unsigned long p, void *b, unsigned long c), \
|
||||
(p, b, c))
|
||||
DEF_PCI_AC_NORET(insw, (unsigned long p, void *b, unsigned long c), \
|
||||
(p, b, c))
|
||||
DEF_PCI_AC_NORET(insl, (unsigned long p, void *b, unsigned long c), \
|
||||
(p, b, c))
|
||||
DEF_PCI_AC_NORET(outsb, (unsigned long p, const void *b, unsigned long c), \
|
||||
(p, b, c))
|
||||
DEF_PCI_AC_NORET(outsw, (unsigned long p, const void *b, unsigned long c), \
|
||||
(p, b, c))
|
||||
DEF_PCI_AC_NORET(outsl, (unsigned long p, const void *b, unsigned long c), \
|
||||
(p, b, c))
|
||||
DEF_PCI_AC_NORET(insb, (unsigned long p, void *b, unsigned long c),
|
||||
(p, b, c), pio, p)
|
||||
DEF_PCI_AC_NORET(insw, (unsigned long p, void *b, unsigned long c),
|
||||
(p, b, c), pio, p)
|
||||
DEF_PCI_AC_NORET(insl, (unsigned long p, void *b, unsigned long c),
|
||||
(p, b, c), pio, p)
|
||||
DEF_PCI_AC_NORET(outsb, (unsigned long p, const void *b, unsigned long c),
|
||||
(p, b, c), pio, p)
|
||||
DEF_PCI_AC_NORET(outsw, (unsigned long p, const void *b, unsigned long c),
|
||||
(p, b, c), pio, p)
|
||||
DEF_PCI_AC_NORET(outsl, (unsigned long p, const void *b, unsigned long c),
|
||||
(p, b, c), pio, p)
|
||||
|
||||
DEF_PCI_AC_NORET(memset_io, (PCI_IO_ADDR a, int c, unsigned long n), \
|
||||
(a, c, n))
|
||||
DEF_PCI_AC_NORET(memcpy_fromio,(void *d,const PCI_IO_ADDR s,unsigned long n), \
|
||||
(d, s, n))
|
||||
DEF_PCI_AC_NORET(memcpy_toio,(PCI_IO_ADDR d,const void *s,unsigned long n), \
|
||||
(d, s, n))
|
||||
DEF_PCI_AC_NORET(memset_io, (PCI_IO_ADDR a, int c, unsigned long n),
|
||||
(a, c, n), mem, a)
|
||||
DEF_PCI_AC_NORET(memcpy_fromio, (void *d, const PCI_IO_ADDR s, unsigned long n),
|
||||
(d, s, n), mem, s)
|
||||
DEF_PCI_AC_NORET(memcpy_toio, (PCI_IO_ADDR d, const void *s, unsigned long n),
|
||||
(d, s, n), mem, d)
|
||||
|
||||
@ -458,8 +458,8 @@ __do_out_asm(_rec_outl, "stwbrx")
|
||||
/* Structure containing all the hooks */
|
||||
extern struct ppc_pci_io {
|
||||
|
||||
#define DEF_PCI_AC_RET(name, ret, at, al) ret (*name) at;
|
||||
#define DEF_PCI_AC_NORET(name, at, al) void (*name) at;
|
||||
#define DEF_PCI_AC_RET(name, ret, at, al, space, aa) ret (*name) at;
|
||||
#define DEF_PCI_AC_NORET(name, at, al, space, aa) void (*name) at;
|
||||
|
||||
#include <asm/io-defs.h>
|
||||
|
||||
@ -469,7 +469,7 @@ extern struct ppc_pci_io {
|
||||
} ppc_pci_io;
|
||||
|
||||
/* The inline wrappers */
|
||||
#define DEF_PCI_AC_RET(name, ret, at, al) \
|
||||
#define DEF_PCI_AC_RET(name, ret, at, al, space, aa) \
|
||||
static inline ret name at \
|
||||
{ \
|
||||
if (DEF_PCI_HOOK(ppc_pci_io.name) != NULL) \
|
||||
@ -477,7 +477,7 @@ static inline ret name at \
|
||||
return __do_##name al; \
|
||||
}
|
||||
|
||||
#define DEF_PCI_AC_NORET(name, at, al) \
|
||||
#define DEF_PCI_AC_NORET(name, at, al, space, aa) \
|
||||
static inline void name at \
|
||||
{ \
|
||||
if (DEF_PCI_HOOK(ppc_pci_io.name) != NULL) \
|
||||
|
||||
Loading…
Reference in New Issue
Block a user