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Palmchip BK3710 IDE driver
This is Palmchip BK3710 IDE controller support. The IDE controller logic supports PIO, MultiWord-DMA and Ultra-DMA modes. Supports interface to Compact Flash (CF) configured in True-IDE mode. Bart: - remove dead code - fix ide_hwif_setup_dma() build problem Signed-off-by: Anton Salnikov <asalnikov@ru.mvista.com> Reviewed-by: Alan Cox <alan@lxorguk.ukuu.org.uk> Reviewed-by: Sergei Shtylyov <sshtylyov@ru.mvista.com> Signed-off-by: Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
This commit is contained in:
Anton Salnikov
Bartlomiej Zolnierkiewicz
parent
b2a53bc636
commit
7c7e92a926
@ -1009,6 +1009,15 @@ config BLK_DEV_Q40IDE
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normally be on; disable it only if you are running a custom hard
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drive subsystem through an expansion card.
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config BLK_DEV_PALMCHIP_BK3710
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tristate "Palmchip bk3710 IDE controller support"
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depends on ARCH_DAVINCI
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select BLK_DEV_IDEDMA_PCI
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help
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Say Y here if you want to support the onchip IDE controller on the
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TI DaVinci SoC
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config BLK_DEV_MPC8xx_IDE
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tristate "MPC8xx IDE support"
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depends on 8xx && (LWMON || IVMS8 || IVML24 || TQM8xxL) && IDE=y && BLK_DEV_IDE=y && !PPC_MERGE
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@ -2,6 +2,7 @@
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obj-$(CONFIG_BLK_DEV_IDE_ICSIDE) += icside.o
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obj-$(CONFIG_BLK_DEV_IDE_RAPIDE) += rapide.o
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obj-$(CONFIG_BLK_DEV_IDE_BAST) += bast-ide.o
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obj-$(CONFIG_BLK_DEV_PALMCHIP_BK3710) += palm_bk3710.o
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ifeq ($(CONFIG_IDE_ARM), m)
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obj-m += ide_arm.o
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395
drivers/ide/arm/palm_bk3710.c
Normal file
395
drivers/ide/arm/palm_bk3710.c
Normal file
@ -0,0 +1,395 @@
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/*
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* Palmchip bk3710 IDE controller
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*
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* Copyright (C) 2006 Texas Instruments.
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* Copyright (C) 2007 MontaVista Software, Inc., <source@mvista.com>
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*
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* ----------------------------------------------------------------------------
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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* ----------------------------------------------------------------------------
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*
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*/
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#include <linux/types.h>
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/ioport.h>
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#include <linux/hdreg.h>
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#include <linux/ide.h>
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#include <linux/delay.h>
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#include <linux/init.h>
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#include <linux/clk.h>
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#include <linux/platform_device.h>
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/* Offset of the primary interface registers */
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#define IDE_PALM_ATA_PRI_REG_OFFSET 0x1F0
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/* Primary Control Offset */
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#define IDE_PALM_ATA_PRI_CTL_OFFSET 0x3F6
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/*
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* PalmChip 3710 IDE Controller UDMA timing structure Definition
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*/
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struct palm_bk3710_udmatiming {
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unsigned int rptime; /* Ready to pause time */
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unsigned int cycletime; /* Cycle Time */
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};
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#define BK3710_BMICP 0x00
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#define BK3710_BMISP 0x02
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#define BK3710_BMIDTP 0x04
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#define BK3710_BMICS 0x08
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#define BK3710_BMISS 0x0A
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#define BK3710_BMIDTS 0x0C
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#define BK3710_IDETIMP 0x40
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#define BK3710_IDETIMS 0x42
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#define BK3710_SIDETIM 0x44
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#define BK3710_SLEWCTL 0x45
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#define BK3710_IDESTATUS 0x47
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#define BK3710_UDMACTL 0x48
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#define BK3710_UDMATIM 0x4A
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#define BK3710_MISCCTL 0x50
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#define BK3710_REGSTB 0x54
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#define BK3710_REGRCVR 0x58
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#define BK3710_DATSTB 0x5C
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#define BK3710_DATRCVR 0x60
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#define BK3710_DMASTB 0x64
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#define BK3710_DMARCVR 0x68
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#define BK3710_UDMASTB 0x6C
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#define BK3710_UDMATRP 0x70
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#define BK3710_UDMAENV 0x74
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#define BK3710_IORDYTMP 0x78
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#define BK3710_IORDYTMS 0x7C
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#include "../ide-timing.h"
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static long ide_palm_clk;
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static const struct palm_bk3710_udmatiming palm_bk3710_udmatimings[6] = {
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{160, 240}, /* UDMA Mode 0 */
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{125, 160}, /* UDMA Mode 1 */
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{100, 120}, /* UDMA Mode 2 */
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{100, 90}, /* UDMA Mode 3 */
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{85, 60}, /* UDMA Mode 4 */
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};
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static struct clk *ideclkp;
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static void palm_bk3710_setudmamode(void __iomem *base, unsigned int dev,
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unsigned int mode)
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{
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u8 tenv, trp, t0;
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u32 val32;
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u16 val16;
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/* DMA Data Setup */
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t0 = (palm_bk3710_udmatimings[mode].cycletime + ide_palm_clk - 1)
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/ ide_palm_clk - 1;
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tenv = (20 + ide_palm_clk - 1) / ide_palm_clk - 1;
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trp = (palm_bk3710_udmatimings[mode].rptime + ide_palm_clk - 1)
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/ ide_palm_clk - 1;
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/* udmatim Register */
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val16 = readw(base + BK3710_UDMATIM) & (dev ? 0xFF0F : 0xFFF0);
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val16 |= (mode << (dev ? 4 : 0));
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writew(val16, base + BK3710_UDMATIM);
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/* udmastb Ultra DMA Access Strobe Width */
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val32 = readl(base + BK3710_UDMASTB) & (0xFF << (dev ? 0 : 8));
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val32 |= (t0 << (dev ? 8 : 0));
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writel(val32, base + BK3710_UDMASTB);
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/* udmatrp Ultra DMA Ready to Pause Time */
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val32 = readl(base + BK3710_UDMATRP) & (0xFF << (dev ? 0 : 8));
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val32 |= (trp << (dev ? 8 : 0));
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writel(val32, base + BK3710_UDMATRP);
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/* udmaenv Ultra DMA envelop Time */
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val32 = readl(base + BK3710_UDMAENV) & (0xFF << (dev ? 0 : 8));
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val32 |= (tenv << (dev ? 8 : 0));
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writel(val32, base + BK3710_UDMAENV);
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/* Enable UDMA for Device */
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val16 = readw(base + BK3710_UDMACTL) | (1 << dev);
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writew(val16, base + BK3710_UDMACTL);
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}
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static void palm_bk3710_setdmamode(void __iomem *base, unsigned int dev,
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unsigned short min_cycle,
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unsigned int mode)
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{
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u8 td, tkw, t0;
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u32 val32;
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u16 val16;
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struct ide_timing *t;
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int cycletime;
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t = ide_timing_find_mode(mode);
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cycletime = max_t(int, t->cycle, min_cycle);
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/* DMA Data Setup */
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t0 = (cycletime + ide_palm_clk - 1) / ide_palm_clk;
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td = (t->active + ide_palm_clk - 1) / ide_palm_clk;
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tkw = t0 - td - 1;
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td -= 1;
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val32 = readl(base + BK3710_DMASTB) & (0xFF << (dev ? 0 : 8));
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val32 |= (td << (dev ? 8 : 0));
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writel(val32, base + BK3710_DMASTB);
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val32 = readl(base + BK3710_DMARCVR) & (0xFF << (dev ? 0 : 8));
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val32 |= (tkw << (dev ? 8 : 0));
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writel(val32, base + BK3710_DMARCVR);
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/* Disable UDMA for Device */
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val16 = readw(base + BK3710_UDMACTL) & ~(1 << dev);
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writew(val16, base + BK3710_UDMACTL);
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}
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static void palm_bk3710_setpiomode(void __iomem *base, ide_drive_t *mate,
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unsigned int dev, unsigned int cycletime,
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unsigned int mode)
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{
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u8 t2, t2i, t0;
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u32 val32;
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struct ide_timing *t;
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/* PIO Data Setup */
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t0 = (cycletime + ide_palm_clk - 1) / ide_palm_clk;
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t2 = (ide_timing_find_mode(XFER_PIO_0 + mode)->active +
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ide_palm_clk - 1) / ide_palm_clk;
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t2i = t0 - t2 - 1;
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t2 -= 1;
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val32 = readl(base + BK3710_DATSTB) & (0xFF << (dev ? 0 : 8));
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val32 |= (t2 << (dev ? 8 : 0));
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writel(val32, base + BK3710_DATSTB);
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val32 = readl(base + BK3710_DATRCVR) & (0xFF << (dev ? 0 : 8));
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val32 |= (t2i << (dev ? 8 : 0));
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writel(val32, base + BK3710_DATRCVR);
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if (mate && mate->present) {
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u8 mode2 = ide_get_best_pio_mode(mate, 255, 4);
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if (mode2 < mode)
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mode = mode2;
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}
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/* TASKFILE Setup */
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t = ide_timing_find_mode(XFER_PIO_0 + mode);
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t0 = (t->cyc8b + ide_palm_clk - 1) / ide_palm_clk;
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t2 = (t->act8b + ide_palm_clk - 1) / ide_palm_clk;
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t2i = t0 - t2 - 1;
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t2 -= 1;
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val32 = readl(base + BK3710_REGSTB) & (0xFF << (dev ? 0 : 8));
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val32 |= (t2 << (dev ? 8 : 0));
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writel(val32, base + BK3710_REGSTB);
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val32 = readl(base + BK3710_REGRCVR) & (0xFF << (dev ? 0 : 8));
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val32 |= (t2i << (dev ? 8 : 0));
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writel(val32, base + BK3710_REGRCVR);
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}
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static void palm_bk3710_set_dma_mode(ide_drive_t *drive, u8 xferspeed)
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{
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int is_slave = drive->dn & 1;
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void __iomem *base = (void *)drive->hwif->dma_base;
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if (xferspeed >= XFER_UDMA_0) {
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palm_bk3710_setudmamode(base, is_slave,
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xferspeed - XFER_UDMA_0);
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} else {
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palm_bk3710_setdmamode(base, is_slave, drive->id->eide_dma_min,
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xferspeed);
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}
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}
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static void palm_bk3710_set_pio_mode(ide_drive_t *drive, u8 pio)
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{
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unsigned int cycle_time;
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int is_slave = drive->dn & 1;
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ide_drive_t *mate;
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void __iomem *base = (void *)drive->hwif->dma_base;
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/*
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* Obtain the drive PIO data for tuning the Palm Chip registers
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*/
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cycle_time = ide_pio_cycle_time(drive, pio);
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mate = ide_get_paired_drive(drive);
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palm_bk3710_setpiomode(base, mate, is_slave, cycle_time, pio);
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}
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static void __devinit palm_bk3710_chipinit(void __iomem *base)
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{
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/*
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* enable the reset_en of ATA controller so that when ata signals
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* are brought out, by writing into device config. at that
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* time por_n signal should not be 'Z' and have a stable value.
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*/
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writel(0x0300, base + BK3710_MISCCTL);
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/* wait for some time and deassert the reset of ATA Device. */
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mdelay(100);
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/* Deassert the Reset */
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writel(0x0200, base + BK3710_MISCCTL);
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/*
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* Program the IDETIMP Register Value based on the following assumptions
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*
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* (ATA_IDETIMP_IDEEN , ENABLE ) |
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* (ATA_IDETIMP_SLVTIMEN , DISABLE) |
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* (ATA_IDETIMP_RDYSMPL , 70NS) |
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* (ATA_IDETIMP_RDYRCVRY , 50NS) |
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* (ATA_IDETIMP_DMAFTIM1 , PIOCOMP) |
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* (ATA_IDETIMP_PREPOST1 , DISABLE) |
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* (ATA_IDETIMP_RDYSEN1 , DISABLE) |
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* (ATA_IDETIMP_PIOFTIM1 , DISABLE) |
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* (ATA_IDETIMP_DMAFTIM0 , PIOCOMP) |
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* (ATA_IDETIMP_PREPOST0 , DISABLE) |
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* (ATA_IDETIMP_RDYSEN0 , DISABLE) |
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* (ATA_IDETIMP_PIOFTIM0 , DISABLE)
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*/
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writew(0xB388, base + BK3710_IDETIMP);
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/*
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* Configure SIDETIM Register
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* (ATA_SIDETIM_RDYSMPS1 ,120NS ) |
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* (ATA_SIDETIM_RDYRCYS1 ,120NS )
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*/
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writeb(0, base + BK3710_SIDETIM);
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/*
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* UDMACTL Ultra-ATA DMA Control
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* (ATA_UDMACTL_UDMAP1 , 0 ) |
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* (ATA_UDMACTL_UDMAP0 , 0 )
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*
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*/
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writew(0, base + BK3710_UDMACTL);
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/*
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* MISCCTL Miscellaneous Conrol Register
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* (ATA_MISCCTL_RSTMODEP , 1) |
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* (ATA_MISCCTL_RESETP , 0) |
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* (ATA_MISCCTL_TIMORIDE , 1)
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*/
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writel(0x201, base + BK3710_MISCCTL);
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/*
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* IORDYTMP IORDY Timer for Primary Register
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* (ATA_IORDYTMP_IORDYTMP , 0xffff )
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*/
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writel(0xFFFF, base + BK3710_IORDYTMP);
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/*
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* Configure BMISP Register
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* (ATA_BMISP_DMAEN1 , DISABLE ) |
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* (ATA_BMISP_DMAEN0 , DISABLE ) |
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* (ATA_BMISP_IORDYINT , CLEAR) |
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* (ATA_BMISP_INTRSTAT , CLEAR) |
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* (ATA_BMISP_DMAERROR , CLEAR)
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*/
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writew(0, base + BK3710_BMISP);
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palm_bk3710_setpiomode(base, NULL, 0, 600, 0);
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palm_bk3710_setpiomode(base, NULL, 1, 600, 0);
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}
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static int __devinit palm_bk3710_probe(struct platform_device *pdev)
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{
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hw_regs_t ide_ctlr_info;
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int index = 0;
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int pribase;
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struct clk *clkp;
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struct resource *mem, *irq;
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ide_hwif_t *hwif;
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void __iomem *base;
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clkp = clk_get(NULL, "IDECLK");
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if (IS_ERR(clkp))
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return -ENODEV;
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ideclkp = clkp;
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clk_enable(ideclkp);
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ide_palm_clk = clk_get_rate(ideclkp)/100000;
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ide_palm_clk = (10000/ide_palm_clk) + 1;
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/* Register the IDE interface with Linux ATA Interface */
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memset(&ide_ctlr_info, 0, sizeof(ide_ctlr_info));
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mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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if (mem == NULL) {
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printk(KERN_ERR "failed to get memory region resource\n");
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return -ENODEV;
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}
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irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
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if (irq == NULL) {
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printk(KERN_ERR "failed to get IRQ resource\n");
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return -ENODEV;
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}
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base = (void *)mem->start;
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/* Configure the Palm Chip controller */
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palm_bk3710_chipinit(base);
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pribase = mem->start + IDE_PALM_ATA_PRI_REG_OFFSET;
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for (index = 0; index < IDE_NR_PORTS - 2; index++)
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ide_ctlr_info.io_ports[index] = pribase + index;
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ide_ctlr_info.io_ports[IDE_CONTROL_OFFSET] = mem->start +
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IDE_PALM_ATA_PRI_CTL_OFFSET;
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ide_ctlr_info.irq = irq->start;
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ide_ctlr_info.chipset = ide_palm3710;
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if (ide_register_hw(&ide_ctlr_info, NULL, &hwif) < 0) {
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printk(KERN_WARNING "Palm Chip BK3710 IDE Register Fail\n");
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return -ENODEV;
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}
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hwif->set_pio_mode = &palm_bk3710_set_pio_mode;
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hwif->set_dma_mode = &palm_bk3710_set_dma_mode;
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hwif->mmio = 1;
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default_hwif_mmiops(hwif);
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hwif->cbl = ATA_CBL_PATA80;
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hwif->ultra_mask = 0x1f; /* Ultra DMA Mode 4 Max
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(input clk 99MHz) */
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hwif->mwdma_mask = 0x7;
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hwif->drives[0].autotune = 1;
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hwif->drives[1].autotune = 1;
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ide_setup_dma(hwif, mem->start);
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return 0;
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}
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static struct platform_driver platform_bk_driver = {
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.driver = {
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.name = "palm_bk3710",
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},
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.probe = palm_bk3710_probe,
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||||
.remove = NULL,
|
||||
};
|
||||
|
||||
static int __init palm_bk3710_init(void)
|
||||
{
|
||||
return platform_driver_register(&platform_bk_driver);
|
||||
}
|
||||
|
||||
module_init(palm_bk3710_init);
|
||||
MODULE_LICENSE("GPL");
|
||||
|
||||
@ -65,6 +65,7 @@ static int proc_ide_read_imodel
|
||||
case ide_4drives: name = "4drives"; break;
|
||||
case ide_pmac: name = "mac-io"; break;
|
||||
case ide_au1xxx: name = "au1xxx"; break;
|
||||
case ide_palm3710: name = "palm3710"; break;
|
||||
case ide_etrax100: name = "etrax100"; break;
|
||||
case ide_acorn: name = "acorn"; break;
|
||||
default: name = "(unknown)"; break;
|
||||
|
||||
@ -173,7 +173,7 @@ enum { ide_unknown, ide_generic, ide_pci,
|
||||
ide_rz1000, ide_trm290,
|
||||
ide_cmd646, ide_cy82c693, ide_4drives,
|
||||
ide_pmac, ide_etrax100, ide_acorn,
|
||||
ide_au1xxx, ide_forced
|
||||
ide_au1xxx, ide_palm3710, ide_forced
|
||||
};
|
||||
|
||||
typedef u8 hwif_chipset_t;
|
||||
@ -1014,7 +1014,8 @@ extern int __ide_pci_register_driver(struct pci_driver *driver, struct module *o
|
||||
void ide_pci_setup_ports(struct pci_dev *, const struct ide_port_info *, int, u8 *);
|
||||
void ide_setup_pci_noise(struct pci_dev *, const struct ide_port_info *);
|
||||
|
||||
#ifdef CONFIG_BLK_DEV_IDEDMA_PCI
|
||||
/* FIXME: palm_bk3710 uses BLK_DEV_IDEDMA_PCI without BLK_DEV_IDEPCI! */
|
||||
#if defined(CONFIG_BLK_DEV_IDEPCI) && defined(CONFIG_BLK_DEV_IDEDMA_PCI)
|
||||
void ide_hwif_setup_dma(ide_hwif_t *, const struct ide_port_info *);
|
||||
#else
|
||||
static inline void ide_hwif_setup_dma(ide_hwif_t *hwif,
|
||||
|
||||
Loading…
Reference in New Issue
Block a user