mirror of
https://github.com/torvalds/linux.git
synced 2024-11-10 06:01:57 +00:00
dmaengine updates for v6.11
New support:
- New dmaengine_prep_peripheral_dma_vec() to support transfers using dma
vectors and documentation and user in AXI dma
- STMicro STM32 DMA3 support and new capabilities of cyclic dma
Updates:
- Yaml conversion for Freescale imx dma and qdma bindings, sprd sc9860 dma
binding
- Altera msgdma updates for descriptor management
-----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEE+vs47OPLdNbVcHzyfBQHDyUjg0cFAmagqd0ACgkQfBQHDyUj
g0cVug//e+Wu5E1xc+PHQl9XHMmgaH0YBNlpVF1cpZH47rXEt9CbHypggAqhM9D7
ubfGSN7q3vb5geT+8177bgM5UdGKjbn/bYXF9wU9+P075E/y46kaxEo6I8PX6isq
kAdKqGWsGQ1lggv3BptLAIstYoRjMrJIH/jwXcvO0CuzT/UYSPdeZny0T50a8nhN
VRe2vev6ikW3XtuPvCRUxgdi/6vCRJP58qeuppOpUmnAlJMrG/5TAB7cq0F6hMRU
XR4VaAnyww0rM5rUqUolLHMCLHxkG4h2FO9T1780kRW5zHBI9K2zzgWV11B1DdiB
tCOpMrcDkbLOsYG3Yr1QbjwtSGOvIP9CuusgFHPqwg+meRY+GHu+/H4j5bxYAHpY
ISPKCqAShCGykjCoMlx5hJKN5FCazQhfqnvi1OXZZmhy7cdv5r0/NPBm9eKT/P9O
hPMcB8ou0EjlJ9xqFmPB+Itw1p7ArEzj/Dv483qudu8nuzOAfZ6LRP3sUoSPcY2K
KokMkHjE5MuAYpA57BQ3vAOFdZCjHkf05K3s1+HQ2/wSKU7elu5BUqo0Oxf6qh46
WkFCcUDYNNOIll31ydw9MNjAT7ontxC+NAEEeTjqid6DIzxefqpfGRpylEUSzNhT
UWq8o4e7ZvKw6bis8SvxiZxmPdAOLKqjJ9Mb7ggRH5XiH5Wk6pI=
=h0hh
-----END PGP SIGNATURE-----
Merge tag 'dmaengine-6.11-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/vkoul/dmaengine
Pull dmaengine updates from Vinod Koul:
"New support:
- New dmaengine_prep_peripheral_dma_vec() to support transfers using
dma vectors and documentation and user in AXI dma
- STMicro STM32 DMA3 support and new capabilities of cyclic dma
Updates:
- Yaml conversion for Freescale imx dma and qdma bindings,
sprd sc9860 dma binding
- Altera msgdma updates for descriptor management"
* tag 'dmaengine-6.11-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/vkoul/dmaengine: (35 commits)
dt-bindings: fsl-qdma: fix interrupts 'if' check logic
dt-bindings: dma: sprd,sc9860-dma: convert to YAML
dmaengine: fsl-dpaa2-qdma: add missing MODULE_DESCRIPTION() macro
dmaengine: ti: add missing MODULE_DESCRIPTION() macros
dmaengine: ti: cppi41: add missing MODULE_DESCRIPTION() macro
dmaengine: virt-dma: add missing MODULE_DESCRIPTION() macro
dmaengine: ti: k3-udma: Fix BCHAN count with UHC and HC channels
dmaengine: sh: rz-dmac: Fix lockdep assert warning
dmaengine: qcom: gpi: clean up the IRQ disable/enable in gpi_reset_chan()
dmaengine: fsl-edma: change the memory access from local into remote mode in i.MX 8QM
dmaengine: qcom: gpi: remove unused struct 'reg_info'
dmaengine: moxart-dma: remove unused struct 'moxart_filter_data'
dt-bindings: fsl-qdma: Convert to yaml format
dmaengine: fsl-edma: remove redundant "idle" field from fsl_chan
dmaengine: fsl-edma: request per-channel IRQ only when channel is allocated
dmaengine: stm32-dma3: defer channel registration to specify channel name
dmaengine: add channel device name to channel registration
dmaengine: stm32-dma3: improve residue granularity
dmaengine: stm32-dma3: add device_pause and device_resume ops
dmaengine: stm32-dma3: add DMA_MEMCPY capability
...
This commit is contained in:
Linus Torvalds
commit
7a46b17d4c
56
Documentation/devicetree/bindings/dma/fsl,imx-dma.yaml
Normal file
56
Documentation/devicetree/bindings/dma/fsl,imx-dma.yaml
Normal file
@ -0,0 +1,56 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
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%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/dma/fsl,imx-dma.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Freescale Direct Memory Access (DMA) Controller for i.MX
|
||||
|
||||
maintainers:
|
||||
- Animesh Agarwal <animeshagarwal28@gmail.com>
|
||||
|
||||
allOf:
|
||||
- $ref: dma-controller.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- fsl,imx1-dma
|
||||
- fsl,imx21-dma
|
||||
- fsl,imx27-dma
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupts:
|
||||
items:
|
||||
- description: DMA complete interrupt
|
||||
- description: DMA Error interrupt
|
||||
minItems: 1
|
||||
|
||||
"#dma-cells":
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const: 1
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||||
|
||||
dma-channels:
|
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const: 16
|
||||
|
||||
dma-requests:
|
||||
description: Number of DMA requests supported.
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- interrupts
|
||||
- "#dma-cells"
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
dma-controller@10001000 {
|
||||
compatible = "fsl,imx27-dma";
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reg = <0x10001000 0x1000>;
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interrupts = <32 33>;
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#dma-cells = <1>;
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dma-channels = <16>;
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};
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@ -1,50 +0,0 @@
|
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* Freescale Direct Memory Access (DMA) Controller for i.MX
|
||||
|
||||
This document will only describe differences to the generic DMA Controller and
|
||||
DMA request bindings as described in dma/dma.txt .
|
||||
|
||||
* DMA controller
|
||||
|
||||
Required properties:
|
||||
- compatible : Should be "fsl,<chip>-dma". chip can be imx1, imx21 or imx27
|
||||
- reg : Should contain DMA registers location and length
|
||||
- interrupts : First item should be DMA interrupt, second one is optional and
|
||||
should contain DMA Error interrupt
|
||||
- #dma-cells : Has to be 1. imx-dma does not support anything else.
|
||||
|
||||
Optional properties:
|
||||
- dma-channels : Number of DMA channels supported. Should be 16.
|
||||
- #dma-channels : deprecated
|
||||
- dma-requests : Number of DMA requests supported.
|
||||
- #dma-requests : deprecated
|
||||
|
||||
Example:
|
||||
|
||||
dma: dma@10001000 {
|
||||
compatible = "fsl,imx27-dma";
|
||||
reg = <0x10001000 0x1000>;
|
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interrupts = <32 33>;
|
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#dma-cells = <1>;
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dma-channels = <16>;
|
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};
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|
||||
|
||||
* DMA client
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||||
|
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Clients have to specify the DMA requests with phandles in a list.
|
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|
||||
Required properties:
|
||||
- dmas: List of one or more DMA request specifiers. One DMA request specifier
|
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consists of a phandle to the DMA controller followed by the integer
|
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specifying the request line.
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- dma-names: List of string identifiers for the DMA requests. For the correct
|
||||
names, have a look at the specific client driver.
|
||||
|
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Example:
|
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|
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sdhci1: sdhci@10013000 {
|
||||
...
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dmas = <&dma 7>;
|
||||
dma-names = "rx-tx";
|
||||
...
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};
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@ -1,58 +0,0 @@
|
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NXP Layerscape SoC qDMA Controller
|
||||
==================================
|
||||
|
||||
This device follows the generic DMA bindings defined in dma/dma.txt.
|
||||
|
||||
Required properties:
|
||||
|
||||
- compatible: Must be one of
|
||||
"fsl,ls1021a-qdma": for LS1021A Board
|
||||
"fsl,ls1028a-qdma": for LS1028A Board
|
||||
"fsl,ls1043a-qdma": for ls1043A Board
|
||||
"fsl,ls1046a-qdma": for ls1046A Board
|
||||
- reg: Should contain the register's base address and length.
|
||||
- interrupts: Should contain a reference to the interrupt used by this
|
||||
device.
|
||||
- interrupt-names: Should contain interrupt names:
|
||||
"qdma-queue0": the block0 interrupt
|
||||
"qdma-queue1": the block1 interrupt
|
||||
"qdma-queue2": the block2 interrupt
|
||||
"qdma-queue3": the block3 interrupt
|
||||
"qdma-error": the error interrupt
|
||||
- fsl,dma-queues: Should contain number of queues supported.
|
||||
- dma-channels: Number of DMA channels supported
|
||||
- block-number: the virtual block number
|
||||
- block-offset: the offset of different virtual block
|
||||
- status-sizes: status queue size of per virtual block
|
||||
- queue-sizes: command queue size of per virtual block, the size number
|
||||
based on queues
|
||||
|
||||
Optional properties:
|
||||
|
||||
- dma-channels: Number of DMA channels supported by the controller.
|
||||
- big-endian: If present registers and hardware scatter/gather descriptors
|
||||
of the qDMA are implemented in big endian mode, otherwise in little
|
||||
mode.
|
||||
|
||||
Examples:
|
||||
|
||||
qdma: dma-controller@8390000 {
|
||||
compatible = "fsl,ls1021a-qdma";
|
||||
reg = <0x0 0x8388000 0x0 0x1000>, /* Controller regs */
|
||||
<0x0 0x8389000 0x0 0x1000>, /* Status regs */
|
||||
<0x0 0x838a000 0x0 0x2000>; /* Block regs */
|
||||
interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "qdma-error",
|
||||
"qdma-queue0", "qdma-queue1";
|
||||
dma-channels = <8>;
|
||||
block-number = <2>;
|
||||
block-offset = <0x1000>;
|
||||
fsl,dma-queues = <2>;
|
||||
status-sizes = <64>;
|
||||
queue-sizes = <64 64>;
|
||||
big-endian;
|
||||
};
|
||||
|
||||
DMA clients must use the format described in dma/dma.txt file.
|
||||
132
Documentation/devicetree/bindings/dma/fsl-qdma.yaml
Normal file
132
Documentation/devicetree/bindings/dma/fsl-qdma.yaml
Normal file
@ -0,0 +1,132 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/dma/fsl-qdma.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: NXP Layerscape SoC qDMA Controller
|
||||
|
||||
maintainers:
|
||||
- Frank Li <Frank.Li@nxp.com>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- fsl,ls1021a-qdma
|
||||
- fsl,ls1028a-qdma
|
||||
- fsl,ls1043a-qdma
|
||||
- fsl,ls1046a-qdma
|
||||
|
||||
reg:
|
||||
items:
|
||||
- description: Controller regs
|
||||
- description: Status regs
|
||||
- description: Block regs
|
||||
|
||||
interrupts:
|
||||
minItems: 2
|
||||
maxItems: 5
|
||||
|
||||
interrupt-names:
|
||||
minItems: 2
|
||||
items:
|
||||
- const: qdma-error
|
||||
- const: qdma-queue0
|
||||
- const: qdma-queue1
|
||||
- const: qdma-queue2
|
||||
- const: qdma-queue3
|
||||
|
||||
dma-channels:
|
||||
minimum: 1
|
||||
maximum: 64
|
||||
|
||||
fsl,dma-queues:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description: Should contain number of queues supported.
|
||||
minimum: 1
|
||||
maximum: 4
|
||||
|
||||
block-number:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description: the virtual block number
|
||||
|
||||
block-offset:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description: the offset of different virtual block
|
||||
|
||||
status-sizes:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description: status queue size of per virtual block
|
||||
|
||||
queue-sizes:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32-array
|
||||
description:
|
||||
command queue size of per virtual block, the size number
|
||||
based on queues
|
||||
|
||||
big-endian:
|
||||
$ref: /schemas/types.yaml#/definitions/flag
|
||||
description:
|
||||
If present registers and hardware scatter/gather descriptors
|
||||
of the qDMA are implemented in big endian mode, otherwise in little
|
||||
mode.
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- interrupts
|
||||
- interrupt-names
|
||||
- fsl,dma-queues
|
||||
- block-number
|
||||
- block-offset
|
||||
- status-sizes
|
||||
- queue-sizes
|
||||
|
||||
allOf:
|
||||
- $ref: dma-controller.yaml#
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- fsl,ls1028a-qdma
|
||||
- fsl,ls1043a-qdma
|
||||
- fsl,ls1046a-qdma
|
||||
then:
|
||||
properties:
|
||||
interrupts:
|
||||
minItems: 5
|
||||
interrupt-names:
|
||||
minItems: 5
|
||||
else:
|
||||
properties:
|
||||
interrupts:
|
||||
maxItems: 3
|
||||
interrupt-names:
|
||||
maxItems: 3
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
|
||||
dma-controller@8390000 {
|
||||
compatible = "fsl,ls1021a-qdma";
|
||||
reg = <0x8388000 0x1000>, /* Controller regs */
|
||||
<0x8389000 0x1000>, /* Status regs */
|
||||
<0x838a000 0x2000>; /* Block regs */
|
||||
interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "qdma-error", "qdma-queue0", "qdma-queue1";
|
||||
#dma-cells = <1>;
|
||||
dma-channels = <8>;
|
||||
block-number = <2>;
|
||||
block-offset = <0x1000>;
|
||||
status-sizes = <64>;
|
||||
queue-sizes = <64 64>;
|
||||
big-endian;
|
||||
fsl,dma-queues = <2>;
|
||||
};
|
||||
|
||||
92
Documentation/devicetree/bindings/dma/sprd,sc9860-dma.yaml
Normal file
92
Documentation/devicetree/bindings/dma/sprd,sc9860-dma.yaml
Normal file
@ -0,0 +1,92 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/dma/sprd,sc9860-dma.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Spreadtrum SC9860 DMA controller
|
||||
|
||||
description: |
|
||||
There are three DMA controllers: AP DMA, AON DMA and AGCP DMA. For AGCP
|
||||
DMA controller, it can or do not request the IRQ, which will save
|
||||
system power without resuming system by DMA interrupts if AGCP DMA
|
||||
does not request the IRQ.
|
||||
|
||||
maintainers:
|
||||
- Orson Zhai <orsonzhai@gmail.com>
|
||||
- Baolin Wang <baolin.wang7@gmail.com>
|
||||
- Chunyan Zhang <zhang.lyra@gmail.com>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: sprd,sc9860-dma
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
minItems: 1
|
||||
items:
|
||||
- description: DMA enable clock
|
||||
- description: optional ashb_eb clock, only for the AGCP DMA controller
|
||||
|
||||
clock-names:
|
||||
minItems: 1
|
||||
items:
|
||||
- const: enable
|
||||
- const: ashb_eb
|
||||
|
||||
'#dma-cells':
|
||||
const: 1
|
||||
|
||||
dma-channels:
|
||||
const: 32
|
||||
|
||||
'#dma-channels':
|
||||
const: 32
|
||||
deprecated: true
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- clock-names
|
||||
- '#dma-cells'
|
||||
- dma-channels
|
||||
|
||||
allOf:
|
||||
- $ref: dma-controller.yaml#
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/sprd,sc9860-clk.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
|
||||
/* AP DMA controller */
|
||||
dma-controller@20100000 {
|
||||
compatible = "sprd,sc9860-dma";
|
||||
reg = <0x20100000 0x4000>;
|
||||
interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&apahb_gate CLK_DMA_EB>;
|
||||
clock-names = "enable";
|
||||
#dma-cells = <1>;
|
||||
dma-channels = <32>;
|
||||
};
|
||||
|
||||
/* AGCP DMA controller */
|
||||
dma-controller@41580000 {
|
||||
compatible = "sprd,sc9860-dma";
|
||||
reg = <0x41580000 0x4000>;
|
||||
clocks = <&agcp_gate CLK_AGCP_DMAAP_EB>,
|
||||
<&agcp_gate CLK_AGCP_AP_ASHB_EB>;
|
||||
clock-names = "enable", "ashb_eb";
|
||||
#dma-cells = <1>;
|
||||
dma-channels = <32>;
|
||||
};
|
||||
...
|
||||
@ -1,44 +0,0 @@
|
||||
* Spreadtrum DMA controller
|
||||
|
||||
This binding follows the generic DMA bindings defined in dma.txt.
|
||||
|
||||
Required properties:
|
||||
- compatible: Should be "sprd,sc9860-dma".
|
||||
- reg: Should contain DMA registers location and length.
|
||||
- interrupts: Should contain one interrupt shared by all channel.
|
||||
- #dma-cells: must be <1>. Used to represent the number of integer
|
||||
cells in the dmas property of client device.
|
||||
- dma-channels : Number of DMA channels supported. Should be 32.
|
||||
- clock-names: Should contain the clock of the DMA controller.
|
||||
- clocks: Should contain a clock specifier for each entry in clock-names.
|
||||
|
||||
Deprecated properties:
|
||||
- #dma-channels : Number of DMA channels supported. Should be 32.
|
||||
|
||||
Example:
|
||||
|
||||
Controller:
|
||||
apdma: dma-controller@20100000 {
|
||||
compatible = "sprd,sc9860-dma";
|
||||
reg = <0x20100000 0x4000>;
|
||||
interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#dma-cells = <1>;
|
||||
dma-channels = <32>;
|
||||
clock-names = "enable";
|
||||
clocks = <&clk_ap_ahb_gates 5>;
|
||||
};
|
||||
|
||||
|
||||
Client:
|
||||
DMA clients connected to the Spreadtrum DMA controller must use the format
|
||||
described in the dma.txt file, using a two-cell specifier for each channel.
|
||||
The two cells in order are:
|
||||
1. A phandle pointing to the DMA controller.
|
||||
2. The slave id.
|
||||
|
||||
spi0: spi@70a00000{
|
||||
...
|
||||
dma-names = "rx_chn", "tx_chn";
|
||||
dmas = <&apdma 11>, <&apdma 12>;
|
||||
...
|
||||
};
|
||||
@ -1,7 +1,7 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/dma/st,stm32-dma.yaml#
|
||||
$id: http://devicetree.org/schemas/dma/stm32/st,stm32-dma.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: STMicroelectronics STM32 DMA Controller
|
||||
@ -53,7 +53,7 @@ maintainers:
|
||||
- Amelie Delaunay <amelie.delaunay@foss.st.com>
|
||||
|
||||
allOf:
|
||||
- $ref: dma-controller.yaml#
|
||||
- $ref: /schemas/dma/dma-controller.yaml#
|
||||
|
||||
properties:
|
||||
"#dma-cells":
|
||||
135
Documentation/devicetree/bindings/dma/stm32/st,stm32-dma3.yaml
Normal file
135
Documentation/devicetree/bindings/dma/stm32/st,stm32-dma3.yaml
Normal file
@ -0,0 +1,135 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/dma/stm32/st,stm32-dma3.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: STMicroelectronics STM32 DMA3 Controller
|
||||
|
||||
description: |
|
||||
The STM32 DMA3 is a direct memory access controller with different features
|
||||
depending on its hardware configuration.
|
||||
It is either called LPDMA (Low Power), GPDMA (General Purpose) or HPDMA (High
|
||||
Performance).
|
||||
Its hardware configuration registers allow to dynamically expose its features.
|
||||
|
||||
GPDMA and HPDMA support 16 independent DMA channels, while only 4 for LPDMA.
|
||||
GPDMA and HPDMA support 256 DMA requests from peripherals, 8 for LPDMA.
|
||||
|
||||
Bindings are generic for these 3 STM32 DMA3 configurations.
|
||||
|
||||
DMA clients connected to the STM32 DMA3 controller must use the format
|
||||
described in "#dma-cells" property description below, using a three-cell
|
||||
specifier for each channel.
|
||||
|
||||
maintainers:
|
||||
- Amelie Delaunay <amelie.delaunay@foss.st.com>
|
||||
|
||||
allOf:
|
||||
- $ref: /schemas/dma/dma-controller.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: st,stm32mp25-dma3
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupts:
|
||||
minItems: 4
|
||||
maxItems: 16
|
||||
description:
|
||||
Should contain all of the per-channel DMA interrupts in ascending order
|
||||
with respect to the DMA channel index.
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
resets:
|
||||
maxItems: 1
|
||||
|
||||
power-domains:
|
||||
maxItems: 1
|
||||
|
||||
"#dma-cells":
|
||||
const: 3
|
||||
description: |
|
||||
Specifies the number of cells needed to provide DMA controller specific
|
||||
information.
|
||||
The first cell is the request line number.
|
||||
The second cell is a 32-bit mask specifying the DMA channel requirements:
|
||||
-bit 0-1: The priority level
|
||||
0x0: low priority, low weight
|
||||
0x1: low priority, mid weight
|
||||
0x2: low priority, high weight
|
||||
0x3: high priority
|
||||
-bit 4-7: The FIFO requirement for queuing source/destination transfers
|
||||
0x0: no FIFO requirement/any channel can fit
|
||||
0x2: FIFO of 8 bytes (2^2+1)
|
||||
0x4: FIFO of 32 bytes (2^4+1)
|
||||
0x6: FIFO of 128 bytes (2^6+1)
|
||||
0x7: FIFO of 256 bytes (2^7+1)
|
||||
The third cell is a 32-bit mask specifying the DMA transfer requirements:
|
||||
-bit 0: The source incrementing burst
|
||||
0x0: fixed burst
|
||||
0x1: contiguously incremented burst
|
||||
-bit 1: The source allocated port
|
||||
0x0: port 0 is allocated to the source transfer
|
||||
0x1: port 1 is allocated to the source transfer
|
||||
-bit 4: The destination incrementing burst
|
||||
0x0: fixed burst
|
||||
0x1: contiguously incremented burst
|
||||
-bit 5: The destination allocated port
|
||||
0x0: port 0 is allocated to the destination transfer
|
||||
0x1: port 1 is allocated to the destination transfer
|
||||
-bit 8: The type of hardware request
|
||||
0x0: burst
|
||||
0x1: block
|
||||
-bit 9: The control mode
|
||||
0x0: DMA controller control mode
|
||||
0x1: peripheral control mode
|
||||
-bit 12-13: The transfer complete event mode
|
||||
0x0: at block level, transfer complete event is generated at the end
|
||||
of a block
|
||||
0x2: at LLI level, the transfer complete event is generated at the end
|
||||
of the LLI transfer
|
||||
including the update of the LLI if any
|
||||
0x3: at channel level, the transfer complete event is generated at the
|
||||
end of the last LLI
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- interrupts
|
||||
- clocks
|
||||
- "#dma-cells"
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/clock/st,stm32mp25-rcc.h>
|
||||
dma-controller@40400000 {
|
||||
compatible = "st,stm32mp25-dma3";
|
||||
reg = <0x40400000 0x1000>;
|
||||
interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&rcc CK_BUS_HPDMA1>;
|
||||
#dma-cells = <3>;
|
||||
};
|
||||
...
|
||||
@ -1,7 +1,7 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/dma/st,stm32-dmamux.yaml#
|
||||
$id: http://devicetree.org/schemas/dma/stm32/st,stm32-dmamux.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: STMicroelectronics STM32 DMA MUX (DMA request router)
|
||||
@ -10,7 +10,7 @@ maintainers:
|
||||
- Amelie Delaunay <amelie.delaunay@foss.st.com>
|
||||
|
||||
allOf:
|
||||
- $ref: dma-router.yaml#
|
||||
- $ref: /schemas/dma/dma-router.yaml#
|
||||
|
||||
properties:
|
||||
"#dma-cells":
|
||||
@ -1,7 +1,7 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/dma/st,stm32-mdma.yaml#
|
||||
$id: http://devicetree.org/schemas/dma/stm32/st,stm32-mdma.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: STMicroelectronics STM32 MDMA Controller
|
||||
@ -53,7 +53,7 @@ maintainers:
|
||||
- Amelie Delaunay <amelie.delaunay@foss.st.com>
|
||||
|
||||
allOf:
|
||||
- $ref: dma-controller.yaml#
|
||||
- $ref: /schemas/dma/dma-controller.yaml#
|
||||
|
||||
properties:
|
||||
"#dma-cells":
|
||||
@ -42,7 +42,7 @@ properties:
|
||||
dmas:
|
||||
description: |
|
||||
DMA specifiers for tx and rx dma. DMA fifo mode must be used. See
|
||||
the STM32 DMA bindings Documentation/devicetree/bindings/dma/st,stm32-dma.yaml.
|
||||
the STM32 DMA controllers bindings Documentation/devicetree/bindings/dma/stm32/*.yaml.
|
||||
items:
|
||||
- description: rx DMA channel
|
||||
- description: tx DMA channel
|
||||
|
||||
@ -21839,6 +21839,15 @@ F: Documentation/devicetree/bindings/iio/adc/st,stm32-dfsdm-adc.yaml
|
||||
F: Documentation/devicetree/bindings/sound/st,stm32-*.yaml
|
||||
F: sound/soc/stm/
|
||||
|
||||
STM32 DMA DRIVERS
|
||||
M: Amélie Delaunay <amelie.delaunay@foss.st.com>
|
||||
L: dmaengine@vger.kernel.org
|
||||
L: linux-stm32@st-md-mailman.stormreply.com (moderated for non-subscribers)
|
||||
S: Maintained
|
||||
F: Documentation/arch/arm/stm32/stm32-dma-mdma-chaining.rst
|
||||
F: Documentation/devicetree/bindings/dma/stm32/
|
||||
F: drivers/dma/stm32/
|
||||
|
||||
STM32 TIMER/LPTIMER DRIVERS
|
||||
M: Fabrice Gasnier <fabrice.gasnier@foss.st.com>
|
||||
S: Maintained
|
||||
|
||||
@ -1172,6 +1172,49 @@ static void request_firmware_work_func(struct work_struct *work)
|
||||
kfree(fw_work);
|
||||
}
|
||||
|
||||
|
||||
static int _request_firmware_nowait(
|
||||
struct module *module, bool uevent,
|
||||
const char *name, struct device *device, gfp_t gfp, void *context,
|
||||
void (*cont)(const struct firmware *fw, void *context), bool nowarn)
|
||||
{
|
||||
struct firmware_work *fw_work;
|
||||
|
||||
fw_work = kzalloc(sizeof(struct firmware_work), gfp);
|
||||
if (!fw_work)
|
||||
return -ENOMEM;
|
||||
|
||||
fw_work->module = module;
|
||||
fw_work->name = kstrdup_const(name, gfp);
|
||||
if (!fw_work->name) {
|
||||
kfree(fw_work);
|
||||
return -ENOMEM;
|
||||
}
|
||||
fw_work->device = device;
|
||||
fw_work->context = context;
|
||||
fw_work->cont = cont;
|
||||
fw_work->opt_flags = FW_OPT_NOWAIT |
|
||||
(uevent ? FW_OPT_UEVENT : FW_OPT_USERHELPER) |
|
||||
(nowarn ? FW_OPT_NO_WARN : 0);
|
||||
|
||||
if (!uevent && fw_cache_is_setup(device, name)) {
|
||||
kfree_const(fw_work->name);
|
||||
kfree(fw_work);
|
||||
return -EOPNOTSUPP;
|
||||
}
|
||||
|
||||
if (!try_module_get(module)) {
|
||||
kfree_const(fw_work->name);
|
||||
kfree(fw_work);
|
||||
return -EFAULT;
|
||||
}
|
||||
|
||||
get_device(fw_work->device);
|
||||
INIT_WORK(&fw_work->work, request_firmware_work_func);
|
||||
schedule_work(&fw_work->work);
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* request_firmware_nowait() - asynchronous version of request_firmware
|
||||
* @module: module requesting the firmware
|
||||
@ -1195,49 +1238,42 @@ static void request_firmware_work_func(struct work_struct *work)
|
||||
*
|
||||
* - can't sleep at all if @gfp is GFP_ATOMIC.
|
||||
**/
|
||||
int
|
||||
request_firmware_nowait(
|
||||
int request_firmware_nowait(
|
||||
struct module *module, bool uevent,
|
||||
const char *name, struct device *device, gfp_t gfp, void *context,
|
||||
void (*cont)(const struct firmware *fw, void *context))
|
||||
{
|
||||
struct firmware_work *fw_work;
|
||||
return _request_firmware_nowait(module, uevent, name, device, gfp,
|
||||
context, cont, false);
|
||||
|
||||
fw_work = kzalloc(sizeof(struct firmware_work), gfp);
|
||||
if (!fw_work)
|
||||
return -ENOMEM;
|
||||
|
||||
fw_work->module = module;
|
||||
fw_work->name = kstrdup_const(name, gfp);
|
||||
if (!fw_work->name) {
|
||||
kfree(fw_work);
|
||||
return -ENOMEM;
|
||||
}
|
||||
fw_work->device = device;
|
||||
fw_work->context = context;
|
||||
fw_work->cont = cont;
|
||||
fw_work->opt_flags = FW_OPT_NOWAIT |
|
||||
(uevent ? FW_OPT_UEVENT : FW_OPT_USERHELPER);
|
||||
|
||||
if (!uevent && fw_cache_is_setup(device, name)) {
|
||||
kfree_const(fw_work->name);
|
||||
kfree(fw_work);
|
||||
return -EOPNOTSUPP;
|
||||
}
|
||||
|
||||
if (!try_module_get(module)) {
|
||||
kfree_const(fw_work->name);
|
||||
kfree(fw_work);
|
||||
return -EFAULT;
|
||||
}
|
||||
|
||||
get_device(fw_work->device);
|
||||
INIT_WORK(&fw_work->work, request_firmware_work_func);
|
||||
schedule_work(&fw_work->work);
|
||||
return 0;
|
||||
}
|
||||
EXPORT_SYMBOL(request_firmware_nowait);
|
||||
|
||||
/**
|
||||
* firmware_request_nowait_nowarn() - async version of request_firmware_nowarn
|
||||
* @module: module requesting the firmware
|
||||
* @name: name of firmware file
|
||||
* @device: device for which firmware is being loaded
|
||||
* @gfp: allocation flags
|
||||
* @context: will be passed over to @cont, and
|
||||
* @fw may be %NULL if firmware request fails.
|
||||
* @cont: function will be called asynchronously when the firmware
|
||||
* request is over.
|
||||
*
|
||||
* Similar in function to request_firmware_nowait(), but doesn't print a warning
|
||||
* when the firmware file could not be found and always sends a uevent to copy
|
||||
* the firmware image.
|
||||
*/
|
||||
int firmware_request_nowait_nowarn(
|
||||
struct module *module, const char *name,
|
||||
struct device *device, gfp_t gfp, void *context,
|
||||
void (*cont)(const struct firmware *fw, void *context))
|
||||
{
|
||||
return _request_firmware_nowait(module, FW_ACTION_UEVENT, name, device,
|
||||
gfp, context, cont, true);
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(firmware_request_nowait_nowarn);
|
||||
|
||||
#ifdef CONFIG_FW_CACHE
|
||||
static ASYNC_DOMAIN_EXCLUSIVE(fw_cache_domain);
|
||||
|
||||
|
||||
@ -568,38 +568,6 @@ config ST_FDMA
|
||||
Say Y here if you have such a chipset.
|
||||
If unsure, say N.
|
||||
|
||||
config STM32_DMA
|
||||
bool "STMicroelectronics STM32 DMA support"
|
||||
depends on ARCH_STM32 || COMPILE_TEST
|
||||
select DMA_ENGINE
|
||||
select DMA_VIRTUAL_CHANNELS
|
||||
help
|
||||
Enable support for the on-chip DMA controller on STMicroelectronics
|
||||
STM32 MCUs.
|
||||
If you have a board based on such a MCU and wish to use DMA say Y
|
||||
here.
|
||||
|
||||
config STM32_DMAMUX
|
||||
bool "STMicroelectronics STM32 dma multiplexer support"
|
||||
depends on STM32_DMA || COMPILE_TEST
|
||||
help
|
||||
Enable support for the on-chip DMA multiplexer on STMicroelectronics
|
||||
STM32 MCUs.
|
||||
If you have a board based on such a MCU and wish to use DMAMUX say Y
|
||||
here.
|
||||
|
||||
config STM32_MDMA
|
||||
bool "STMicroelectronics STM32 master dma support"
|
||||
depends on ARCH_STM32 || COMPILE_TEST
|
||||
depends on OF
|
||||
select DMA_ENGINE
|
||||
select DMA_VIRTUAL_CHANNELS
|
||||
help
|
||||
Enable support for the on-chip MDMA controller on STMicroelectronics
|
||||
STM32 platforms.
|
||||
If you have a board based on STM32 SoC and wish to use the master DMA
|
||||
say Y here.
|
||||
|
||||
config SPRD_DMA
|
||||
tristate "Spreadtrum DMA support"
|
||||
depends on ARCH_SPRD || COMPILE_TEST
|
||||
@ -772,6 +740,8 @@ source "drivers/dma/fsl-dpaa2-qdma/Kconfig"
|
||||
|
||||
source "drivers/dma/lgm/Kconfig"
|
||||
|
||||
source "drivers/dma/stm32/Kconfig"
|
||||
|
||||
# clients
|
||||
comment "DMA Clients"
|
||||
depends on DMA_ENGINE
|
||||
|
||||
@ -70,9 +70,6 @@ obj-$(CONFIG_PXA_DMA) += pxa_dma.o
|
||||
obj-$(CONFIG_RENESAS_DMA) += sh/
|
||||
obj-$(CONFIG_SF_PDMA) += sf-pdma/
|
||||
obj-$(CONFIG_STE_DMA40) += ste_dma40.o ste_dma40_ll.o
|
||||
obj-$(CONFIG_STM32_DMA) += stm32-dma.o
|
||||
obj-$(CONFIG_STM32_DMAMUX) += stm32-dmamux.o
|
||||
obj-$(CONFIG_STM32_MDMA) += stm32-mdma.o
|
||||
obj-$(CONFIG_SPRD_DMA) += sprd-dma.o
|
||||
obj-$(CONFIG_TXX9_DMAC) += txx9dmac.o
|
||||
obj-$(CONFIG_TEGRA186_GPC_DMA) += tegra186-gpc-dma.o
|
||||
@ -88,5 +85,6 @@ obj-$(CONFIG_INTEL_LDMA) += lgm/
|
||||
|
||||
obj-y += mediatek/
|
||||
obj-y += qcom/
|
||||
obj-y += stm32/
|
||||
obj-y += ti/
|
||||
obj-y += xilinx/
|
||||
|
||||
@ -233,7 +233,7 @@ static void msgdma_free_descriptor(struct msgdma_device *mdev,
|
||||
struct msgdma_sw_desc *child, *next;
|
||||
|
||||
mdev->desc_free_cnt++;
|
||||
list_add_tail(&desc->node, &mdev->free_list);
|
||||
list_move_tail(&desc->node, &mdev->free_list);
|
||||
list_for_each_entry_safe(child, next, &desc->tx_list, node) {
|
||||
mdev->desc_free_cnt++;
|
||||
list_move_tail(&child->node, &mdev->free_list);
|
||||
@ -583,22 +583,25 @@ static void msgdma_issue_pending(struct dma_chan *chan)
|
||||
static void msgdma_chan_desc_cleanup(struct msgdma_device *mdev)
|
||||
{
|
||||
struct msgdma_sw_desc *desc, *next;
|
||||
unsigned long irqflags;
|
||||
|
||||
spin_lock_irqsave(&mdev->lock, irqflags);
|
||||
|
||||
list_for_each_entry_safe(desc, next, &mdev->done_list, node) {
|
||||
struct dmaengine_desc_callback cb;
|
||||
|
||||
list_del(&desc->node);
|
||||
|
||||
dmaengine_desc_get_callback(&desc->async_tx, &cb);
|
||||
if (dmaengine_desc_callback_valid(&cb)) {
|
||||
spin_unlock(&mdev->lock);
|
||||
spin_unlock_irqrestore(&mdev->lock, irqflags);
|
||||
dmaengine_desc_callback_invoke(&cb, NULL);
|
||||
spin_lock(&mdev->lock);
|
||||
spin_lock_irqsave(&mdev->lock, irqflags);
|
||||
}
|
||||
|
||||
/* Run any dependencies, then free the descriptor */
|
||||
msgdma_free_descriptor(mdev, desc);
|
||||
}
|
||||
|
||||
spin_unlock_irqrestore(&mdev->lock, irqflags);
|
||||
}
|
||||
|
||||
/**
|
||||
@ -713,10 +716,11 @@ static void msgdma_tasklet(struct tasklet_struct *t)
|
||||
}
|
||||
|
||||
msgdma_complete_descriptor(mdev);
|
||||
msgdma_chan_desc_cleanup(mdev);
|
||||
}
|
||||
|
||||
spin_unlock_irqrestore(&mdev->lock, flags);
|
||||
|
||||
msgdma_chan_desc_cleanup(mdev);
|
||||
}
|
||||
|
||||
/**
|
||||
|
||||
@ -1037,7 +1037,8 @@ static int get_dma_id(struct dma_device *device)
|
||||
}
|
||||
|
||||
static int __dma_async_device_channel_register(struct dma_device *device,
|
||||
struct dma_chan *chan)
|
||||
struct dma_chan *chan,
|
||||
const char *name)
|
||||
{
|
||||
int rc;
|
||||
|
||||
@ -1066,8 +1067,10 @@ static int __dma_async_device_channel_register(struct dma_device *device,
|
||||
chan->dev->device.parent = device->dev;
|
||||
chan->dev->chan = chan;
|
||||
chan->dev->dev_id = device->dev_id;
|
||||
dev_set_name(&chan->dev->device, "dma%dchan%d",
|
||||
device->dev_id, chan->chan_id);
|
||||
if (!name)
|
||||
dev_set_name(&chan->dev->device, "dma%dchan%d", device->dev_id, chan->chan_id);
|
||||
else
|
||||
dev_set_name(&chan->dev->device, name);
|
||||
rc = device_register(&chan->dev->device);
|
||||
if (rc)
|
||||
goto err_out_ida;
|
||||
@ -1087,11 +1090,12 @@ static int __dma_async_device_channel_register(struct dma_device *device,
|
||||
}
|
||||
|
||||
int dma_async_device_channel_register(struct dma_device *device,
|
||||
struct dma_chan *chan)
|
||||
struct dma_chan *chan,
|
||||
const char *name)
|
||||
{
|
||||
int rc;
|
||||
|
||||
rc = __dma_async_device_channel_register(device, chan);
|
||||
rc = __dma_async_device_channel_register(device, chan, name);
|
||||
if (rc < 0)
|
||||
return rc;
|
||||
|
||||
@ -1203,7 +1207,7 @@ int dma_async_device_register(struct dma_device *device)
|
||||
|
||||
/* represent channels in sysfs. Probably want devs too */
|
||||
list_for_each_entry(chan, &device->channels, device_node) {
|
||||
rc = __dma_async_device_channel_register(device, chan);
|
||||
rc = __dma_async_device_channel_register(device, chan, NULL);
|
||||
if (rc < 0)
|
||||
goto err_out;
|
||||
}
|
||||
|
||||
@ -1372,4 +1372,5 @@ static void __exit dmatest_exit(void)
|
||||
module_exit(dmatest_exit);
|
||||
|
||||
MODULE_AUTHOR("Haavard Skinnemoen (Atmel)");
|
||||
MODULE_DESCRIPTION("DMA Engine test module");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
|
||||
@ -367,4 +367,5 @@ int dpdmai_get_tx_queue(struct fsl_mc_io *mc_io, u32 cmd_flags,
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(dpdmai_get_tx_queue);
|
||||
|
||||
MODULE_DESCRIPTION("NXP DPAA2 QDMA driver");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
|
||||
@ -59,7 +59,6 @@ void fsl_edma_tx_chan_handler(struct fsl_edma_chan *fsl_chan)
|
||||
vchan_cookie_complete(&fsl_chan->edesc->vdesc);
|
||||
fsl_chan->edesc = NULL;
|
||||
fsl_chan->status = DMA_COMPLETE;
|
||||
fsl_chan->idle = true;
|
||||
} else {
|
||||
vchan_cyclic_callback(&fsl_chan->edesc->vdesc);
|
||||
}
|
||||
@ -239,7 +238,7 @@ int fsl_edma_terminate_all(struct dma_chan *chan)
|
||||
spin_lock_irqsave(&fsl_chan->vchan.lock, flags);
|
||||
fsl_edma_disable_request(fsl_chan);
|
||||
fsl_chan->edesc = NULL;
|
||||
fsl_chan->idle = true;
|
||||
fsl_chan->status = DMA_COMPLETE;
|
||||
vchan_get_all_descriptors(&fsl_chan->vchan, &head);
|
||||
spin_unlock_irqrestore(&fsl_chan->vchan.lock, flags);
|
||||
vchan_dma_desc_free_list(&fsl_chan->vchan, &head);
|
||||
@ -259,7 +258,6 @@ int fsl_edma_pause(struct dma_chan *chan)
|
||||
if (fsl_chan->edesc) {
|
||||
fsl_edma_disable_request(fsl_chan);
|
||||
fsl_chan->status = DMA_PAUSED;
|
||||
fsl_chan->idle = true;
|
||||
}
|
||||
spin_unlock_irqrestore(&fsl_chan->vchan.lock, flags);
|
||||
return 0;
|
||||
@ -274,7 +272,6 @@ int fsl_edma_resume(struct dma_chan *chan)
|
||||
if (fsl_chan->edesc) {
|
||||
fsl_edma_enable_request(fsl_chan);
|
||||
fsl_chan->status = DMA_IN_PROGRESS;
|
||||
fsl_chan->idle = false;
|
||||
}
|
||||
spin_unlock_irqrestore(&fsl_chan->vchan.lock, flags);
|
||||
return 0;
|
||||
@ -758,6 +755,8 @@ struct dma_async_tx_descriptor *fsl_edma_prep_memcpy(struct dma_chan *chan,
|
||||
fsl_desc->iscyclic = false;
|
||||
|
||||
fsl_chan->is_sw = true;
|
||||
if (fsl_edma_drvflags(fsl_chan) & FSL_EDMA_DRV_MEM_REMOTE)
|
||||
fsl_chan->is_remote = true;
|
||||
|
||||
/* To match with copy_align and max_seg_size so 1 tcd is enough */
|
||||
fsl_edma_fill_tcd(fsl_chan, fsl_desc->tcd[0].vtcd, dma_src, dma_dst,
|
||||
@ -780,7 +779,6 @@ void fsl_edma_xfer_desc(struct fsl_edma_chan *fsl_chan)
|
||||
fsl_edma_set_tcd_regs(fsl_chan, fsl_chan->edesc->tcd[0].vtcd);
|
||||
fsl_edma_enable_request(fsl_chan);
|
||||
fsl_chan->status = DMA_IN_PROGRESS;
|
||||
fsl_chan->idle = false;
|
||||
}
|
||||
|
||||
void fsl_edma_issue_pending(struct dma_chan *chan)
|
||||
@ -805,6 +803,7 @@ void fsl_edma_issue_pending(struct dma_chan *chan)
|
||||
int fsl_edma_alloc_chan_resources(struct dma_chan *chan)
|
||||
{
|
||||
struct fsl_edma_chan *fsl_chan = to_fsl_edma_chan(chan);
|
||||
int ret;
|
||||
|
||||
if (fsl_edma_drvflags(fsl_chan) & FSL_EDMA_DRV_HAS_CHCLK)
|
||||
clk_prepare_enable(fsl_chan->clk);
|
||||
@ -813,6 +812,17 @@ int fsl_edma_alloc_chan_resources(struct dma_chan *chan)
|
||||
fsl_edma_drvflags(fsl_chan) & FSL_EDMA_DRV_TCD64 ?
|
||||
sizeof(struct fsl_edma_hw_tcd64) : sizeof(struct fsl_edma_hw_tcd),
|
||||
32, 0);
|
||||
|
||||
if (fsl_chan->txirq) {
|
||||
ret = request_irq(fsl_chan->txirq, fsl_chan->irq_handler, IRQF_SHARED,
|
||||
fsl_chan->chan_name, fsl_chan);
|
||||
|
||||
if (ret) {
|
||||
dma_pool_destroy(fsl_chan->tcd_pool);
|
||||
return ret;
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
@ -832,11 +842,15 @@ void fsl_edma_free_chan_resources(struct dma_chan *chan)
|
||||
fsl_edma_unprep_slave_dma(fsl_chan);
|
||||
spin_unlock_irqrestore(&fsl_chan->vchan.lock, flags);
|
||||
|
||||
if (fsl_chan->txirq)
|
||||
free_irq(fsl_chan->txirq, fsl_chan);
|
||||
|
||||
vchan_dma_desc_free_list(&fsl_chan->vchan, &head);
|
||||
dma_pool_destroy(fsl_chan->tcd_pool);
|
||||
fsl_chan->tcd_pool = NULL;
|
||||
fsl_chan->is_sw = false;
|
||||
fsl_chan->srcid = 0;
|
||||
fsl_chan->is_remote = false;
|
||||
if (fsl_edma_drvflags(fsl_chan) & FSL_EDMA_DRV_HAS_CHCLK)
|
||||
clk_disable_unprepare(fsl_chan->clk);
|
||||
}
|
||||
|
||||
@ -150,7 +150,6 @@ struct fsl_edma_chan {
|
||||
struct virt_dma_chan vchan;
|
||||
enum dma_status status;
|
||||
enum fsl_edma_pm_state pm_state;
|
||||
bool idle;
|
||||
struct fsl_edma_engine *edma;
|
||||
struct fsl_edma_desc *edesc;
|
||||
struct dma_slave_config cfg;
|
||||
@ -172,6 +171,7 @@ struct fsl_edma_chan {
|
||||
int priority;
|
||||
int hw_chanid;
|
||||
int txirq;
|
||||
irqreturn_t (*irq_handler)(int irq, void *dev_id);
|
||||
bool is_rxchan;
|
||||
bool is_remote;
|
||||
bool is_multi_fifo;
|
||||
@ -194,6 +194,7 @@ struct fsl_edma_desc {
|
||||
#define FSL_EDMA_DRV_HAS_PD BIT(5)
|
||||
#define FSL_EDMA_DRV_HAS_CHCLK BIT(6)
|
||||
#define FSL_EDMA_DRV_HAS_CHMUX BIT(7)
|
||||
#define FSL_EDMA_DRV_MEM_REMOTE BIT(8)
|
||||
/* control and status register is in tcd address space, edma3 reg layout */
|
||||
#define FSL_EDMA_DRV_SPLIT_REG BIT(9)
|
||||
#define FSL_EDMA_DRV_BUS_8BYTE BIT(10)
|
||||
@ -455,7 +456,6 @@ static inline struct fsl_edma_desc *to_fsl_edma_desc(struct virt_dma_desc *vd)
|
||||
static inline void fsl_edma_err_chan_handler(struct fsl_edma_chan *fsl_chan)
|
||||
{
|
||||
fsl_chan->status = DMA_ERROR;
|
||||
fsl_chan->idle = true;
|
||||
}
|
||||
|
||||
void fsl_edma_tx_chan_handler(struct fsl_edma_chan *fsl_chan);
|
||||
|
||||
@ -65,6 +65,13 @@ static irqreturn_t fsl_edma3_tx_handler(int irq, void *dev_id)
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
static irqreturn_t fsl_edma2_tx_handler(int irq, void *devi_id)
|
||||
{
|
||||
struct fsl_edma_chan *fsl_chan = devi_id;
|
||||
|
||||
return fsl_edma_tx_handler(irq, fsl_chan->edma);
|
||||
}
|
||||
|
||||
static irqreturn_t fsl_edma_err_handler(int irq, void *dev_id)
|
||||
{
|
||||
struct fsl_edma_engine *fsl_edma = dev_id;
|
||||
@ -228,7 +235,6 @@ fsl_edma_irq_init(struct platform_device *pdev, struct fsl_edma_engine *fsl_edma
|
||||
|
||||
static int fsl_edma3_irq_init(struct platform_device *pdev, struct fsl_edma_engine *fsl_edma)
|
||||
{
|
||||
int ret;
|
||||
int i;
|
||||
|
||||
for (i = 0; i < fsl_edma->n_chans; i++) {
|
||||
@ -243,13 +249,7 @@ static int fsl_edma3_irq_init(struct platform_device *pdev, struct fsl_edma_engi
|
||||
if (fsl_chan->txirq < 0)
|
||||
return -EINVAL;
|
||||
|
||||
ret = devm_request_irq(&pdev->dev, fsl_chan->txirq,
|
||||
fsl_edma3_tx_handler, IRQF_SHARED,
|
||||
fsl_chan->chan_name, fsl_chan);
|
||||
if (ret) {
|
||||
dev_err(&pdev->dev, "Can't register chan%d's IRQ.\n", i);
|
||||
return -EINVAL;
|
||||
}
|
||||
fsl_chan->irq_handler = fsl_edma3_tx_handler;
|
||||
}
|
||||
|
||||
return 0;
|
||||
@ -278,19 +278,20 @@ fsl_edma2_irq_init(struct platform_device *pdev,
|
||||
*/
|
||||
for (i = 0; i < count; i++) {
|
||||
irq = platform_get_irq(pdev, i);
|
||||
ret = 0;
|
||||
if (irq < 0)
|
||||
return -ENXIO;
|
||||
|
||||
/* The last IRQ is for eDMA err */
|
||||
if (i == count - 1)
|
||||
if (i == count - 1) {
|
||||
ret = devm_request_irq(&pdev->dev, irq,
|
||||
fsl_edma_err_handler,
|
||||
0, "eDMA2-ERR", fsl_edma);
|
||||
else
|
||||
ret = devm_request_irq(&pdev->dev, irq,
|
||||
fsl_edma_tx_handler, 0,
|
||||
fsl_edma->chans[i].chan_name,
|
||||
fsl_edma);
|
||||
} else {
|
||||
fsl_edma->chans[i].txirq = irq;
|
||||
fsl_edma->chans[i].irq_handler = fsl_edma2_tx_handler;
|
||||
}
|
||||
|
||||
if (ret)
|
||||
return ret;
|
||||
}
|
||||
@ -342,7 +343,7 @@ static struct fsl_edma_drvdata imx7ulp_data = {
|
||||
};
|
||||
|
||||
static struct fsl_edma_drvdata imx8qm_data = {
|
||||
.flags = FSL_EDMA_DRV_HAS_PD | FSL_EDMA_DRV_EDMA3,
|
||||
.flags = FSL_EDMA_DRV_HAS_PD | FSL_EDMA_DRV_EDMA3 | FSL_EDMA_DRV_MEM_REMOTE,
|
||||
.chreg_space_sz = 0x10000,
|
||||
.chreg_off = 0x10000,
|
||||
.setup_irq = fsl_edma3_irq_init,
|
||||
@ -543,7 +544,6 @@ static int fsl_edma_probe(struct platform_device *pdev)
|
||||
fsl_chan->edma = fsl_edma;
|
||||
fsl_chan->pm_state = RUNNING;
|
||||
fsl_chan->srcid = 0;
|
||||
fsl_chan->idle = true;
|
||||
fsl_chan->dma_dir = DMA_NONE;
|
||||
fsl_chan->vchan.desc_free = fsl_edma_free_desc;
|
||||
|
||||
@ -668,7 +668,7 @@ static int fsl_edma_suspend_late(struct device *dev)
|
||||
continue;
|
||||
spin_lock_irqsave(&fsl_chan->vchan.lock, flags);
|
||||
/* Make sure chan is idle or will force disable. */
|
||||
if (unlikely(!fsl_chan->idle)) {
|
||||
if (unlikely(fsl_chan->status == DMA_IN_PROGRESS)) {
|
||||
dev_warn(dev, "WARN: There is non-idle channel.");
|
||||
fsl_edma_disable_request(fsl_chan);
|
||||
fsl_edma_chan_mux(fsl_chan, 0, false);
|
||||
|
||||
@ -269,7 +269,7 @@ static int idxd_register_dma_channel(struct idxd_wq *wq)
|
||||
desc->txd.tx_submit = idxd_dma_tx_submit;
|
||||
}
|
||||
|
||||
rc = dma_async_device_channel_register(dma, chan);
|
||||
rc = dma_async_device_channel_register(dma, chan, NULL);
|
||||
if (rc < 0) {
|
||||
kfree(idxd_chan);
|
||||
return rc;
|
||||
|
||||
@ -22,6 +22,7 @@
|
||||
#include "perfmon.h"
|
||||
|
||||
MODULE_VERSION(IDXD_DRIVER_VERSION);
|
||||
MODULE_DESCRIPTION("Intel Data Streaming Accelerator and In-Memory Analytics Accelerator common driver");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
MODULE_AUTHOR("Intel Corporation");
|
||||
MODULE_IMPORT_NS(IDXD);
|
||||
|
||||
@ -2107,8 +2107,7 @@ static int sdma_get_firmware(struct sdma_engine *sdma,
|
||||
{
|
||||
int ret;
|
||||
|
||||
ret = request_firmware_nowait(THIS_MODULE,
|
||||
FW_ACTION_UEVENT, fw_name, sdma->dev,
|
||||
ret = firmware_request_nowait_nowarn(THIS_MODULE, fw_name, sdma->dev,
|
||||
GFP_KERNEL, sdma, sdma_load_firmware);
|
||||
|
||||
return ret;
|
||||
|
||||
@ -23,6 +23,7 @@
|
||||
#include "../dmaengine.h"
|
||||
|
||||
MODULE_VERSION(IOAT_DMA_VERSION);
|
||||
MODULE_DESCRIPTION("Intel I/OAT DMA Linux driver");
|
||||
MODULE_LICENSE("Dual BSD/GPL");
|
||||
MODULE_AUTHOR("Intel Corporation");
|
||||
|
||||
|
||||
@ -64,7 +64,6 @@ static irqreturn_t mcf_edma_err_handler(int irq, void *dev_id)
|
||||
fsl_edma_disable_request(&mcf_edma->chans[ch]);
|
||||
iowrite8(EDMA_CERR_CERR(ch), regs->cerr);
|
||||
mcf_edma->chans[ch].status = DMA_ERROR;
|
||||
mcf_edma->chans[ch].idle = true;
|
||||
}
|
||||
}
|
||||
|
||||
@ -196,7 +195,6 @@ static int mcf_edma_probe(struct platform_device *pdev)
|
||||
|
||||
mcf_chan->edma = mcf_edma;
|
||||
mcf_chan->srcid = i;
|
||||
mcf_chan->idle = true;
|
||||
mcf_chan->dma_dir = DMA_NONE;
|
||||
mcf_chan->vchan.desc_free = fsl_edma_free_desc;
|
||||
vchan_init(&mcf_chan->vchan, &mcf_edma->dma_dev);
|
||||
|
||||
@ -148,11 +148,6 @@ struct moxart_dmadev {
|
||||
unsigned int irq;
|
||||
};
|
||||
|
||||
struct moxart_filter_data {
|
||||
struct moxart_dmadev *mdc;
|
||||
struct of_phandle_args *dma_spec;
|
||||
};
|
||||
|
||||
static const unsigned int es_bytes[] = {
|
||||
[MOXART_DMA_DATA_TYPE_S8] = 1,
|
||||
[MOXART_DMA_DATA_TYPE_S16] = 2,
|
||||
|
||||
@ -476,12 +476,6 @@ struct gpi_dev {
|
||||
struct gpii *gpiis;
|
||||
};
|
||||
|
||||
struct reg_info {
|
||||
char *name;
|
||||
u32 offset;
|
||||
u32 val;
|
||||
};
|
||||
|
||||
struct gchan {
|
||||
struct virt_dma_chan vc;
|
||||
u32 chid;
|
||||
@ -1197,7 +1191,6 @@ static int gpi_reset_chan(struct gchan *gchan, enum gpi_cmd gpi_cmd)
|
||||
{
|
||||
struct gpii *gpii = gchan->gpii;
|
||||
struct gpi_ring *ch_ring = &gchan->ch_ring;
|
||||
unsigned long flags;
|
||||
LIST_HEAD(list);
|
||||
int ret;
|
||||
|
||||
@ -1220,9 +1213,9 @@ static int gpi_reset_chan(struct gchan *gchan, enum gpi_cmd gpi_cmd)
|
||||
gpi_mark_stale_events(gchan);
|
||||
|
||||
/* remove all async descriptors */
|
||||
spin_lock_irqsave(&gchan->vc.lock, flags);
|
||||
spin_lock(&gchan->vc.lock);
|
||||
vchan_get_all_descriptors(&gchan->vc, &list);
|
||||
spin_unlock_irqrestore(&gchan->vc.lock, flags);
|
||||
spin_unlock(&gchan->vc.lock);
|
||||
write_unlock_irq(&gpii->pm_lock);
|
||||
vchan_dma_desc_free_list(&gchan->vc, &list);
|
||||
|
||||
|
||||
@ -957,4 +957,5 @@ static struct platform_driver hidma_driver = {
|
||||
};
|
||||
|
||||
module_platform_driver(hidma_driver);
|
||||
MODULE_DESCRIPTION("Qualcomm Technologies HIDMA Channel support");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
|
||||
@ -331,4 +331,5 @@ static struct platform_driver hidma_mgmt_driver = {
|
||||
};
|
||||
|
||||
module_platform_driver(hidma_mgmt_driver);
|
||||
MODULE_DESCRIPTION("Qualcomm Technologies HIDMA DMA engine interface");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
|
||||
@ -540,8 +540,8 @@ static int rz_dmac_terminate_all(struct dma_chan *chan)
|
||||
spin_lock_irqsave(&channel->vc.lock, flags);
|
||||
list_splice_tail_init(&channel->ld_active, &channel->ld_free);
|
||||
list_splice_tail_init(&channel->ld_queue, &channel->ld_free);
|
||||
spin_unlock_irqrestore(&channel->vc.lock, flags);
|
||||
vchan_get_all_descriptors(&channel->vc, &head);
|
||||
spin_unlock_irqrestore(&channel->vc.lock, flags);
|
||||
vchan_dma_desc_free_list(&channel->vc, &head);
|
||||
|
||||
return 0;
|
||||
|
||||
47
drivers/dma/stm32/Kconfig
Normal file
47
drivers/dma/stm32/Kconfig
Normal file
@ -0,0 +1,47 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only
|
||||
#
|
||||
# STM32 DMA controllers drivers
|
||||
#
|
||||
if ARCH_STM32 || COMPILE_TEST
|
||||
|
||||
config STM32_DMA
|
||||
bool "STMicroelectronics STM32 DMA support"
|
||||
select DMA_ENGINE
|
||||
select DMA_VIRTUAL_CHANNELS
|
||||
help
|
||||
Enable support for the on-chip DMA controller on STMicroelectronics
|
||||
STM32 platforms.
|
||||
If you have a board based on STM32 SoC with such DMA controller
|
||||
and want to use DMA say Y here.
|
||||
|
||||
config STM32_DMAMUX
|
||||
bool "STMicroelectronics STM32 DMA multiplexer support"
|
||||
depends on STM32_DMA
|
||||
help
|
||||
Enable support for the on-chip DMA multiplexer on STMicroelectronics
|
||||
STM32 platforms.
|
||||
If you have a board based on STM32 SoC with such DMA multiplexer
|
||||
and want to use DMAMUX say Y here.
|
||||
|
||||
config STM32_MDMA
|
||||
bool "STMicroelectronics STM32 master DMA support"
|
||||
depends on OF
|
||||
select DMA_ENGINE
|
||||
select DMA_VIRTUAL_CHANNELS
|
||||
help
|
||||
Enable support for the on-chip MDMA controller on STMicroelectronics
|
||||
STM32 platforms.
|
||||
If you have a board based on STM32 SoC with such DMA controller
|
||||
and want to use MDMA say Y here.
|
||||
|
||||
config STM32_DMA3
|
||||
tristate "STMicroelectronics STM32 DMA3 support"
|
||||
select DMA_ENGINE
|
||||
select DMA_VIRTUAL_CHANNELS
|
||||
help
|
||||
Enable support for the on-chip DMA3 controller on STMicroelectronics
|
||||
STM32 platforms.
|
||||
If you have a board based on STM32 SoC with such DMA3 controller
|
||||
and want to use DMA3, say Y here.
|
||||
|
||||
endif
|
||||
5
drivers/dma/stm32/Makefile
Normal file
5
drivers/dma/stm32/Makefile
Normal file
@ -0,0 +1,5 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only
|
||||
obj-$(CONFIG_STM32_DMA) += stm32-dma.o
|
||||
obj-$(CONFIG_STM32_DMAMUX) += stm32-dmamux.o
|
||||
obj-$(CONFIG_STM32_MDMA) += stm32-mdma.o
|
||||
obj-$(CONFIG_STM32_DMA3) += stm32-dma3.o
|
||||
@ -28,7 +28,7 @@
|
||||
#include <linux/sched.h>
|
||||
#include <linux/slab.h>
|
||||
|
||||
#include "virt-dma.h"
|
||||
#include "../virt-dma.h"
|
||||
|
||||
#define STM32_DMA_LISR 0x0000 /* DMA Low Int Status Reg */
|
||||
#define STM32_DMA_HISR 0x0004 /* DMA High Int Status Reg */
|
||||
1847
drivers/dma/stm32/stm32-dma3.c
Normal file
1847
drivers/dma/stm32/stm32-dma3.c
Normal file
File diff suppressed because it is too large
Load Diff
@ -30,7 +30,7 @@
|
||||
#include <linux/reset.h>
|
||||
#include <linux/slab.h>
|
||||
|
||||
#include "virt-dma.h"
|
||||
#include "../virt-dma.h"
|
||||
|
||||
#define STM32_MDMA_GISR0 0x0000 /* MDMA Int Status Reg 1 */
|
||||
|
||||
@ -1252,5 +1252,6 @@ static struct platform_driver cpp41_dma_driver = {
|
||||
};
|
||||
|
||||
module_platform_driver(cpp41_dma_driver);
|
||||
MODULE_DESCRIPTION("Texas Instruments CPPI 4.1 DMA support");
|
||||
MODULE_LICENSE("GPL");
|
||||
MODULE_AUTHOR("Sebastian Andrzej Siewior <bigeasy@linutronix.de>");
|
||||
|
||||
@ -106,4 +106,5 @@ int psil_set_new_ep_config(struct device *dev, const char *name,
|
||||
return 0;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(psil_set_new_ep_config);
|
||||
MODULE_DESCRIPTION("K3 PSI-L endpoint configuration");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
|
||||
@ -1574,4 +1574,5 @@ static int __init k3_udma_glue_class_init(void)
|
||||
}
|
||||
|
||||
module_init(k3_udma_glue_class_init);
|
||||
MODULE_DESCRIPTION("TI K3 NAVSS DMA glue interface");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
|
||||
@ -4405,6 +4405,7 @@ static const struct of_device_id udma_of_match[] = {
|
||||
},
|
||||
{ /* Sentinel */ },
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, udma_of_match);
|
||||
|
||||
static struct udma_soc_data am654_soc_data = {
|
||||
.oes = {
|
||||
@ -4472,7 +4473,9 @@ static int udma_get_mmrs(struct platform_device *pdev, struct udma_dev *ud)
|
||||
ud->rchan_cnt = UDMA_CAP2_RCHAN_CNT(cap2);
|
||||
break;
|
||||
case DMA_TYPE_BCDMA:
|
||||
ud->bchan_cnt = BCDMA_CAP2_BCHAN_CNT(cap2);
|
||||
ud->bchan_cnt = BCDMA_CAP2_BCHAN_CNT(cap2) +
|
||||
BCDMA_CAP3_HBCHAN_CNT(cap3) +
|
||||
BCDMA_CAP3_UBCHAN_CNT(cap3);
|
||||
ud->tchan_cnt = BCDMA_CAP2_TCHAN_CNT(cap2);
|
||||
ud->rchan_cnt = BCDMA_CAP2_RCHAN_CNT(cap2);
|
||||
ud->rflow_cnt = ud->rchan_cnt;
|
||||
@ -5621,6 +5624,7 @@ static struct platform_driver udma_driver = {
|
||||
};
|
||||
|
||||
module_platform_driver(udma_driver);
|
||||
MODULE_DESCRIPTION("Texas Instruments UDMA support");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
|
||||
/* Private interfaces to UDMA */
|
||||
|
||||
@ -1950,4 +1950,5 @@ static void __exit omap_dma_exit(void)
|
||||
module_exit(omap_dma_exit);
|
||||
|
||||
MODULE_AUTHOR("Russell King");
|
||||
MODULE_DESCRIPTION("Texas Instruments sDMA DMAengine support");
|
||||
MODULE_LICENSE("GPL");
|
||||
|
||||
@ -139,4 +139,5 @@ void vchan_init(struct virt_dma_chan *vc, struct dma_device *dmadev)
|
||||
EXPORT_SYMBOL_GPL(vchan_init);
|
||||
|
||||
MODULE_AUTHOR("Russell King");
|
||||
MODULE_DESCRIPTION("Virtual DMA channel support for DMAengine");
|
||||
MODULE_LICENSE("GPL");
|
||||
|
||||
@ -1608,7 +1608,8 @@ int dma_async_device_register(struct dma_device *device);
|
||||
int dmaenginem_async_device_register(struct dma_device *device);
|
||||
void dma_async_device_unregister(struct dma_device *device);
|
||||
int dma_async_device_channel_register(struct dma_device *device,
|
||||
struct dma_chan *chan);
|
||||
struct dma_chan *chan,
|
||||
const char *name);
|
||||
void dma_async_device_channel_unregister(struct dma_device *device,
|
||||
struct dma_chan *chan);
|
||||
void dma_run_dependencies(struct dma_async_tx_descriptor *tx);
|
||||
|
||||
@ -98,6 +98,10 @@ static inline bool firmware_request_builtin(struct firmware *fw,
|
||||
#if IS_REACHABLE(CONFIG_FW_LOADER)
|
||||
int request_firmware(const struct firmware **fw, const char *name,
|
||||
struct device *device);
|
||||
int firmware_request_nowait_nowarn(
|
||||
struct module *module, const char *name,
|
||||
struct device *device, gfp_t gfp, void *context,
|
||||
void (*cont)(const struct firmware *fw, void *context));
|
||||
int firmware_request_nowarn(const struct firmware **fw, const char *name,
|
||||
struct device *device);
|
||||
int firmware_request_platform(const struct firmware **fw, const char *name,
|
||||
@ -123,6 +127,14 @@ static inline int request_firmware(const struct firmware **fw,
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
static inline int firmware_request_nowait_nowarn(
|
||||
struct module *module, const char *name,
|
||||
struct device *device, gfp_t gfp, void *context,
|
||||
void (*cont)(const struct firmware *fw, void *context))
|
||||
{
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
static inline int firmware_request_nowarn(const struct firmware **fw,
|
||||
const char *name,
|
||||
struct device *device)
|
||||
|
||||
Loading…
Reference in New Issue
Block a user