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drm/amdgpu: create function to check RAS RMA status
In the convenience of calling it globally. Signed-off-by: Tao Zhou <tao.zhou1@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -2153,7 +2153,7 @@ static void amdgpu_ras_interrupt_poison_consumption_handler(struct ras_manager *
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/* gpu reset is fallback for failed and default cases.
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* For RMA case, amdgpu_umc_poison_handler will handle gpu reset.
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*/
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if (poison_stat && !con->is_rma) {
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if (poison_stat && !amdgpu_ras_is_rma(adev)) {
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event_id = amdgpu_ras_acquire_event_id(adev, type);
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RAS_EVENT_LOG(adev, event_id,
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"GPU reset for %s RAS poison consumption is issued!\n",
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@ -2945,7 +2945,7 @@ static void amdgpu_ras_do_page_retirement(struct work_struct *work)
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amdgpu_ras_error_data_fini(&err_data);
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if (err_cnt && con->is_rma)
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if (err_cnt && amdgpu_ras_is_rma(adev))
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amdgpu_ras_reset_gpu(adev);
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amdgpu_ras_schedule_retirement_dwork(con,
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@ -3046,7 +3046,7 @@ static int amdgpu_ras_poison_consumption_handler(struct amdgpu_device *adev,
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}
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/* for RMA, amdgpu_ras_poison_creation_handler will trigger gpu reset */
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if (reset_flags && !con->is_rma) {
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if (reset_flags && !amdgpu_ras_is_rma(adev)) {
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if (reset_flags & AMDGPU_RAS_GPU_RESET_MODE1_RESET)
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reset = AMDGPU_RAS_GPU_RESET_MODE1_RESET;
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else if (reset_flags & AMDGPU_RAS_GPU_RESET_MODE2_RESET)
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@ -3192,7 +3192,7 @@ int amdgpu_ras_recovery_init(struct amdgpu_device *adev)
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* This calling fails when is_rma is true or
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* ret != 0.
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*/
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if (con->is_rma || ret)
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if (amdgpu_ras_is_rma(adev) || ret)
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goto free;
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if (con->eeprom_control.ras_num_recs) {
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@ -3241,7 +3241,7 @@ out:
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* Except error threshold exceeding case, other failure cases in this
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* function would not fail amdgpu driver init.
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*/
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if (!con->is_rma)
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if (!amdgpu_ras_is_rma(adev))
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ret = 0;
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else
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ret = -EINVAL;
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@ -4284,7 +4284,7 @@ int amdgpu_ras_reset_gpu(struct amdgpu_device *adev)
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struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
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/* mode1 is the only selection for RMA status */
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if (ras->is_rma) {
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if (amdgpu_ras_is_rma(adev)) {
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ras->gpu_reset_flags = 0;
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ras->gpu_reset_flags |= AMDGPU_RAS_GPU_RESET_MODE1_RESET;
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}
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@ -4824,3 +4824,13 @@ void amdgpu_ras_event_log_print(struct amdgpu_device *adev, u64 event_id,
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va_end(args);
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}
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bool amdgpu_ras_is_rma(struct amdgpu_device *adev)
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{
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struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
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if (!con)
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return false;
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return con->is_rma;
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}
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@ -974,4 +974,5 @@ __printf(3, 4)
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void amdgpu_ras_event_log_print(struct amdgpu_device *adev, u64 event_id,
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const char *fmt, ...);
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bool amdgpu_ras_is_rma(struct amdgpu_device *adev);
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#endif
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@ -196,7 +196,7 @@ static int amdgpu_umc_do_page_retirement(struct amdgpu_device *adev,
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amdgpu_umc_handle_bad_pages(adev, ras_error_status);
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if ((err_data->ue_count || err_data->de_count) &&
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(reset || (con && con->is_rma))) {
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(reset || amdgpu_ras_is_rma(adev))) {
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con->gpu_reset_flags |= reset;
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amdgpu_ras_reset_gpu(adev);
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}
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@ -97,7 +97,7 @@ static int gfx_v11_0_3_poison_consumption_handler(struct amdgpu_device *adev,
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ras->gpu_reset_flags |= AMDGPU_RAS_GPU_RESET_MODE2_RESET;
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}
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if (con && !con->is_rma)
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if (con && !amdgpu_ras_is_rma(adev))
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amdgpu_ras_reset_gpu(adev);
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}
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