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MIPS: SGI-IP30: Move irq bits to better header files
Move HEART specific parts of mach-ip30/irq.h to asm/sgi/heart.h and IP30 specific parts to sgi-ip30/ip30-common.h. Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
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Thomas Bogendoerfer
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bc1c969f11
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7895d662ba
@ -1,87 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* HEART IRQ defines
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*
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* Copyright (C) 2009 Johannes Dickgreber <tanzy@gmx.de>
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* 2014-2016 Joshua Kinard <kumba@gentoo.org>
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*
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*/
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#ifndef __ASM_MACH_IP30_IRQ_H
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#define __ASM_MACH_IP30_IRQ_H
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/*
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* HEART has 64 hardware interrupts, but use 128 to leave room for a few
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* software interrupts as well (such as the CPU timer interrupt.
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*/
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#define NR_IRQS 128
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extern void __init ip30_install_ipi(void);
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/*
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* HEART has 64 interrupt vectors available to it, subdivided into five
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* priority levels. They are numbered 0 to 63.
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*/
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#define HEART_NUM_IRQS 64
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/*
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* These are the five interrupt priority levels and their corresponding
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* CPU IPx interrupt pins.
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*
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* Level 4 - Error Interrupts.
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* Level 3 - HEART timer interrupt.
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* Level 2 - CPU IPI, CPU debug, power putton, general device interrupts.
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* Level 1 - General device interrupts.
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* Level 0 - General device GFX flow control interrupts.
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*/
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#define HEART_L4_INT_MASK 0xfff8000000000000ULL /* IP6 */
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#define HEART_L3_INT_MASK 0x0004000000000000ULL /* IP5 */
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#define HEART_L2_INT_MASK 0x0003ffff00000000ULL /* IP4 */
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#define HEART_L1_INT_MASK 0x00000000ffff0000ULL /* IP3 */
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#define HEART_L0_INT_MASK 0x000000000000ffffULL /* IP2 */
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/* HEART L0 Interrupts (Low Priority) */
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#define HEART_L0_INT_GENERIC 0
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#define HEART_L0_INT_FLOW_CTRL_HWTR_0 1
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#define HEART_L0_INT_FLOW_CTRL_HWTR_1 2
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/* HEART L2 Interrupts (High Priority) */
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#define HEART_L2_INT_RESCHED_CPU_0 46
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#define HEART_L2_INT_RESCHED_CPU_1 47
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#define HEART_L2_INT_CALL_CPU_0 48
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#define HEART_L2_INT_CALL_CPU_1 49
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/* HEART L3 Interrupts (Compare/Counter Timer) */
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#define HEART_L3_INT_TIMER 50
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/* HEART L4 Interrupts (Errors) */
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#define HEART_L4_INT_XWID_ERR_9 51
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#define HEART_L4_INT_XWID_ERR_A 52
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#define HEART_L4_INT_XWID_ERR_B 53
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#define HEART_L4_INT_XWID_ERR_C 54
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#define HEART_L4_INT_XWID_ERR_D 55
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#define HEART_L4_INT_XWID_ERR_E 56
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#define HEART_L4_INT_XWID_ERR_F 57
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#define HEART_L4_INT_XWID_ERR_XBOW 58
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#define HEART_L4_INT_CPU_BUS_ERR_0 59
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#define HEART_L4_INT_CPU_BUS_ERR_1 60
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#define HEART_L4_INT_CPU_BUS_ERR_2 61
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#define HEART_L4_INT_CPU_BUS_ERR_3 62
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#define HEART_L4_INT_HEART_EXCP 63
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/*
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* Power Switch is wired via BaseIO BRIDGE slot #6.
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*
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* ACFail is wired via BaseIO BRIDGE slot #7.
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*/
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#define IP30_POWER_IRQ HEART_L2_INT_POWER_BTN
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#include <asm/mach-generic/irq.h>
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#define IP30_HEART_L0_IRQ (MIPS_CPU_IRQ_BASE + 2)
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#define IP30_HEART_L1_IRQ (MIPS_CPU_IRQ_BASE + 3)
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#define IP30_HEART_L2_IRQ (MIPS_CPU_IRQ_BASE + 4)
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#define IP30_HEART_TIMER_IRQ (MIPS_CPU_IRQ_BASE + 5)
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#define IP30_HEART_ERR_IRQ (MIPS_CPU_IRQ_BASE + 6)
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#endif /* __ASM_MACH_IP30_IRQ_H */
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@ -264,6 +264,57 @@ struct ip30_heart_regs { /* 0x0ff00000 */
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#define HC_NCOR_MEM_ERR BIT(1)
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#define HC_COR_MEM_ERR BIT(0)
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/*
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* HEART has 64 interrupt vectors available to it, subdivided into five
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* priority levels. They are numbered 0 to 63.
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*/
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#define HEART_NUM_IRQS 64
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/*
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* These are the five interrupt priority levels and their corresponding
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* CPU IPx interrupt pins.
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*
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* Level 4 - Error Interrupts.
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* Level 3 - HEART timer interrupt.
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* Level 2 - CPU IPI, CPU debug, power putton, general device interrupts.
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* Level 1 - General device interrupts.
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* Level 0 - General device GFX flow control interrupts.
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*/
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#define HEART_L4_INT_MASK 0xfff8000000000000ULL /* IP6 */
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#define HEART_L3_INT_MASK 0x0004000000000000ULL /* IP5 */
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#define HEART_L2_INT_MASK 0x0003ffff00000000ULL /* IP4 */
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#define HEART_L1_INT_MASK 0x00000000ffff0000ULL /* IP3 */
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#define HEART_L0_INT_MASK 0x000000000000ffffULL /* IP2 */
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/* HEART L0 Interrupts (Low Priority) */
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#define HEART_L0_INT_GENERIC 0
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#define HEART_L0_INT_FLOW_CTRL_HWTR_0 1
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#define HEART_L0_INT_FLOW_CTRL_HWTR_1 2
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/* HEART L2 Interrupts (High Priority) */
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#define HEART_L2_INT_RESCHED_CPU_0 46
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#define HEART_L2_INT_RESCHED_CPU_1 47
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#define HEART_L2_INT_CALL_CPU_0 48
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#define HEART_L2_INT_CALL_CPU_1 49
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/* HEART L3 Interrupts (Compare/Counter Timer) */
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#define HEART_L3_INT_TIMER 50
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/* HEART L4 Interrupts (Errors) */
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#define HEART_L4_INT_XWID_ERR_9 51
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#define HEART_L4_INT_XWID_ERR_A 52
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#define HEART_L4_INT_XWID_ERR_B 53
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#define HEART_L4_INT_XWID_ERR_C 54
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#define HEART_L4_INT_XWID_ERR_D 55
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#define HEART_L4_INT_XWID_ERR_E 56
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#define HEART_L4_INT_XWID_ERR_F 57
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#define HEART_L4_INT_XWID_ERR_XBOW 58
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#define HEART_L4_INT_CPU_BUS_ERR_0 59
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#define HEART_L4_INT_CPU_BUS_ERR_1 60
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#define HEART_L4_INT_CPU_BUS_ERR_2 61
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#define HEART_L4_INT_CPU_BUS_ERR_3 62
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#define HEART_L4_INT_HEART_EXCP 63
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extern struct ip30_heart_regs __iomem *heart_regs;
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#define heart_read ____raw_readq
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@ -3,6 +3,20 @@
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#ifndef __IP30_COMMON_H
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#define __IP30_COMMON_H
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/*
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* Power Switch is wired via BaseIO BRIDGE slot #6.
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*
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* ACFail is wired via BaseIO BRIDGE slot #7.
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*/
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#define IP30_POWER_IRQ HEART_L2_INT_POWER_BTN
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#define IP30_HEART_L0_IRQ (MIPS_CPU_IRQ_BASE + 2)
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#define IP30_HEART_L1_IRQ (MIPS_CPU_IRQ_BASE + 3)
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#define IP30_HEART_L2_IRQ (MIPS_CPU_IRQ_BASE + 4)
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#define IP30_HEART_TIMER_IRQ (MIPS_CPU_IRQ_BASE + 5)
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#define IP30_HEART_ERR_IRQ (MIPS_CPU_IRQ_BASE + 6)
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extern void __init ip30_install_ipi(void);
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extern struct plat_smp_ops ip30_smp_ops;
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extern void __init ip30_per_cpu_init(void);
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@ -14,6 +14,8 @@
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#include <asm/irq_cpu.h>
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#include <asm/sgi/heart.h>
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#include "ip30-common.h"
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struct heart_irq_data {
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u64 *irq_mask;
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int cpu;
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