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ASoC: SOF: Intel: MTL: Fixes for suspend/resume
Merge series from Ranjani Sridharan <ranjani.sridharan@linux.intel.com>: This series includes fixes for suspend/resume and module loading/unloading for the MTL platform.
This commit is contained in:
commit
76003e4d0d
@ -104,6 +104,8 @@ const struct sof_intel_dsp_desc apl_chip_info = {
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.quirks = SOF_INTEL_PROCEN_FMT_QUIRK,
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.check_ipc_irq = hda_dsp_check_ipc_irq,
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.cl_init = cl_dsp_init,
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.power_down_dsp = hda_power_down_dsp,
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.disable_interrupts = hda_dsp_disable_interrupts,
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.hw_ip_version = SOF_INTEL_CAVS_1_5_PLUS,
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};
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EXPORT_SYMBOL_NS(apl_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON);
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@ -412,6 +412,8 @@ const struct sof_intel_dsp_desc cnl_chip_info = {
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.check_sdw_irq = hda_common_check_sdw_irq,
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.check_ipc_irq = hda_dsp_check_ipc_irq,
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.cl_init = cl_dsp_init,
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.power_down_dsp = hda_power_down_dsp,
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.disable_interrupts = hda_dsp_disable_interrupts,
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.hw_ip_version = SOF_INTEL_CAVS_1_8,
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};
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EXPORT_SYMBOL_NS(cnl_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON);
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@ -442,6 +444,8 @@ const struct sof_intel_dsp_desc jsl_chip_info = {
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.check_sdw_irq = hda_common_check_sdw_irq,
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.check_ipc_irq = hda_dsp_check_ipc_irq,
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.cl_init = cl_dsp_init,
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.power_down_dsp = hda_power_down_dsp,
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.disable_interrupts = hda_dsp_disable_interrupts,
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.hw_ip_version = SOF_INTEL_CAVS_2_0,
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};
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EXPORT_SYMBOL_NS(jsl_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON);
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@ -629,10 +629,9 @@ static int hda_suspend(struct snd_sof_dev *sdev, bool runtime_suspend)
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sdev->fw_state == SOF_FW_BOOT_FAILED)
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hda->skip_imr_boot = true;
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hda_sdw_int_enable(sdev, false);
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/* disable IPC interrupts */
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hda_dsp_ipc_int_disable(sdev);
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ret = chip->disable_interrupts(sdev);
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if (ret < 0)
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return ret;
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#if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
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hda_codec_jack_wake_enable(sdev, runtime_suspend);
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@ -641,11 +640,9 @@ static int hda_suspend(struct snd_sof_dev *sdev, bool runtime_suspend)
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snd_hdac_ext_bus_link_power_down_all(bus);
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#endif
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/* power down DSP */
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ret = hda_dsp_core_reset_power_down(sdev, chip->host_managed_cores_mask);
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ret = chip->power_down_dsp(sdev);
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if (ret < 0) {
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dev_err(sdev->dev,
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"error: failed to power down core during suspend\n");
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dev_err(sdev->dev, "failed to power down DSP during suspend\n");
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return ret;
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}
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@ -989,3 +986,11 @@ power_down:
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return ret;
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}
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int hda_dsp_disable_interrupts(struct snd_sof_dev *sdev)
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{
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hda_sdw_int_enable(sdev, false);
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hda_dsp_ipc_int_disable(sdev);
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return 0;
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}
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@ -1191,9 +1191,9 @@ int hda_dsp_remove(struct snd_sof_dev *sdev)
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snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, SOF_HDA_INTCTL,
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SOF_HDA_INT_CTRL_EN | SOF_HDA_INT_GLOBAL_EN, 0);
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/* disable cores */
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if (chip)
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hda_dsp_core_reset_power_down(sdev, chip->host_managed_cores_mask);
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/* no need to check for error as the DSP will be disabled anyway */
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if (chip && chip->power_down_dsp)
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chip->power_down_dsp(sdev);
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/* disable DSP */
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snd_sof_dsp_update_bits(sdev, HDA_DSP_PP_BAR, SOF_HDA_REG_PP_PPCTL,
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@ -1219,6 +1219,14 @@ int hda_dsp_remove(struct snd_sof_dev *sdev)
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return 0;
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}
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int hda_power_down_dsp(struct snd_sof_dev *sdev)
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{
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struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;
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const struct sof_intel_dsp_desc *chip = hda->desc;
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return hda_dsp_core_reset_power_down(sdev, chip->host_managed_cores_mask);
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}
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#if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
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static void hda_generic_machine_select(struct snd_sof_dev *sdev,
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struct snd_soc_acpi_mach **mach)
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@ -567,6 +567,7 @@ int hda_dsp_core_run(struct snd_sof_dev *sdev, unsigned int core_mask);
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int hda_dsp_enable_core(struct snd_sof_dev *sdev, unsigned int core_mask);
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int hda_dsp_core_reset_power_down(struct snd_sof_dev *sdev,
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unsigned int core_mask);
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int hda_power_down_dsp(struct snd_sof_dev *sdev);
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int hda_dsp_core_get(struct snd_sof_dev *sdev, int core);
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void hda_dsp_ipc_int_enable(struct snd_sof_dev *sdev);
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void hda_dsp_ipc_int_disable(struct snd_sof_dev *sdev);
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@ -586,6 +587,7 @@ void hda_dsp_dump(struct snd_sof_dev *sdev, u32 flags);
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void hda_ipc_dump(struct snd_sof_dev *sdev);
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void hda_ipc_irq_dump(struct snd_sof_dev *sdev);
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void hda_dsp_d0i3_work(struct work_struct *work);
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int hda_dsp_disable_interrupts(struct snd_sof_dev *sdev);
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/*
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* DSP PCM Operations.
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@ -175,6 +175,8 @@ const struct sof_intel_dsp_desc icl_chip_info = {
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.check_sdw_irq = hda_common_check_sdw_irq,
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.check_ipc_irq = hda_dsp_check_ipc_irq,
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.cl_init = cl_dsp_init,
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.power_down_dsp = hda_power_down_dsp,
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.disable_interrupts = hda_dsp_disable_interrupts,
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.hw_ip_version = SOF_INTEL_CAVS_2_0,
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};
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EXPORT_SYMBOL_NS(icl_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON);
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@ -144,7 +144,6 @@ static int mtl_enable_interrupts(struct snd_sof_dev *sdev)
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/* check if operation was successful */
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host_ipc = MTL_IRQ_INTEN_L_HOST_IPC_MASK | MTL_IRQ_INTEN_L_SOUNDWIRE_MASK;
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irqinten = snd_sof_dsp_read(sdev, HDA_DSP_BAR, hfintipptr);
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ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR, hfintipptr, irqinten,
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(irqinten & host_ipc) == host_ipc,
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HDA_DSP_REG_POLL_INTERVAL_US, HDA_DSP_RESET_TIMEOUT_US);
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@ -159,7 +158,6 @@ static int mtl_enable_interrupts(struct snd_sof_dev *sdev)
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/* check if operation was successful */
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host_ipc = MTL_DSP_REG_HfHIPCIE_IE_MASK;
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hipcie = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_DSP_REG_HfHIPCIE);
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ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR, MTL_DSP_REG_HfHIPCIE, hipcie,
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(hipcie & host_ipc) == host_ipc,
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HDA_DSP_REG_POLL_INTERVAL_US, HDA_DSP_RESET_TIMEOUT_US);
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@ -171,7 +169,6 @@ static int mtl_enable_interrupts(struct snd_sof_dev *sdev)
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snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, MTL_DSP_REG_HfSNDWIE,
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MTL_DSP_REG_HfSNDWIE_IE_MASK, MTL_DSP_REG_HfSNDWIE_IE_MASK);
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host_ipc = MTL_DSP_REG_HfSNDWIE_IE_MASK;
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hipcie = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_DSP_REG_HfSNDWIE);
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ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR, MTL_DSP_REG_HfSNDWIE, hipcie,
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(hipcie & host_ipc) == host_ipc,
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HDA_DSP_REG_POLL_INTERVAL_US, HDA_DSP_RESET_TIMEOUT_US);
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@ -199,7 +196,6 @@ static int mtl_disable_interrupts(struct snd_sof_dev *sdev)
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/* check if operation was successful */
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host_ipc = MTL_IRQ_INTEN_L_HOST_IPC_MASK | MTL_IRQ_INTEN_L_SOUNDWIRE_MASK;
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irqinten = snd_sof_dsp_read(sdev, HDA_DSP_BAR, hfintipptr);
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ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR, hfintipptr, irqinten,
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(irqinten & host_ipc) == 0,
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HDA_DSP_REG_POLL_INTERVAL_US, HDA_DSP_RESET_TIMEOUT_US);
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@ -213,7 +209,6 @@ static int mtl_disable_interrupts(struct snd_sof_dev *sdev)
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/* check if operation was successful */
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host_ipc = MTL_DSP_REG_HfHIPCIE_IE_MASK;
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hipcie = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_DSP_REG_HfHIPCIE);
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ret1 = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR, MTL_DSP_REG_HfHIPCIE, hipcie,
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(hipcie & host_ipc) == 0,
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HDA_DSP_REG_POLL_INTERVAL_US,
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@ -228,7 +223,6 @@ static int mtl_disable_interrupts(struct snd_sof_dev *sdev)
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snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, MTL_DSP_REG_HfSNDWIE,
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MTL_DSP_REG_HfSNDWIE_IE_MASK, 0);
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host_ipc = MTL_DSP_REG_HfSNDWIE_IE_MASK;
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hipcie = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_DSP_REG_HfSNDWIE);
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ret1 = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR, MTL_DSP_REG_HfSNDWIE, hipcie,
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(hipcie & host_ipc) == 0,
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HDA_DSP_REG_POLL_INTERVAL_US,
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@ -260,7 +254,6 @@ static int mtl_dsp_pre_fw_run(struct snd_sof_dev *sdev)
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/* poll with timeout to check if operation successful */
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cpa = MTL_HFDSSCS_CPA_MASK;
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dsphfdsscs = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_HFDSSCS);
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ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR, MTL_HFDSSCS, dsphfdsscs,
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(dsphfdsscs & cpa) == cpa, HDA_DSP_REG_POLL_INTERVAL_US,
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HDA_DSP_RESET_TIMEOUT_US);
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@ -277,7 +270,6 @@ static int mtl_dsp_pre_fw_run(struct snd_sof_dev *sdev)
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/* poll with timeout to check if operation successful */
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pgs = MTL_HFPWRSTS_DSPHPXPGS_MASK;
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dsphfpwrsts = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_HFPWRSTS);
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ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR, MTL_HFPWRSTS, dsphfpwrsts,
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(dsphfpwrsts & pgs) == pgs,
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HDA_DSP_REG_POLL_INTERVAL_US,
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@ -406,6 +398,33 @@ static int mtl_dsp_core_power_down(struct snd_sof_dev *sdev, int core)
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return ret;
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}
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static int mtl_power_down_dsp(struct snd_sof_dev *sdev)
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{
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u32 dsphfdsscs, cpa;
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int ret;
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/* first power down core */
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ret = mtl_dsp_core_power_down(sdev, SOF_DSP_PRIMARY_CORE);
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if (ret) {
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dev_err(sdev->dev, "mtl dsp power down error, %d\n", ret);
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return ret;
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}
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/* Set the DSP subsystem power down */
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snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, MTL_HFDSSCS,
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MTL_HFDSSCS_SPA_MASK, 0);
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/* Wait for unstable CPA read (1 then 0 then 1) just after setting SPA bit */
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usleep_range(1000, 1010);
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/* poll with timeout to check if operation successful */
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cpa = MTL_HFDSSCS_CPA_MASK;
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dsphfdsscs = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_HFDSSCS);
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return snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR, MTL_HFDSSCS, dsphfdsscs,
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(dsphfdsscs & cpa) == 0, HDA_DSP_REG_POLL_INTERVAL_US,
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HDA_DSP_RESET_TIMEOUT_US);
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}
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static int mtl_dsp_cl_init(struct snd_sof_dev *sdev, int stream_tag, bool imr_boot)
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{
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struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;
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@ -552,150 +571,6 @@ static int mtl_dsp_ipc_get_window_offset(struct snd_sof_dev *sdev, u32 id)
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return MTL_SRAM_WINDOW_OFFSET(id);
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}
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static int mtl_suspend(struct snd_sof_dev *sdev, bool runtime_suspend)
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{
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struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;
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const struct sof_intel_dsp_desc *chip = hda->desc;
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#if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
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struct hdac_bus *bus = sof_to_bus(sdev);
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#endif
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u32 dsphfdsscs;
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u32 cpa;
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int ret;
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int i;
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mtl_disable_ipc_interrupts(sdev);
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ret = mtl_disable_interrupts(sdev);
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if (ret)
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return ret;
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#if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
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hda_codec_jack_wake_enable(sdev, runtime_suspend);
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/* power down all hda link */
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snd_hdac_ext_bus_link_power_down_all(bus);
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#endif
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snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, MTL_HFPWRCTL,
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MTL_HFPWRCTL_WPDSPHPXPG, 0);
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/* Set the DSP subsystem power down */
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snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, MTL_HFDSSCS,
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MTL_HFDSSCS_SPA_MASK, 0);
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/* Wait for unstable CPA read (1 then 0 then 1) just after setting SPA bit */
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usleep_range(1000, 1010);
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/* poll with timeout to check if operation successful */
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cpa = MTL_HFDSSCS_CPA_MASK;
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dsphfdsscs = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_HFDSSCS);
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ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR, MTL_HFDSSCS, dsphfdsscs,
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(dsphfdsscs & cpa) == 0, HDA_DSP_REG_POLL_INTERVAL_US,
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HDA_DSP_RESET_TIMEOUT_US);
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if (ret < 0)
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dev_err(sdev->dev, "failed to disable DSP subsystem\n");
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/* reset ref counts for all cores */
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for (i = 0; i < chip->cores_num; i++)
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sdev->dsp_core_ref_count[i] = 0;
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/* TODO: need to reset controller? */
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/* display codec can be powered off after link reset */
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hda_codec_i915_display_power(sdev, false);
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return 0;
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}
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static int mtl_dsp_suspend(struct snd_sof_dev *sdev, u32 target_state)
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{
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const struct sof_dsp_power_state target_dsp_state = {
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.state = target_state,
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.substate = target_state == SOF_DSP_PM_D0 ?
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SOF_HDA_DSP_PM_D0I3 : 0,
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};
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int ret;
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ret = mtl_suspend(sdev, false);
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if (ret < 0)
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return ret;
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return snd_sof_dsp_set_power_state(sdev, &target_dsp_state);
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}
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static int mtl_dsp_runtime_suspend(struct snd_sof_dev *sdev)
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{
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const struct sof_dsp_power_state target_state = {
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.state = SOF_DSP_PM_D3,
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};
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int ret;
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ret = mtl_suspend(sdev, true);
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if (ret < 0)
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return ret;
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return snd_sof_dsp_set_power_state(sdev, &target_state);
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}
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static int mtl_resume(struct snd_sof_dev *sdev, bool runtime_resume)
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{
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#if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
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struct hdac_bus *bus = sof_to_bus(sdev);
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struct hdac_ext_link *hlink = NULL;
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#endif
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/* display codec must be powered before link reset */
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hda_codec_i915_display_power(sdev, true);
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#if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
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/* check jack status */
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if (runtime_resume) {
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hda_codec_jack_wake_enable(sdev, false);
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if (sdev->system_suspend_target == SOF_SUSPEND_NONE)
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hda_codec_jack_check(sdev);
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}
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/* turn off the links that were off before suspend */
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list_for_each_entry(hlink, &bus->hlink_list, list) {
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if (!hlink->ref_count)
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snd_hdac_ext_bus_link_power_down(hlink);
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}
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/* check dma status and clean up CORB/RIRB buffers */
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if (!bus->cmd_dma_state)
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snd_hdac_bus_stop_cmd_io(bus);
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#endif
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return 0;
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}
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static int mtl_dsp_resume(struct snd_sof_dev *sdev)
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{
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const struct sof_dsp_power_state target_state = {
|
||||
.state = SOF_DSP_PM_D0,
|
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.substate = SOF_HDA_DSP_PM_D0I0,
|
||||
};
|
||||
int ret;
|
||||
|
||||
ret = mtl_resume(sdev, false);
|
||||
if (ret < 0)
|
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return ret;
|
||||
|
||||
return snd_sof_dsp_set_power_state(sdev, &target_state);
|
||||
}
|
||||
|
||||
static int mtl_dsp_runtime_resume(struct snd_sof_dev *sdev)
|
||||
{
|
||||
const struct sof_dsp_power_state target_state = {
|
||||
.state = SOF_DSP_PM_D0,
|
||||
};
|
||||
int ret;
|
||||
|
||||
ret = mtl_resume(sdev, true);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
return snd_sof_dsp_set_power_state(sdev, &target_state);
|
||||
}
|
||||
|
||||
static void mtl_ipc_dump(struct snd_sof_dev *sdev)
|
||||
{
|
||||
u32 hipcctl;
|
||||
@ -714,6 +589,12 @@ static void mtl_ipc_dump(struct snd_sof_dev *sdev)
|
||||
hipcida, hipctdr, hipcctl);
|
||||
}
|
||||
|
||||
static int mtl_dsp_disable_interrupts(struct snd_sof_dev *sdev)
|
||||
{
|
||||
mtl_disable_ipc_interrupts(sdev);
|
||||
return mtl_disable_interrupts(sdev);
|
||||
}
|
||||
|
||||
/* Meteorlake ops */
|
||||
struct snd_sof_dsp_ops sof_mtl_ops;
|
||||
EXPORT_SYMBOL_NS(sof_mtl_ops, SND_SOC_SOF_INTEL_HDA_COMMON);
|
||||
@ -752,12 +633,6 @@ int sof_mtl_ops_init(struct snd_sof_dev *sdev)
|
||||
/* dsp core get/put */
|
||||
/* TODO: add core_get and core_put */
|
||||
|
||||
/* PM */
|
||||
sof_mtl_ops.suspend = mtl_dsp_suspend;
|
||||
sof_mtl_ops.resume = mtl_dsp_resume;
|
||||
sof_mtl_ops.runtime_suspend = mtl_dsp_runtime_suspend;
|
||||
sof_mtl_ops.runtime_resume = mtl_dsp_runtime_resume;
|
||||
|
||||
sdev->private = devm_kzalloc(sdev->dev, sizeof(struct sof_ipc4_fw_data), GFP_KERNEL);
|
||||
if (!sdev->private)
|
||||
return -ENOMEM;
|
||||
@ -792,6 +667,8 @@ const struct sof_intel_dsp_desc mtl_chip_info = {
|
||||
.check_sdw_irq = mtl_dsp_check_sdw_irq,
|
||||
.check_ipc_irq = mtl_dsp_check_ipc_irq,
|
||||
.cl_init = mtl_dsp_cl_init,
|
||||
.power_down_dsp = mtl_power_down_dsp,
|
||||
.disable_interrupts = mtl_dsp_disable_interrupts,
|
||||
.hw_ip_version = SOF_INTEL_ACE_1_0,
|
||||
};
|
||||
EXPORT_SYMBOL_NS(mtl_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON);
|
||||
|
@ -186,6 +186,8 @@ struct sof_intel_dsp_desc {
|
||||
enum sof_intel_hw_ip_version hw_ip_version;
|
||||
bool (*check_sdw_irq)(struct snd_sof_dev *sdev);
|
||||
bool (*check_ipc_irq)(struct snd_sof_dev *sdev);
|
||||
int (*power_down_dsp)(struct snd_sof_dev *sdev);
|
||||
int (*disable_interrupts)(struct snd_sof_dev *sdev);
|
||||
int (*cl_init)(struct snd_sof_dev *sdev, int stream_tag, bool imr_boot);
|
||||
};
|
||||
|
||||
|
@ -111,6 +111,8 @@ const struct sof_intel_dsp_desc skl_chip_info = {
|
||||
.rom_status_reg = HDA_DSP_SRAM_REG_ROM_STATUS_SKL,
|
||||
.rom_init_timeout = 300,
|
||||
.check_ipc_irq = hda_dsp_check_ipc_irq,
|
||||
.power_down_dsp = hda_power_down_dsp,
|
||||
.disable_interrupts = hda_dsp_disable_interrupts,
|
||||
.hw_ip_version = SOF_INTEL_CAVS_1_5,
|
||||
};
|
||||
EXPORT_SYMBOL_NS(skl_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON);
|
||||
|
@ -130,6 +130,8 @@ const struct sof_intel_dsp_desc tgl_chip_info = {
|
||||
.check_sdw_irq = hda_common_check_sdw_irq,
|
||||
.check_ipc_irq = hda_dsp_check_ipc_irq,
|
||||
.cl_init = cl_dsp_init,
|
||||
.power_down_dsp = hda_power_down_dsp,
|
||||
.disable_interrupts = hda_dsp_disable_interrupts,
|
||||
.hw_ip_version = SOF_INTEL_CAVS_2_5,
|
||||
};
|
||||
EXPORT_SYMBOL_NS(tgl_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON);
|
||||
@ -153,6 +155,8 @@ const struct sof_intel_dsp_desc tglh_chip_info = {
|
||||
.check_sdw_irq = hda_common_check_sdw_irq,
|
||||
.check_ipc_irq = hda_dsp_check_ipc_irq,
|
||||
.cl_init = cl_dsp_init,
|
||||
.power_down_dsp = hda_power_down_dsp,
|
||||
.disable_interrupts = hda_dsp_disable_interrupts,
|
||||
.hw_ip_version = SOF_INTEL_CAVS_2_5,
|
||||
};
|
||||
EXPORT_SYMBOL_NS(tglh_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON);
|
||||
@ -176,6 +180,8 @@ const struct sof_intel_dsp_desc ehl_chip_info = {
|
||||
.check_sdw_irq = hda_common_check_sdw_irq,
|
||||
.check_ipc_irq = hda_dsp_check_ipc_irq,
|
||||
.cl_init = cl_dsp_init,
|
||||
.power_down_dsp = hda_power_down_dsp,
|
||||
.disable_interrupts = hda_dsp_disable_interrupts,
|
||||
.hw_ip_version = SOF_INTEL_CAVS_2_5,
|
||||
};
|
||||
EXPORT_SYMBOL_NS(ehl_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON);
|
||||
@ -199,6 +205,8 @@ const struct sof_intel_dsp_desc adls_chip_info = {
|
||||
.check_sdw_irq = hda_common_check_sdw_irq,
|
||||
.check_ipc_irq = hda_dsp_check_ipc_irq,
|
||||
.cl_init = cl_dsp_init,
|
||||
.power_down_dsp = hda_power_down_dsp,
|
||||
.disable_interrupts = hda_dsp_disable_interrupts,
|
||||
.hw_ip_version = SOF_INTEL_CAVS_2_5,
|
||||
};
|
||||
EXPORT_SYMBOL_NS(adls_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON);
|
||||
|
Loading…
Reference in New Issue
Block a user