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sh: pci: Rewrite SH7751 PCI support to follow SH7780.

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This follows the similar sort of scheme that the refactored SH7780 code
uses, using a 64MB CS3 mapping to handle the window0 case, and simply
discarding window1. This vastly simplifies the code, and allows most of
the board-specific setup to go die.

Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This commit is contained in:
Paul Mundt 2009-04-20 21:11:07 +09:00
parent a5b0804712
commit 757e3c16f8
10 changed files with 81 additions and 310 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
arch/sh/drivers/pci/Kconfig
View File

@ -23,7 +23,8 @@ config PCI_NEW
bool
depends on PCI
default y if CPU_SUBTYPE_SH7763 || CPU_SUBTYPE_SH7780 || \
CPU_SUBTYPE_SH7785 || CPU_SH5
CPU_SUBTYPE_SH7785 || CPU_SH5 || \
CPU_SUBTYPE_SH7751 || CPU_SUBTYPE_SH7751R
# This is also board-specific
config PCI_AUTO

2
arch/sh/drivers/pci/Makefile
View File

@ -16,7 +16,7 @@ obj-$(CONFIG_SH_DREAMCAST) += ops-dreamcast.o fixups-dreamcast.o \
pci-dreamcast.o
obj-$(CONFIG_SH_SECUREEDGE5410) += ops-snapgear.o
obj-$(CONFIG_SH_RTS7751R2D) += ops-rts7751r2d.o fixups-rts7751r2d.o
obj-$(CONFIG_SH_SH03) += ops-sh03.o fixups-sh03.o
obj-$(CONFIG_SH_SH03) += fixups-sh03.o
obj-$(CONFIG_SH_HIGHLANDER) += fixups-r7780rp.o
obj-$(CONFIG_SH_SH7785LCR) += fixups-r7780rp.o
obj-$(CONFIG_SH_SDK7780) += fixups-sdk7780.o

31
arch/sh/drivers/pci/ops-landisk.c
View File

@ -15,37 +15,6 @@
#include <linux/pci.h>
#include "pci-sh4.h"
static struct resource sh7751_io_resource = {
.name = "SH7751 IO",
.start = SH7751_PCI_IO_BASE,
.end = SH7751_PCI_IO_BASE + SH7751_PCI_IO_SIZE - 1,
.flags = IORESOURCE_IO
};
static struct resource sh7751_mem_resource = {
.name = "SH7751 mem",
.start = SH7751_PCI_MEMORY_BASE,
.end = SH7751_PCI_MEMORY_BASE + SH7751_PCI_MEM_SIZE - 1,
.flags = IORESOURCE_MEM
};
struct pci_channel board_pci_channels[] = {
{ sh7751_pci_init, &sh4_pci_ops, &sh7751_io_resource, &sh7751_mem_resource, 0, 0x3ff},
{NULL, NULL, NULL, 0, 0},
};
static struct sh4_pci_address_map sh7751_pci_map = {
.window0 = {
.base = SH7751_CS3_BASE_ADDR,
.size = (64 << 20), /* 64MB */
},
};
int __init pcibios_init_platform(void)
{
return sh7751_pcic_init(&board_pci_channels[0], &sh7751_pci_map);
}
int pcibios_map_platform_irq(struct pci_dev *pdev, u8 slot, u8 pin)
{
/*

33
arch/sh/drivers/pci/ops-lboxre2.c
View File

@ -21,36 +21,3 @@ int __init pcibios_map_platform_irq(struct pci_dev *pdev, u8 slot, u8 pin)
{
return lboxre2_irq_tab[slot];
}
static struct resource sh7751_io_resource = {
.name = "SH7751_IO",
.start = SH7751_PCI_IO_BASE ,
.end = SH7751_PCI_IO_BASE + SH7751_PCI_IO_SIZE - 1,
.flags = IORESOURCE_IO
};
static struct resource sh7751_mem_resource = {
.name = "SH7751_mem",
.start = SH7751_PCI_MEMORY_BASE,
.end = SH7751_PCI_MEMORY_BASE + SH7751_PCI_MEM_SIZE - 1,
.flags = IORESOURCE_MEM
};
extern struct pci_ops sh7751_pci_ops;
struct pci_channel board_pci_channels[] = {
{ sh7751_pci_init, &sh4_pci_ops, &sh7751_io_resource, &sh7751_mem_resource, 0, 0xff },
{ NULL, NULL, NULL, 0, 0 },
};
static struct sh4_pci_address_map sh7751_pci_map = {
.window0 = {
.base = SH7751_CS3_BASE_ADDR,
.size = 0x04000000,
},
};
int __init pcibios_init_platform(void)
{
return sh7751_pcic_init(&board_pci_channels[0], &sh7751_pci_map);
}

34
arch/sh/drivers/pci/ops-rts7751r2d.c
View File

@ -29,37 +29,3 @@ int __init pcibios_map_platform_irq(struct pci_dev *pdev, u8 slot, u8 pin)
{
return rts7751r2d_irq_tab[slot];
}
static struct resource sh7751_io_resource = {
.name = "SH7751_IO",
.start = 0x4000,
.end = SH7751_PCI_IO_SIZE - 1,
.flags = IORESOURCE_IO
};
static struct resource sh7751_mem_resource = {
.name = "SH7751_mem",
.start = SH7751_PCI_MEMORY_BASE,
.end = SH7751_PCI_MEMORY_BASE + SH7751_PCI_MEM_SIZE - 1,
.flags = IORESOURCE_MEM
};
extern struct pci_ops sh7751_pci_ops;
struct pci_channel board_pci_channels[] = {
{ sh7751_pci_init, &sh4_pci_ops, &sh7751_io_resource, &sh7751_mem_resource, 0, 0xff },
{ NULL, NULL, NULL, 0, 0 },
};
static struct sh4_pci_address_map sh7751_pci_map = {
.window0 = {
.base = SH7751_CS3_BASE_ADDR,
.size = 0x04000000,
},
};
int __init pcibios_init_platform(void)
{
return sh7751_pcic_init(&board_pci_channels[0], &sh7751_pci_map);
}

45
arch/sh/drivers/pci/ops-sh03.c
View File

@ -1,45 +0,0 @@
/*
* linux/arch/sh/drivers/pci/ops-sh03.c
*
* PCI initialization for the Interface CTP/PCI-SH03 board
*/
#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/pci.h>
#include <asm/io.h>
#include "pci-sh7751.h"
/*
* Description: This function sets up and initializes the pcic, sets
* up the BARS, maps the DRAM into the address space etc, etc.
*/
int __init pcibios_init_platform(void)
{
__set_io_port_base(SH7751_PCI_IO_BASE);
return 1;
}
static struct resource sh7751_io_resource = {
.name = "SH03 IO",
.start = SH7751_PCI_IO_BASE,
.end = SH7751_PCI_IO_BASE + SH7751_PCI_IO_SIZE - 1,
.flags = IORESOURCE_IO
};
static struct resource sh7751_mem_resource = {
.name = "SH03 mem",
.start = SH7751_PCI_MEMORY_BASE,
.end = SH7751_PCI_MEMORY_BASE + SH7751_PCI_MEM_SIZE - 1,
.flags = IORESOURCE_MEM
};
extern struct pci_ops sh4_pci_ops;
struct pci_channel board_pci_channels[] = {
{ sh7751_pci_init, &sh4_pci_ops, &sh7751_io_resource, &sh7751_mem_resource, 0, 0xff },
{ NULL, NULL, NULL, 0, 0 },
};

49
arch/sh/drivers/pci/ops-snapgear.c
View File

@ -18,55 +18,6 @@
#include <linux/pci.h>
#include "pci-sh4.h"
#define SNAPGEAR_PCI_IO 0x4000
#define SNAPGEAR_PCI_MEM 0xfd000000
/* PCI: default LOCAL memory window sizes (seen from PCI bus) */
#define SNAPGEAR_LSR0_SIZE (64*(1<<20)) //64MB
#define SNAPGEAR_LSR1_SIZE (64*(1<<20)) //64MB
static struct resource sh7751_io_resource = {
.name = "SH7751 IO",
.start = SNAPGEAR_PCI_IO,
.end = SNAPGEAR_PCI_IO + (64*1024) - 1, /* 64KiB I/O */
.flags = IORESOURCE_IO,
};
static struct resource sh7751_mem_resource = {
.name = "SH7751 mem",
.start = SNAPGEAR_PCI_MEM,
.end = SNAPGEAR_PCI_MEM + (64*1024*1024) - 1, /* 64MiB mem */
.flags = IORESOURCE_MEM,
};
struct pci_channel board_pci_channels[] = {
{ sh7751_pci_init, &sh4_pci_ops, &sh7751_io_resource, &sh7751_mem_resource, 0, 0xff },
{ 0, }
};
static struct sh4_pci_address_map sh7751_pci_map = {
.window0 = {
.base = SH7751_CS2_BASE_ADDR,
.size = SNAPGEAR_LSR0_SIZE,
},
.window1 = {
.base = SH7751_CS2_BASE_ADDR,
.size = SNAPGEAR_LSR1_SIZE,
},
};
/*
* Initialize the SnapGear PCI interface
* Setup hardware to be Central Funtion
* Copy the BSR regs to the PCI interface
* Setup PCI windows into local RAM
*/
int __init pcibios_init_platform(void)
{
return sh7751_pcic_init(&board_pci_channels[0], &sh7751_pci_map);
}
int __init pcibios_map_platform_irq(struct pci_dev *pdev, u8 slot, u8 pin)
{
int irq = -1;

36
arch/sh/drivers/pci/ops-titan.c
View File

@ -36,39 +36,3 @@ int __init pcibios_map_platform_irq(struct pci_dev *pdev, u8 slot, u8 pin)
return irq;
}
static struct resource sh7751_io_resource = {
.name = "SH7751_IO",
.start = SH7751_PCI_IO_BASE,
.end = SH7751_PCI_IO_BASE + SH7751_PCI_IO_SIZE - 1,
.flags = IORESOURCE_IO
};
static struct resource sh7751_mem_resource = {
.name = "SH7751_mem",
.start = SH7751_PCI_MEMORY_BASE,
.end = SH7751_PCI_MEMORY_BASE + SH7751_PCI_MEM_SIZE - 1,
.flags = IORESOURCE_MEM
};
struct pci_channel board_pci_channels[] = {
{ sh7751_pci_init, &sh4_pci_ops, &sh7751_io_resource, &sh7751_mem_resource, 0, 0xff },
{ NULL, NULL, NULL, 0, 0 },
};
static struct sh4_pci_address_map sh7751_pci_map = {
.window0 = {
.base = SH7751_CS2_BASE_ADDR,
.size = SH7751_MEM_REGION_SIZE*2, /* cs2 and cs3 */
},
.window1 = {
.base = SH7751_CS2_BASE_ADDR,
.size = SH7751_MEM_REGION_SIZE*2,
},
};
int __init pcibios_init_platform(void)
{
return sh7751_pcic_init(&board_pci_channels[0], &sh7751_pci_map);
}

145
arch/sh/drivers/pci/pci-sh7751.c
View File

@ -1,43 +1,86 @@
/*
* Low-Level PCI Support for the SH7751
* Low-Level PCI Support for the SH7751
*
* Dustin McIntire (dustin@sensoria.com)
* Derived from arch/i386/kernel/pci-*.c which bore the message:
* (c) 1999--2000 Martin Mares <mj@ucw.cz>
* Copyright (C) 2003 - 2009 Paul Mundt
* Copyright (C) 2001 Dustin McIntire
*
* Ported to the new API by Paul Mundt <lethal@linux-sh.org>
* With cleanup by Paul van Gool <pvangool@mimotech.com>
*
* May be copied or modified under the terms of the GNU General Public
* License. See linux/COPYING for more information.
* With cleanup by Paul van Gool <pvangool@mimotech.com>, 2003.
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*/
#undef DEBUG
#include <linux/init.h>
#include <linux/pci.h>
#include <linux/types.h>
#include <linux/errno.h>
#include <linux/delay.h>
#include <linux/io.h>
#include "pci-sh4.h"
#include <asm/addrspace.h>
#include <asm/io.h>
/*
* Initialization. Try all known PCI access methods. Note that we support
* using both PCI BIOS and direct access: in such cases, we use I/O ports
* to access config space.
*
* Note that the platform specific initialization (BSC registers, and memory
* space mapping) will be called via the platform defined function
* pcibios_init_platform().
*/
int __init sh7751_pci_init(struct pci_channel *chan)
static int __init __area_sdram_check(struct pci_channel *chan,
unsigned int area)
{
unsigned long word;
word = __raw_readl(SH7751_BCR1);
/* check BCR for SDRAM in area */
if (((word >> area) & 1) == 0) {
printk("PCI: Area %d is not configured for SDRAM. BCR1=0x%lx\n",
area, word);
return 0;
}
pci_write_reg(chan, word, SH4_PCIBCR1);
word = __raw_readw(SH7751_BCR2);
/* check BCR2 for 32bit SDRAM interface*/
if (((word >> (area << 1)) & 0x3) != 0x3) {
printk("PCI: Area %d is not 32 bit SDRAM. BCR2=0x%lx\n",
area, word);
return 0;
}
pci_write_reg(chan, word, SH4_PCIBCR2);
return 1;
}
static struct resource sh7751_io_resource = {
.name = "SH7751_IO",
.start = SH7751_PCI_IO_BASE,
.end = SH7751_PCI_IO_BASE + SH7751_PCI_IO_SIZE - 1,
.flags = IORESOURCE_IO
};
static struct resource sh7751_mem_resource = {
.name = "SH7785_mem",
.start = SH7751_PCI_MEMORY_BASE,
.end = SH7751_PCI_MEMORY_BASE + SH7751_PCI_MEM_SIZE - 1,
.flags = IORESOURCE_MEM
};
static struct pci_channel sh7751_pci_controller = {
.pci_ops = &sh4_pci_ops,
.mem_resource = &sh7751_mem_resource,
.mem_offset = 0x00000000,
.io_resource = &sh7751_io_resource,
.io_offset = 0x00000000,
};
static struct sh4_pci_address_map sh7751_pci_map = {
.window0 = {
.base = SH7751_CS3_BASE_ADDR,
.size = 0x04000000,
},
};
static int __init sh7751_pci_init(void)
{
struct pci_channel *chan = &sh7751_pci_controller;
unsigned int id;
u32 word, reg;
int ret;
pr_debug("PCI: Starting intialization.\n");
printk(KERN_NOTICE "PCI: Starting intialization.\n");
chan->reg_base = 0xfe200000;
@ -52,41 +95,6 @@ int __init sh7751_pci_init(struct pci_channel *chan)
if ((ret = sh4_pci_check_direct(chan)) != 0)
return ret;
return pcibios_init_platform();
}
static int __init __area_sdram_check(struct pci_channel *chan,
unsigned int area)
{
u32 word;
word = ctrl_inl(SH7751_BCR1);
/* check BCR for SDRAM in area */
if (((word >> area) & 1) == 0) {
printk("PCI: Area %d is not configured for SDRAM. BCR1=0x%x\n",
area, word);
return 0;
}
pci_write_reg(chan, word, SH4_PCIBCR1);
word = (u16)ctrl_inw(SH7751_BCR2);
/* check BCR2 for 32bit SDRAM interface*/
if (((word >> (area << 1)) & 0x3) != 0x3) {
printk("PCI: Area %d is not 32 bit SDRAM. BCR2=0x%x\n",
area, word);
return 0;
}
pci_write_reg(chan, word, SH4_PCIBCR2);
return 1;
}
int __init sh7751_pcic_init(struct pci_channel *chan,
struct sh4_pci_address_map *map)
{
u32 reg;
u32 word;
/* Set the BCR's to enable PCI access */
reg = ctrl_inl(SH7751_BCR1);
reg |= 0x80000;
@ -112,21 +120,13 @@ int __init sh7751_pcic_init(struct pci_channel *chan,
/* Set IO and Mem windows to local address
* Make PCI and local address the same for easy 1 to 1 mapping
* Window0 = map->window0.size @ non-cached area base = SDRAM
* Window1 = map->window1.size @ cached area base = SDRAM
*/
word = map->window0.size - 1;
word = sh7751_pci_map.window0.size - 1;
pci_write_reg(chan, word, SH4_PCILSR0);
word = map->window1.size - 1;
pci_write_reg(chan, word, SH4_PCILSR1);
/* Set the values on window 0 PCI config registers */
word = P2SEGADDR(map->window0.base);
word = P2SEGADDR(sh7751_pci_map.window0.base);
pci_write_reg(chan, word, SH4_PCILAR0);
pci_write_reg(chan, word, SH7751_PCICONF5);
/* Set the values on window 1 PCI config registers */
word = PHYSADDR(map->window1.base);
pci_write_reg(chan, word, SH4_PCILAR1);
pci_write_reg(chan, word, SH7751_PCICONF6);
/* Set the local 16MB PCI memory space window to
* the lowest PCI mapped address
@ -144,7 +144,7 @@ int __init sh7751_pcic_init(struct pci_channel *chan,
/* Set PCI WCRx, BCRx's, copy from BSC locations */
/* check BCR for SDRAM in specified area */
switch (map->window0.base) {
switch (sh7751_pci_map.window0.base) {
case SH7751_CS0_BASE_ADDR: word = __area_sdram_check(chan, 0); break;
case SH7751_CS1_BASE_ADDR: word = __area_sdram_check(chan, 1); break;
case SH7751_CS2_BASE_ADDR: word = __area_sdram_check(chan, 2); break;
@ -179,5 +179,10 @@ int __init sh7751_pcic_init(struct pci_channel *chan,
word = SH4_PCICR_PREFIX | SH4_PCICR_CFIN | SH4_PCICR_ARBM;
pci_write_reg(chan, word, SH4_PCICR);
__set_io_port_base(SH7751_PCI_IO_BASE);
register_pci_controller(chan);
return 0;
}
arch_initcall(sh7751_pci_init);

13
arch/sh/drivers/pci/pci-sh7751.h
View File

@ -57,7 +57,7 @@
#define SH7751_PCICONF2_SCC 0x00FF0000 /* Sub-Class Code */
#define SH7751_PCICONF2_RLPI 0x0000FF00 /* Programming Interface */
#define SH7751_PCICONF2_REV 0x000000FF /* Revision ID */
#define SH7751_PCICONF3 0xC /* PCI Config Reg 3 */
#define SH7751_PCICONF3 0xC /* PCI Config Reg 3 */
#define SH7751_PCICONF3_BIST7 0x80000000 /* Bist Supported */
#define SH7751_PCICONF3_BIST6 0x40000000 /* Bist Executing */
#define SH7751_PCICONF3_BIST3_0 0x0F000000 /* Bist Passed */
@ -72,12 +72,12 @@
#define SH7751_PCICONF5_BASE 0xFFFFFFF0 /* Mem Space Base Addr */
#define SH7751_PCICONF5_LAP 0x00000008 /* Prefetch Enabled */
#define SH7751_PCICONF5_LAT 0x00000006 /* Local Memory type */
#define SH7751_PCICONF5_ASI 0x00000001 /* Address Space Type */
#define SH7751_PCICONF5_ASI 0x00000001 /* Address Space Type */
#define SH7751_PCICONF6 0x18 /* PCI Config Reg 6 */
#define SH7751_PCICONF6_BASE 0xFFFFFFF0 /* Mem Space Base Addr */
#define SH7751_PCICONF6_LAP 0x00000008 /* Prefetch Enabled */
#define SH7751_PCICONF6_LAT 0x00000006 /* Local Memory type */
#define SH7751_PCICONF6_ASI 0x00000001 /* Address Space Type */
#define SH7751_PCICONF6_ASI 0x00000001 /* Address Space Type */
/* PCICONF7 - PCICONF10 are undefined */
#define SH7751_PCICONF11 0x2C /* PCI Config Reg 11 */
#define SH7751_PCICONF11_SSID 0xFFFF0000 /* Subsystem ID */
@ -126,11 +126,4 @@
#define SH7751_CS5_BASE_ADDR (SH7751_CS4_BASE_ADDR + SH7751_MEM_REGION_SIZE)
#define SH7751_CS6_BASE_ADDR (SH7751_CS5_BASE_ADDR + SH7751_MEM_REGION_SIZE)
struct sh4_pci_address_map;
/* arch/sh/drivers/pci/pci-sh7751.c */
int sh7751_pci_init(struct pci_channel *chan);
int sh7751_pcic_init(struct pci_channel *chan,
struct sh4_pci_address_map *map);
#endif /* _PCI_SH7751_H_ */