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sh: Fix up SH7786 PCI resource definitions.
This adds in some of the missing memory resources for channels 1/2 and gets the code building again for the recent changes. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This commit is contained in:
Paul Mundt
parent
13fd7aeb9a
commit
7561f2dd39
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@ -1,7 +1,7 @@
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/*
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* Low-Level PCI Express Support for the SH7786
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*
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* Copyright (C) 2009 Paul Mundt
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* Copyright (C) 2009 - 2010 Paul Mundt
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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@ -30,60 +30,84 @@ static struct sh7786_pcie_hwops {
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int (*port_init_hw)(struct sh7786_pcie_port *port);
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} *sh7786_pcie_hwops;
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static struct resource sh7786_pci_32bit_mem_resources[] = {
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static struct resource sh7786_pci0_resources[] = {
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{
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.name = "pci0_mem",
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.start = SH4A_PCIMEM_BASEA,
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.end = SH4A_PCIMEM_BASEA + SZ_64M - 1,
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.name = "PCIe0 IO",
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.start = 0xfd000000,
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.end = 0xfd000000 + SZ_8M - 1,
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.flags = IORESOURCE_IO,
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}, {
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.name = "PCIe0 MEM 0",
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.start = 0xc0000000,
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.end = 0xc0000000 + SZ_512M - 1,
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.flags = IORESOURCE_MEM | IORESOURCE_MEM_32BIT,
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}, {
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.name = "PCIe0 MEM 1",
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.start = 0x10000000,
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.end = 0x10000000 + SZ_64M - 1,
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.flags = IORESOURCE_MEM,
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}, {
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.name = "pci1_mem",
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.start = SH4A_PCIMEM_BASEA1,
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.end = SH4A_PCIMEM_BASEA1 + SZ_64M - 1,
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.flags = IORESOURCE_MEM,
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}, {
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.name = "pci2_mem",
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.start = SH4A_PCIMEM_BASEA2,
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.end = SH4A_PCIMEM_BASEA2 + SZ_64M - 1,
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.flags = IORESOURCE_MEM,
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.name = "PCIe0 MEM 2",
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.start = 0xfe100000,
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.end = 0xfe100000 + SZ_1M - 1,
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},
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};
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static struct resource sh7786_pci_29bit_mem_resource = {
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.start = SH4A_PCIMEM_BASE,
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.end = SH4A_PCIMEM_BASE + SZ_64M - 1,
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.flags = IORESOURCE_MEM,
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static struct resource sh7786_pci1_resources[] = {
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{
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.name = "PCIe1 IO",
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.start = 0xfd800000,
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.end = 0xfd800000 + SZ_8M - 1,
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.flags = IORESOURCE_IO,
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}, {
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.name = "PCIe1 MEM 0",
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.start = 0xa0000000,
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.end = 0xa0000000 + SZ_512M - 1,
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.flags = IORESOURCE_MEM | IORESOURCE_MEM_32BIT,
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}, {
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.name = "PCIe1 MEM 1",
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.start = 0x30000000,
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.end = 0x30000000 + SZ_256M - 1,
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.flags = IORESOURCE_MEM | IORESOURCE_MEM_32BIT,
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}, {
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.name = "PCIe1 MEM 2",
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.start = 0xfe300000,
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.end = 0xfe300000 + SZ_1M - 1,
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},
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};
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static struct resource sh7786_pci_io_resources[] = {
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static struct resource sh7786_pci2_resources[] = {
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{
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.name = "pci0_io",
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.start = SH4A_PCIIO_BASE,
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.end = SH4A_PCIIO_BASE + SZ_8M - 1,
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.flags = IORESOURCE_IO,
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.name = "PCIe2 IO",
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.start = 0xfc800000,
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.end = 0xfc800000 + SZ_4M - 1,
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}, {
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.name = "pci1_io",
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.start = SH4A_PCIIO_BASE1,
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.end = SH4A_PCIIO_BASE1 + SZ_8M - 1,
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.flags = IORESOURCE_IO,
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.name = "PCIe2 MEM 0",
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.start = 0x80000000,
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.end = 0x80000000 + SZ_512M - 1,
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.flags = IORESOURCE_MEM | IORESOURCE_MEM_32BIT,
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}, {
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.name = "pci2_io",
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.start = SH4A_PCIIO_BASE2,
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.end = SH4A_PCIIO_BASE2 + SZ_4M - 1,
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.flags = IORESOURCE_IO,
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.name = "PCIe2 MEM 1",
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.start = 0x20000000,
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.end = 0x20000000 + SZ_256M - 1,
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.flags = IORESOURCE_MEM | IORESOURCE_MEM_32BIT,
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}, {
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.name = "PCIe2 MEM 2",
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.start = 0xfcd00000,
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.end = 0xfcd00000 + SZ_1M - 1,
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},
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};
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extern struct pci_ops sh7786_pci_ops;
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#define DEFINE_CONTROLLER(start, idx) \
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{ \
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.pci_ops = &sh7786_pci_ops, \
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.reg_base = start, \
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/* mem_resource filled in at probe time */ \
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.mem_offset = 0, \
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.io_resource = &sh7786_pci_io_resources[idx], \
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.io_offset = 0, \
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#define DEFINE_CONTROLLER(start, idx) \
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{ \
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.pci_ops = &sh7786_pci_ops, \
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.resources = sh7786_pci##idx##_resources, \
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.nr_resources = ARRAY_SIZE(sh7786_pci##idx##_resources), \
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.reg_base = start, \
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.mem_offset = 0, \
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.io_offset = 0, \
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}
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static struct pci_channel sh7786_pci_channels[] = {
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@ -330,17 +354,7 @@ static int __init sh7786_pcie_init(void)
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port->index = i;
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port->hose = sh7786_pci_channels + i;
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port->hose->io_map_base = port->hose->io_resource->start;
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/*
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* Check if we are booting in 29 or 32-bit mode
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*
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* 32-bit mode provides each controller with its own
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* memory window, while 29-bit mode uses a shared one.
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*/
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port->hose->mem_resource = test_mode_pin(MODE_PIN10) ?
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&sh7786_pci_32bit_mem_resources[i] :
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&sh7786_pci_29bit_mem_resource;
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port->hose->io_map_base = port->hose->resources[0].start;
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ret |= sh7786_pcie_hwops->port_init_hw(port);
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}
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@ -30,47 +30,9 @@
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* for other(Max Payload Size=4096B,PCIIO_SIZE=8M)
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*/
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/* PCI0-0: PCI I/O space */
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#define SH4A_PCIIO_BASE 0xFD000000 /* PCI I/O for controller 0 */
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#define SH4A_PCIIO_BASE1 0xFD800000 /* PCI I/O for controller 1 (Rev1.14)*/
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#define SH4A_PCIIO_BASE2 0xFC800000 /* PCI I/O for controller 2 (Rev1.171)*/
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#define SH4A_PCIIO_SIZE64 0x00010000 /* PLX allows only 64K */
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#define SH4A_PCIIO_SIZE 0x00800000 /* 8M */
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#define SH4A_PCIIO_SIZE2 0x00400000 /* 4M (Rev1.171)*/
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/* PCI0-1: PCI memory space 29-bit address */
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#define SH4A_PCIMEM_BASE 0x10000000
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#define SH4A_PCIMEM_SIZE 0x04000000 /* 64M */
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/* PCI0-2: PCI memory space 32-bit address */
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#define SH4A_PCIMEM_BASEA 0xC0000000 /* for controller 0 */
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#define SH4A_PCIMEM_BASEA1 0xA0000000 /* for controller 1 (Rev1.14)*/
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#define SH4A_PCIMEM_BASEA2 0x80000000 /* for controller 2 (Rev1.171)*/
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#define SH4A_PCIMEM_SIZEA 0x20000000 /* 512M */
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/* PCI0: PCI memory target transfer 32-bit address translation value(Rev1.11T)*/
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#define SH4A_PCIBMSTR_TRANSLATION 0x20000000
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#define SH4A_PCI_DEVICE_ID 0x0002
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#define SH4A_PCI_VENDOR_ID 0x1912
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// PCI compatible 000-03f
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#define PCI_CMD 0x004
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#define PCI_RID 0x008
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#define PCI_IBAR 0x010
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#define PCI_MBAR0 0x014
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#define PCI_MBAR1 0x018
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/* PCI power management/MSI/capablity 040-0ff */
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/* PCIE extended 100-fff */
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/* SH7786 device identification */ // Rev1.171
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#define SH4A_PVR (0xFF000030)
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#define SH4A_PVR_SHX3 (0x10400000)
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#define SH4A_PRR (0xFF000044)
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#define SH4A_PRR_SH7786 (0x00000400) // Rev1.171
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/* SPVCR0 */
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#define SH4A_PCIEVCR0 (0x000000) /* R - 0x0000 0000 32 */
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#define BITS_TOP_MB (24)
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