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sfc: Fix some incorrect or redundant comments
In particular, the comment about EVQ_RPTR_REG is based on inconsistent preliminary hardware documentation, though the following code was fixed long before release. Signed-off-by: Ben Hutchings <bhutchings@solarflare.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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@ -196,7 +196,7 @@ int efx_ethtool_get_settings(struct net_device *net_dev,
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efx->phy_op->get_settings(efx, ecmd);
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mutex_unlock(&efx->mac_lock);
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/* Falcon GMAC does not support 1000Mbps HD */
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/* GMAC does not support 1000Mbps HD */
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ecmd->supported &= ~SUPPORTED_1000baseT_Half;
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/* Both MACs support pause frames (bidirectional and respond-only) */
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ecmd->supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause;
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@ -216,7 +216,7 @@ int efx_ethtool_set_settings(struct net_device *net_dev,
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struct efx_nic *efx = netdev_priv(net_dev);
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int rc;
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/* Falcon GMAC does not support 1000Mbps HD */
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/* GMAC does not support 1000Mbps HD */
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if (ecmd->speed == SPEED_1000 && ecmd->duplex != DUPLEX_FULL) {
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EFX_LOG(efx, "rejecting unsupported 1000Mbps HD"
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" setting\n");
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@ -1730,7 +1730,7 @@ static int falcon_set_wol(struct efx_nic *efx, u32 type)
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/**************************************************************************
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*
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* Revision-dependent attributes used by efx.c
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* Revision-dependent attributes used by efx.c and nic.c
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*
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**************************************************************************
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*/
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@ -101,9 +101,6 @@ do {if (net_ratelimit()) EFX_LOG(efx, fmt, ##args); } while (0)
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* Special buffers are used for the event queues and the TX and RX
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* descriptor queues for each channel. They are *not* used for the
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* actual transmit and receive buffers.
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*
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* Note that for Falcon, TX and RX descriptor queues live in host memory.
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* Allocation and freeing procedures must take this into account.
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*/
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struct efx_special_buffer {
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void *addr;
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@ -300,7 +297,7 @@ struct efx_rx_queue {
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* @dma_addr: DMA base address of the buffer
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* @len: Buffer length, in bytes
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*
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* Falcon uses these buffers for its interrupt status registers and
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* The NIC uses these buffers for its interrupt status registers and
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* MAC stats dumps.
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*/
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struct efx_buffer {
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@ -674,7 +671,7 @@ union efx_multicast_hash {
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* @irq_status: Interrupt status buffer
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* @last_irq_cpu: Last CPU to handle interrupt.
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* This register is written with the SMP processor ID whenever an
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* interrupt is handled. It is used by falcon_test_interrupt()
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* interrupt is handled. It is used by efx_nic_test_interrupt()
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* to verify that an interrupt has occurred.
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* @spi_flash: SPI flash device
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* This field will be %NULL if no flash device is present (or for Siena).
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@ -723,8 +720,7 @@ union efx_multicast_hash {
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* @loopback_modes: Supported loopback mode bitmask
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* @loopback_selftest: Offline self-test private state
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*
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* The @priv field of the corresponding &struct net_device points to
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* this.
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* This is stored in the private area of the &struct net_device.
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*/
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struct efx_nic {
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char name[IFNAMSIZ];
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@ -997,7 +993,7 @@ static inline void clear_bit_le(unsigned nr, unsigned char *addr)
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* that the net driver will program into the MAC as the maximum frame
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* length.
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*
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* The 10G MAC used in Falcon requires 8-byte alignment on the frame
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* The 10G MAC requires 8-byte alignment on the frame
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* length, so we round up to the nearest 8.
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*
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* Re-clocking by the XGXS on RX can reduce an IPG to 32 bits (half an
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@ -623,10 +623,6 @@ void efx_nic_remove_rx(struct efx_rx_queue *rx_queue)
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*
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* This writes the EVQ_RPTR_REG register for the specified channel's
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* event queue.
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*
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* Note that EVQ_RPTR_REG contains the index of the "last read" event,
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* whereas channel->eventq_read_ptr contains the index of the "next to
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* read" event.
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*/
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void efx_nic_eventq_read_ack(struct efx_channel *channel)
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{
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