mips: dts: realtek: Add RTL9302C board

Add support for the RTL9302 SoC and the RTL9302C_2xRTL8224_2XGE
reference board.

The RTL930x family of SoCs are Realtek switches with an embedded MIPS
core (800MHz 34Kc). Most of the peripherals are similar to the RTL838x
SoC and can make use of many existing drivers.

Add in full DSA switch support is still a work in progress.

Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
This commit is contained in:
Chris Packham 2024-07-10 16:35:24 +12:00 committed by Thomas Bogendoerfer
parent 662c0002ca
commit 74beefb593
3 changed files with 153 additions and 0 deletions

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@ -1,2 +1,3 @@
# SPDX-License-Identifier: GPL-2.0
dtb-y += cisco_sg220-26.dtb
dtb-y += cameo-rtl9302c-2x-rtl8224-2xge.dtb

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// SPDX-License-Identifier: GPL-2.0-or-later
/dts-v1/;
#include "rtl930x.dtsi"
#include <dt-bindings/input/input.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/leds/common.h>
#include <dt-bindings/thermal/thermal.h>
/ {
compatible = "cameo,rtl9302c-2x-rtl8224-2xge", "realtek,rtl9302-soc";
model = "RTL9302C Development Board";
memory@0 {
device_type = "memory";
reg = <0x0 0x8000000>;
};
chosen {
stdout-path = "serial0:115200n8";
};
};
&uart0 {
status = "okay";
};
&spi0 {
status = "okay";
flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <10000000>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "LOADER";
reg = <0x0 0xe0000>;
read-only;
};
partition@e0000 {
label = "BDINFO";
reg = <0xe0000 0x10000>;
};
partition@f0000 {
label = "SYSINFO";
reg = <0xf0000 0x10000>;
read-only;
};
partition@100000 {
label = "JFFS2 CFG";
reg = <0x100000 0x100000>;
};
partition@200000 {
label = "JFFS2 LOG";
reg = <0x200000 0x100000>;
};
partition@300000 {
label = "RUNTIME";
reg = <0x300000 0xe80000>;
};
partition@1180000 {
label = "RUNTIME2";
reg = <0x1180000 0xe80000>;
};
};
};
};

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// SPDX-License-Identifier: GPL-2.0-or-later OR BSD-2-Clause
#include "rtl83xx.dtsi"
/ {
compatible = "realtek,rtl9302-soc";
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
device_type = "cpu";
compatible = "mips,mips34Kc";
reg = <0>;
clocks = <&baseclk 0>;
clock-names = "cpu";
};
};
baseclk: clock-800mhz {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <800000000>;
};
lx_clk: clock-175mhz {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <175000000>;
};
};
&soc {
intc: interrupt-controller@3000 {
compatible = "realtek,rtl9300-intc", "realtek,rtl-intc";
reg = <0x3000 0x18>, <0x3018 0x18>;
interrupt-controller;
#interrupt-cells = <1>;
interrupt-parent = <&cpuintc>;
interrupts = <2>, <3>, <4>, <5>, <6>, <7>;
};
spi0: spi@1200 {
compatible = "realtek,rtl8380-spi";
reg = <0x1200 0x100>;
#address-cells = <1>;
#size-cells = <0>;
};
timer0: timer@3200 {
compatible = "realtek,rtl9302-timer", "realtek,otto-timer";
reg = <0x3200 0x10>, <0x3210 0x10>, <0x3220 0x10>,
<0x3230 0x10>, <0x3240 0x10>;
interrupt-parent = <&intc>;
interrupts = <7>, <8>, <9>, <10>, <11>;
clocks = <&lx_clk>;
};
};
&uart0 {
/delete-property/ clock-frequency;
clocks = <&lx_clk>;
interrupt-parent = <&intc>;
interrupts = <30>;
};
&uart1 {
/delete-property/ clock-frequency;
clocks = <&lx_clk>;
interrupt-parent = <&intc>;
interrupts = <31>;
};