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rtc: abx80x: add basic watchdog support
The abx804 and abx805 chips have support for a simple watchdog function that can trigger an external reset. Signed-off-by: Jeremy Gebben <jgebben@sweptlaser.com> Reviewed-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
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@ -187,6 +187,7 @@ config RTC_DRV_ABB5ZES3
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config RTC_DRV_ABX80X
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config RTC_DRV_ABX80X
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tristate "Abracon ABx80x"
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tristate "Abracon ABx80x"
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select WATCHDOG_CORE if WATCHDOG
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help
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help
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If you say yes here you get support for Abracon AB080X and AB180X
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If you say yes here you get support for Abracon AB080X and AB180X
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families of ultra-low-power battery- and capacitor-backed real-time
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families of ultra-low-power battery- and capacitor-backed real-time
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@ -17,6 +17,7 @@
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#include <linux/i2c.h>
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#include <linux/i2c.h>
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#include <linux/module.h>
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#include <linux/module.h>
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#include <linux/rtc.h>
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#include <linux/rtc.h>
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#include <linux/watchdog.h>
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#define ABX8XX_REG_HTH 0x00
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#define ABX8XX_REG_HTH 0x00
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#define ABX8XX_REG_SC 0x01
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#define ABX8XX_REG_SC 0x01
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@ -37,6 +38,7 @@
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#define ABX8XX_REG_STATUS 0x0f
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#define ABX8XX_REG_STATUS 0x0f
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#define ABX8XX_STATUS_AF BIT(2)
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#define ABX8XX_STATUS_AF BIT(2)
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#define ABX8XX_STATUS_WDT BIT(6)
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#define ABX8XX_REG_CTRL1 0x10
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#define ABX8XX_REG_CTRL1 0x10
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#define ABX8XX_CTRL_WRITE BIT(0)
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#define ABX8XX_CTRL_WRITE BIT(0)
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@ -61,6 +63,14 @@
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#define ABX8XX_OSS_OF BIT(1)
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#define ABX8XX_OSS_OF BIT(1)
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#define ABX8XX_OSS_OMODE BIT(4)
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#define ABX8XX_OSS_OMODE BIT(4)
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#define ABX8XX_REG_WDT 0x1b
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#define ABX8XX_WDT_WDS BIT(7)
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#define ABX8XX_WDT_BMB_MASK 0x7c
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#define ABX8XX_WDT_BMB_SHIFT 2
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#define ABX8XX_WDT_MAX_TIME (ABX8XX_WDT_BMB_MASK >> ABX8XX_WDT_BMB_SHIFT)
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#define ABX8XX_WDT_WRB_MASK 0x03
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#define ABX8XX_WDT_WRB_1HZ 0x02
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#define ABX8XX_REG_CFG_KEY 0x1f
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#define ABX8XX_REG_CFG_KEY 0x1f
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#define ABX8XX_CFG_KEY_OSC 0xa1
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#define ABX8XX_CFG_KEY_OSC 0xa1
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#define ABX8XX_CFG_KEY_MISC 0x9d
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#define ABX8XX_CFG_KEY_MISC 0x9d
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@ -80,23 +90,25 @@ enum abx80x_chip {AB0801, AB0803, AB0804, AB0805,
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struct abx80x_cap {
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struct abx80x_cap {
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u16 pn;
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u16 pn;
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bool has_tc;
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bool has_tc;
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bool has_wdog;
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};
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};
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static struct abx80x_cap abx80x_caps[] = {
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static struct abx80x_cap abx80x_caps[] = {
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[AB0801] = {.pn = 0x0801},
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[AB0801] = {.pn = 0x0801},
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[AB0803] = {.pn = 0x0803},
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[AB0803] = {.pn = 0x0803},
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[AB0804] = {.pn = 0x0804, .has_tc = true},
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[AB0804] = {.pn = 0x0804, .has_tc = true, .has_wdog = true},
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[AB0805] = {.pn = 0x0805, .has_tc = true},
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[AB0805] = {.pn = 0x0805, .has_tc = true, .has_wdog = true},
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[AB1801] = {.pn = 0x1801},
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[AB1801] = {.pn = 0x1801},
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[AB1803] = {.pn = 0x1803},
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[AB1803] = {.pn = 0x1803},
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[AB1804] = {.pn = 0x1804, .has_tc = true},
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[AB1804] = {.pn = 0x1804, .has_tc = true, .has_wdog = true},
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[AB1805] = {.pn = 0x1805, .has_tc = true},
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[AB1805] = {.pn = 0x1805, .has_tc = true, .has_wdog = true},
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[ABX80X] = {.pn = 0}
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[ABX80X] = {.pn = 0}
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};
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};
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struct abx80x_priv {
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struct abx80x_priv {
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struct rtc_device *rtc;
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struct rtc_device *rtc;
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struct i2c_client *client;
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struct i2c_client *client;
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struct watchdog_device wdog;
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};
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};
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static int abx80x_is_rc_mode(struct i2c_client *client)
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static int abx80x_is_rc_mode(struct i2c_client *client)
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@ -234,6 +246,13 @@ static irqreturn_t abx80x_handle_irq(int irq, void *dev_id)
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if (status & ABX8XX_STATUS_AF)
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if (status & ABX8XX_STATUS_AF)
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rtc_update_irq(rtc, 1, RTC_AF | RTC_IRQF);
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rtc_update_irq(rtc, 1, RTC_AF | RTC_IRQF);
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/*
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* It is unclear if we'll get an interrupt before the external
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* reset kicks in.
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*/
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if (status & ABX8XX_STATUS_WDT)
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dev_alert(&client->dev, "watchdog timeout interrupt.\n");
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i2c_smbus_write_byte_data(client, ABX8XX_REG_STATUS, 0);
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i2c_smbus_write_byte_data(client, ABX8XX_REG_STATUS, 0);
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return IRQ_HANDLED;
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return IRQ_HANDLED;
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@ -535,6 +554,89 @@ static void rtc_calib_remove_sysfs_group(void *_dev)
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sysfs_remove_group(&dev->kobj, &rtc_calib_attr_group);
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sysfs_remove_group(&dev->kobj, &rtc_calib_attr_group);
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}
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}
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#ifdef CONFIG_WATCHDOG
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static inline u8 timeout_bits(unsigned int timeout)
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{
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return ((timeout << ABX8XX_WDT_BMB_SHIFT) & ABX8XX_WDT_BMB_MASK) |
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ABX8XX_WDT_WRB_1HZ;
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}
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static int __abx80x_wdog_set_timeout(struct watchdog_device *wdog,
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unsigned int timeout)
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{
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struct abx80x_priv *priv = watchdog_get_drvdata(wdog);
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u8 val = ABX8XX_WDT_WDS | timeout_bits(timeout);
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/*
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* Writing any timeout to the WDT register resets the watchdog timer.
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* Writing 0 disables it.
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*/
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return i2c_smbus_write_byte_data(priv->client, ABX8XX_REG_WDT, val);
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}
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static int abx80x_wdog_set_timeout(struct watchdog_device *wdog,
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unsigned int new_timeout)
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{
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int err = 0;
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if (watchdog_hw_running(wdog))
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err = __abx80x_wdog_set_timeout(wdog, new_timeout);
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if (err == 0)
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wdog->timeout = new_timeout;
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return err;
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}
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static int abx80x_wdog_ping(struct watchdog_device *wdog)
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{
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return __abx80x_wdog_set_timeout(wdog, wdog->timeout);
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}
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static int abx80x_wdog_start(struct watchdog_device *wdog)
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{
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return __abx80x_wdog_set_timeout(wdog, wdog->timeout);
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}
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static int abx80x_wdog_stop(struct watchdog_device *wdog)
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{
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return __abx80x_wdog_set_timeout(wdog, 0);
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}
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static const struct watchdog_info abx80x_wdog_info = {
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.identity = "abx80x watchdog",
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.options = WDIOF_KEEPALIVEPING | WDIOF_SETTIMEOUT | WDIOF_MAGICCLOSE,
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};
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static const struct watchdog_ops abx80x_wdog_ops = {
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.owner = THIS_MODULE,
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.start = abx80x_wdog_start,
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.stop = abx80x_wdog_stop,
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.ping = abx80x_wdog_ping,
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.set_timeout = abx80x_wdog_set_timeout,
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};
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static int abx80x_setup_watchdog(struct abx80x_priv *priv)
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{
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priv->wdog.parent = &priv->client->dev;
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priv->wdog.ops = &abx80x_wdog_ops;
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priv->wdog.info = &abx80x_wdog_info;
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priv->wdog.min_timeout = 1;
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priv->wdog.max_timeout = ABX8XX_WDT_MAX_TIME;
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priv->wdog.timeout = ABX8XX_WDT_MAX_TIME;
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watchdog_set_drvdata(&priv->wdog, priv);
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return devm_watchdog_register_device(&priv->client->dev, &priv->wdog);
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}
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#else
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static int abx80x_setup_watchdog(struct abx80x_priv *priv)
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{
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return 0;
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}
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#endif
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static int abx80x_probe(struct i2c_client *client,
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static int abx80x_probe(struct i2c_client *client,
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const struct i2c_device_id *id)
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const struct i2c_device_id *id)
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{
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{
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@ -629,6 +731,12 @@ static int abx80x_probe(struct i2c_client *client,
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i2c_set_clientdata(client, priv);
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i2c_set_clientdata(client, priv);
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if (abx80x_caps[part].has_wdog) {
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err = abx80x_setup_watchdog(priv);
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if (err)
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return err;
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}
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if (client->irq > 0) {
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if (client->irq > 0) {
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dev_info(&client->dev, "IRQ %d supplied\n", client->irq);
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dev_info(&client->dev, "IRQ %d supplied\n", client->irq);
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err = devm_request_threaded_irq(&client->dev, client->irq, NULL,
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err = devm_request_threaded_irq(&client->dev, client->irq, NULL,
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