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RISC-V: KVM: Add in-kernel emulation of AIA APLIC
There is no virtualization support in AIA APLIC so we add in-kernel emulation of AIA APLIC which only supports MSI-mode (i.e. wired interrupts forwarded to AIA IMSIC as MSIs). Signed-off-by: Anup Patel <apatel@ventanamicro.com> Reviewed-by: Atish Patra <atishp@rivosinc.com> Signed-off-by: Anup Patel <anup@brainfault.org>
This commit is contained in:
Anup Patel
Anup Patel
parent
89d01306e3
commit
74967aa208
@ -129,20 +129,9 @@ static inline void kvm_riscv_vcpu_aia_imsic_cleanup(struct kvm_vcpu *vcpu)
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{
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}
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static inline int kvm_riscv_aia_aplic_inject(struct kvm *kvm,
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u32 source, bool level)
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{
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return 0;
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}
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static inline int kvm_riscv_aia_aplic_init(struct kvm *kvm)
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{
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return 0;
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}
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static inline void kvm_riscv_aia_aplic_cleanup(struct kvm *kvm)
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{
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}
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int kvm_riscv_aia_aplic_inject(struct kvm *kvm, u32 source, bool level);
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int kvm_riscv_aia_aplic_init(struct kvm *kvm);
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void kvm_riscv_aia_aplic_cleanup(struct kvm *kvm);
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#ifdef CONFIG_32BIT
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void kvm_riscv_vcpu_aia_flush_interrupts(struct kvm_vcpu *vcpu);
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@ -28,3 +28,4 @@ kvm-y += vcpu_timer.o
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kvm-$(CONFIG_RISCV_PMU_SBI) += vcpu_pmu.o vcpu_sbi_pmu.o
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kvm-y += aia.o
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kvm-y += aia_device.o
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kvm-y += aia_aplic.o
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576
arch/riscv/kvm/aia_aplic.c
Normal file
576
arch/riscv/kvm/aia_aplic.c
Normal file
@ -0,0 +1,576 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2021 Western Digital Corporation or its affiliates.
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* Copyright (C) 2022 Ventana Micro Systems Inc.
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*
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* Authors:
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* Anup Patel <apatel@ventanamicro.com>
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*/
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#include <linux/kvm_host.h>
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#include <linux/math.h>
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#include <linux/spinlock.h>
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#include <linux/swab.h>
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#include <kvm/iodev.h>
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#include <asm/kvm_aia_aplic.h>
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struct aplic_irq {
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raw_spinlock_t lock;
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u32 sourcecfg;
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u32 state;
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#define APLIC_IRQ_STATE_PENDING BIT(0)
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#define APLIC_IRQ_STATE_ENABLED BIT(1)
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#define APLIC_IRQ_STATE_ENPEND (APLIC_IRQ_STATE_PENDING | \
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APLIC_IRQ_STATE_ENABLED)
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#define APLIC_IRQ_STATE_INPUT BIT(8)
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u32 target;
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};
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struct aplic {
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struct kvm_io_device iodev;
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u32 domaincfg;
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u32 genmsi;
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u32 nr_irqs;
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u32 nr_words;
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struct aplic_irq *irqs;
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};
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static u32 aplic_read_sourcecfg(struct aplic *aplic, u32 irq)
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{
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u32 ret;
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unsigned long flags;
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struct aplic_irq *irqd;
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if (!irq || aplic->nr_irqs <= irq)
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return 0;
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irqd = &aplic->irqs[irq];
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raw_spin_lock_irqsave(&irqd->lock, flags);
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ret = irqd->sourcecfg;
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raw_spin_unlock_irqrestore(&irqd->lock, flags);
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return ret;
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}
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static void aplic_write_sourcecfg(struct aplic *aplic, u32 irq, u32 val)
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{
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unsigned long flags;
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struct aplic_irq *irqd;
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if (!irq || aplic->nr_irqs <= irq)
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return;
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irqd = &aplic->irqs[irq];
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if (val & APLIC_SOURCECFG_D)
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val = 0;
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else
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val &= APLIC_SOURCECFG_SM_MASK;
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raw_spin_lock_irqsave(&irqd->lock, flags);
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irqd->sourcecfg = val;
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raw_spin_unlock_irqrestore(&irqd->lock, flags);
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}
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static u32 aplic_read_target(struct aplic *aplic, u32 irq)
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{
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u32 ret;
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unsigned long flags;
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struct aplic_irq *irqd;
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if (!irq || aplic->nr_irqs <= irq)
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return 0;
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irqd = &aplic->irqs[irq];
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raw_spin_lock_irqsave(&irqd->lock, flags);
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ret = irqd->target;
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raw_spin_unlock_irqrestore(&irqd->lock, flags);
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return ret;
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}
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static void aplic_write_target(struct aplic *aplic, u32 irq, u32 val)
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{
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unsigned long flags;
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struct aplic_irq *irqd;
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if (!irq || aplic->nr_irqs <= irq)
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return;
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irqd = &aplic->irqs[irq];
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val &= APLIC_TARGET_EIID_MASK |
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(APLIC_TARGET_HART_IDX_MASK << APLIC_TARGET_HART_IDX_SHIFT) |
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(APLIC_TARGET_GUEST_IDX_MASK << APLIC_TARGET_GUEST_IDX_SHIFT);
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raw_spin_lock_irqsave(&irqd->lock, flags);
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irqd->target = val;
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raw_spin_unlock_irqrestore(&irqd->lock, flags);
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}
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static bool aplic_read_pending(struct aplic *aplic, u32 irq)
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{
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bool ret;
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unsigned long flags;
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struct aplic_irq *irqd;
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if (!irq || aplic->nr_irqs <= irq)
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return false;
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irqd = &aplic->irqs[irq];
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raw_spin_lock_irqsave(&irqd->lock, flags);
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ret = (irqd->state & APLIC_IRQ_STATE_PENDING) ? true : false;
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raw_spin_unlock_irqrestore(&irqd->lock, flags);
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return ret;
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}
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static void aplic_write_pending(struct aplic *aplic, u32 irq, bool pending)
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{
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unsigned long flags, sm;
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struct aplic_irq *irqd;
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if (!irq || aplic->nr_irqs <= irq)
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return;
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irqd = &aplic->irqs[irq];
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raw_spin_lock_irqsave(&irqd->lock, flags);
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sm = irqd->sourcecfg & APLIC_SOURCECFG_SM_MASK;
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if (!pending &&
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((sm == APLIC_SOURCECFG_SM_LEVEL_HIGH) ||
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(sm == APLIC_SOURCECFG_SM_LEVEL_LOW)))
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goto skip_write_pending;
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if (pending)
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irqd->state |= APLIC_IRQ_STATE_PENDING;
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else
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irqd->state &= ~APLIC_IRQ_STATE_PENDING;
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skip_write_pending:
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raw_spin_unlock_irqrestore(&irqd->lock, flags);
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}
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static bool aplic_read_enabled(struct aplic *aplic, u32 irq)
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{
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bool ret;
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unsigned long flags;
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struct aplic_irq *irqd;
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if (!irq || aplic->nr_irqs <= irq)
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return false;
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irqd = &aplic->irqs[irq];
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raw_spin_lock_irqsave(&irqd->lock, flags);
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ret = (irqd->state & APLIC_IRQ_STATE_ENABLED) ? true : false;
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raw_spin_unlock_irqrestore(&irqd->lock, flags);
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return ret;
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}
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static void aplic_write_enabled(struct aplic *aplic, u32 irq, bool enabled)
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{
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unsigned long flags;
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struct aplic_irq *irqd;
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if (!irq || aplic->nr_irqs <= irq)
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return;
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irqd = &aplic->irqs[irq];
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raw_spin_lock_irqsave(&irqd->lock, flags);
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if (enabled)
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irqd->state |= APLIC_IRQ_STATE_ENABLED;
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else
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irqd->state &= ~APLIC_IRQ_STATE_ENABLED;
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raw_spin_unlock_irqrestore(&irqd->lock, flags);
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}
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static bool aplic_read_input(struct aplic *aplic, u32 irq)
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{
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bool ret;
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unsigned long flags;
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struct aplic_irq *irqd;
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if (!irq || aplic->nr_irqs <= irq)
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return false;
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irqd = &aplic->irqs[irq];
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raw_spin_lock_irqsave(&irqd->lock, flags);
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ret = (irqd->state & APLIC_IRQ_STATE_INPUT) ? true : false;
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raw_spin_unlock_irqrestore(&irqd->lock, flags);
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return ret;
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}
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static void aplic_inject_msi(struct kvm *kvm, u32 irq, u32 target)
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{
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u32 hart_idx, guest_idx, eiid;
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hart_idx = target >> APLIC_TARGET_HART_IDX_SHIFT;
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hart_idx &= APLIC_TARGET_HART_IDX_MASK;
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guest_idx = target >> APLIC_TARGET_GUEST_IDX_SHIFT;
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guest_idx &= APLIC_TARGET_GUEST_IDX_MASK;
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eiid = target & APLIC_TARGET_EIID_MASK;
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kvm_riscv_aia_inject_msi_by_id(kvm, hart_idx, guest_idx, eiid);
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}
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static void aplic_update_irq_range(struct kvm *kvm, u32 first, u32 last)
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{
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bool inject;
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u32 irq, target;
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unsigned long flags;
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struct aplic_irq *irqd;
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struct aplic *aplic = kvm->arch.aia.aplic_state;
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if (!(aplic->domaincfg & APLIC_DOMAINCFG_IE))
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return;
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for (irq = first; irq <= last; irq++) {
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if (!irq || aplic->nr_irqs <= irq)
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continue;
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irqd = &aplic->irqs[irq];
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raw_spin_lock_irqsave(&irqd->lock, flags);
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inject = false;
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target = irqd->target;
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if ((irqd->state & APLIC_IRQ_STATE_ENPEND) ==
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APLIC_IRQ_STATE_ENPEND) {
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irqd->state &= ~APLIC_IRQ_STATE_PENDING;
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inject = true;
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}
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raw_spin_unlock_irqrestore(&irqd->lock, flags);
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if (inject)
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aplic_inject_msi(kvm, irq, target);
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}
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}
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int kvm_riscv_aia_aplic_inject(struct kvm *kvm, u32 source, bool level)
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{
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u32 target;
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bool inject = false, ie;
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unsigned long flags;
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struct aplic_irq *irqd;
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struct aplic *aplic = kvm->arch.aia.aplic_state;
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if (!aplic || !source || (aplic->nr_irqs <= source))
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return -ENODEV;
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irqd = &aplic->irqs[source];
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ie = (aplic->domaincfg & APLIC_DOMAINCFG_IE) ? true : false;
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raw_spin_lock_irqsave(&irqd->lock, flags);
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if (irqd->sourcecfg & APLIC_SOURCECFG_D)
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goto skip_unlock;
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switch (irqd->sourcecfg & APLIC_SOURCECFG_SM_MASK) {
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case APLIC_SOURCECFG_SM_EDGE_RISE:
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if (level && !(irqd->state & APLIC_IRQ_STATE_INPUT) &&
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!(irqd->state & APLIC_IRQ_STATE_PENDING))
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irqd->state |= APLIC_IRQ_STATE_PENDING;
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break;
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case APLIC_SOURCECFG_SM_EDGE_FALL:
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if (!level && (irqd->state & APLIC_IRQ_STATE_INPUT) &&
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!(irqd->state & APLIC_IRQ_STATE_PENDING))
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irqd->state |= APLIC_IRQ_STATE_PENDING;
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break;
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case APLIC_SOURCECFG_SM_LEVEL_HIGH:
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if (level && !(irqd->state & APLIC_IRQ_STATE_PENDING))
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irqd->state |= APLIC_IRQ_STATE_PENDING;
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break;
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case APLIC_SOURCECFG_SM_LEVEL_LOW:
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if (!level && !(irqd->state & APLIC_IRQ_STATE_PENDING))
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irqd->state |= APLIC_IRQ_STATE_PENDING;
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break;
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}
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if (level)
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irqd->state |= APLIC_IRQ_STATE_INPUT;
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else
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irqd->state &= ~APLIC_IRQ_STATE_INPUT;
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target = irqd->target;
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if (ie && ((irqd->state & APLIC_IRQ_STATE_ENPEND) ==
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APLIC_IRQ_STATE_ENPEND)) {
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irqd->state &= ~APLIC_IRQ_STATE_PENDING;
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inject = true;
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}
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skip_unlock:
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raw_spin_unlock_irqrestore(&irqd->lock, flags);
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if (inject)
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aplic_inject_msi(kvm, source, target);
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return 0;
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}
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static u32 aplic_read_input_word(struct aplic *aplic, u32 word)
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{
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u32 i, ret = 0;
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for (i = 0; i < 32; i++)
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ret |= aplic_read_input(aplic, word * 32 + i) ? BIT(i) : 0;
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return ret;
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}
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static u32 aplic_read_pending_word(struct aplic *aplic, u32 word)
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{
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u32 i, ret = 0;
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for (i = 0; i < 32; i++)
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ret |= aplic_read_pending(aplic, word * 32 + i) ? BIT(i) : 0;
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return ret;
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}
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static void aplic_write_pending_word(struct aplic *aplic, u32 word,
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u32 val, bool pending)
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{
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u32 i;
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for (i = 0; i < 32; i++) {
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if (val & BIT(i))
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aplic_write_pending(aplic, word * 32 + i, pending);
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}
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}
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static u32 aplic_read_enabled_word(struct aplic *aplic, u32 word)
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{
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u32 i, ret = 0;
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for (i = 0; i < 32; i++)
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ret |= aplic_read_enabled(aplic, word * 32 + i) ? BIT(i) : 0;
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return ret;
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}
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static void aplic_write_enabled_word(struct aplic *aplic, u32 word,
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u32 val, bool enabled)
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{
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u32 i;
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for (i = 0; i < 32; i++) {
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if (val & BIT(i))
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aplic_write_enabled(aplic, word * 32 + i, enabled);
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}
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}
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static int aplic_mmio_read_offset(struct kvm *kvm, gpa_t off, u32 *val32)
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{
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u32 i;
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struct aplic *aplic = kvm->arch.aia.aplic_state;
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if ((off & 0x3) != 0)
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return -EOPNOTSUPP;
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if (off == APLIC_DOMAINCFG) {
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*val32 = APLIC_DOMAINCFG_RDONLY |
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aplic->domaincfg | APLIC_DOMAINCFG_DM;
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} else if ((off >= APLIC_SOURCECFG_BASE) &&
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(off < (APLIC_SOURCECFG_BASE + (aplic->nr_irqs - 1) * 4))) {
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i = ((off - APLIC_SOURCECFG_BASE) >> 2) + 1;
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*val32 = aplic_read_sourcecfg(aplic, i);
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} else if ((off >= APLIC_SETIP_BASE) &&
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(off < (APLIC_SETIP_BASE + aplic->nr_words * 4))) {
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i = (off - APLIC_SETIP_BASE) >> 2;
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*val32 = aplic_read_pending_word(aplic, i);
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} else if (off == APLIC_SETIPNUM) {
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*val32 = 0;
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} else if ((off >= APLIC_CLRIP_BASE) &&
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(off < (APLIC_CLRIP_BASE + aplic->nr_words * 4))) {
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i = (off - APLIC_CLRIP_BASE) >> 2;
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*val32 = aplic_read_input_word(aplic, i);
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} else if (off == APLIC_CLRIPNUM) {
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*val32 = 0;
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} else if ((off >= APLIC_SETIE_BASE) &&
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(off < (APLIC_SETIE_BASE + aplic->nr_words * 4))) {
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i = (off - APLIC_SETIE_BASE) >> 2;
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*val32 = aplic_read_enabled_word(aplic, i);
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} else if (off == APLIC_SETIENUM) {
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*val32 = 0;
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} else if ((off >= APLIC_CLRIE_BASE) &&
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(off < (APLIC_CLRIE_BASE + aplic->nr_words * 4))) {
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*val32 = 0;
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} else if (off == APLIC_CLRIENUM) {
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*val32 = 0;
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} else if (off == APLIC_SETIPNUM_LE) {
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*val32 = 0;
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} else if (off == APLIC_SETIPNUM_BE) {
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*val32 = 0;
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} else if (off == APLIC_GENMSI) {
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*val32 = aplic->genmsi;
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} else if ((off >= APLIC_TARGET_BASE) &&
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(off < (APLIC_TARGET_BASE + (aplic->nr_irqs - 1) * 4))) {
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i = ((off - APLIC_TARGET_BASE) >> 2) + 1;
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*val32 = aplic_read_target(aplic, i);
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} else
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return -ENODEV;
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return 0;
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}
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static int aplic_mmio_read(struct kvm_vcpu *vcpu, struct kvm_io_device *dev,
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gpa_t addr, int len, void *val)
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{
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if (len != 4)
|
||||
return -EOPNOTSUPP;
|
||||
|
||||
return aplic_mmio_read_offset(vcpu->kvm,
|
||||
addr - vcpu->kvm->arch.aia.aplic_addr,
|
||||
val);
|
||||
}
|
||||
|
||||
static int aplic_mmio_write_offset(struct kvm *kvm, gpa_t off, u32 val32)
|
||||
{
|
||||
u32 i;
|
||||
struct aplic *aplic = kvm->arch.aia.aplic_state;
|
||||
|
||||
if ((off & 0x3) != 0)
|
||||
return -EOPNOTSUPP;
|
||||
|
||||
if (off == APLIC_DOMAINCFG) {
|
||||
/* Only IE bit writeable */
|
||||
aplic->domaincfg = val32 & APLIC_DOMAINCFG_IE;
|
||||
} else if ((off >= APLIC_SOURCECFG_BASE) &&
|
||||
(off < (APLIC_SOURCECFG_BASE + (aplic->nr_irqs - 1) * 4))) {
|
||||
i = ((off - APLIC_SOURCECFG_BASE) >> 2) + 1;
|
||||
aplic_write_sourcecfg(aplic, i, val32);
|
||||
} else if ((off >= APLIC_SETIP_BASE) &&
|
||||
(off < (APLIC_SETIP_BASE + aplic->nr_words * 4))) {
|
||||
i = (off - APLIC_SETIP_BASE) >> 2;
|
||||
aplic_write_pending_word(aplic, i, val32, true);
|
||||
} else if (off == APLIC_SETIPNUM) {
|
||||
aplic_write_pending(aplic, val32, true);
|
||||
} else if ((off >= APLIC_CLRIP_BASE) &&
|
||||
(off < (APLIC_CLRIP_BASE + aplic->nr_words * 4))) {
|
||||
i = (off - APLIC_CLRIP_BASE) >> 2;
|
||||
aplic_write_pending_word(aplic, i, val32, false);
|
||||
} else if (off == APLIC_CLRIPNUM) {
|
||||
aplic_write_pending(aplic, val32, false);
|
||||
} else if ((off >= APLIC_SETIE_BASE) &&
|
||||
(off < (APLIC_SETIE_BASE + aplic->nr_words * 4))) {
|
||||
i = (off - APLIC_SETIE_BASE) >> 2;
|
||||
aplic_write_enabled_word(aplic, i, val32, true);
|
||||
} else if (off == APLIC_SETIENUM) {
|
||||
aplic_write_enabled(aplic, val32, true);
|
||||
} else if ((off >= APLIC_CLRIE_BASE) &&
|
||||
(off < (APLIC_CLRIE_BASE + aplic->nr_words * 4))) {
|
||||
i = (off - APLIC_CLRIE_BASE) >> 2;
|
||||
aplic_write_enabled_word(aplic, i, val32, false);
|
||||
} else if (off == APLIC_CLRIENUM) {
|
||||
aplic_write_enabled(aplic, val32, false);
|
||||
} else if (off == APLIC_SETIPNUM_LE) {
|
||||
aplic_write_pending(aplic, val32, true);
|
||||
} else if (off == APLIC_SETIPNUM_BE) {
|
||||
aplic_write_pending(aplic, __swab32(val32), true);
|
||||
} else if (off == APLIC_GENMSI) {
|
||||
aplic->genmsi = val32 & ~(APLIC_TARGET_GUEST_IDX_MASK <<
|
||||
APLIC_TARGET_GUEST_IDX_SHIFT);
|
||||
kvm_riscv_aia_inject_msi_by_id(kvm,
|
||||
val32 >> APLIC_TARGET_HART_IDX_SHIFT, 0,
|
||||
val32 & APLIC_TARGET_EIID_MASK);
|
||||
} else if ((off >= APLIC_TARGET_BASE) &&
|
||||
(off < (APLIC_TARGET_BASE + (aplic->nr_irqs - 1) * 4))) {
|
||||
i = ((off - APLIC_TARGET_BASE) >> 2) + 1;
|
||||
aplic_write_target(aplic, i, val32);
|
||||
} else
|
||||
return -ENODEV;
|
||||
|
||||
aplic_update_irq_range(kvm, 1, aplic->nr_irqs - 1);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int aplic_mmio_write(struct kvm_vcpu *vcpu, struct kvm_io_device *dev,
|
||||
gpa_t addr, int len, const void *val)
|
||||
{
|
||||
if (len != 4)
|
||||
return -EOPNOTSUPP;
|
||||
|
||||
return aplic_mmio_write_offset(vcpu->kvm,
|
||||
addr - vcpu->kvm->arch.aia.aplic_addr,
|
||||
*((const u32 *)val));
|
||||
}
|
||||
|
||||
static struct kvm_io_device_ops aplic_iodoev_ops = {
|
||||
.read = aplic_mmio_read,
|
||||
.write = aplic_mmio_write,
|
||||
};
|
||||
|
||||
int kvm_riscv_aia_aplic_init(struct kvm *kvm)
|
||||
{
|
||||
int i, ret = 0;
|
||||
struct aplic *aplic;
|
||||
|
||||
/* Do nothing if we have zero sources */
|
||||
if (!kvm->arch.aia.nr_sources)
|
||||
return 0;
|
||||
|
||||
/* Allocate APLIC global state */
|
||||
aplic = kzalloc(sizeof(*aplic), GFP_KERNEL);
|
||||
if (!aplic)
|
||||
return -ENOMEM;
|
||||
kvm->arch.aia.aplic_state = aplic;
|
||||
|
||||
/* Setup APLIC IRQs */
|
||||
aplic->nr_irqs = kvm->arch.aia.nr_sources + 1;
|
||||
aplic->nr_words = DIV_ROUND_UP(aplic->nr_irqs, 32);
|
||||
aplic->irqs = kcalloc(aplic->nr_irqs,
|
||||
sizeof(*aplic->irqs), GFP_KERNEL);
|
||||
if (!aplic->irqs) {
|
||||
ret = -ENOMEM;
|
||||
goto fail_free_aplic;
|
||||
}
|
||||
for (i = 0; i < aplic->nr_irqs; i++)
|
||||
raw_spin_lock_init(&aplic->irqs[i].lock);
|
||||
|
||||
/* Setup IO device */
|
||||
kvm_iodevice_init(&aplic->iodev, &aplic_iodoev_ops);
|
||||
mutex_lock(&kvm->slots_lock);
|
||||
ret = kvm_io_bus_register_dev(kvm, KVM_MMIO_BUS,
|
||||
kvm->arch.aia.aplic_addr,
|
||||
KVM_DEV_RISCV_APLIC_SIZE,
|
||||
&aplic->iodev);
|
||||
mutex_unlock(&kvm->slots_lock);
|
||||
if (ret)
|
||||
goto fail_free_aplic_irqs;
|
||||
|
||||
/* Setup default IRQ routing */
|
||||
ret = kvm_riscv_setup_default_irq_routing(kvm, aplic->nr_irqs);
|
||||
if (ret)
|
||||
goto fail_unreg_iodev;
|
||||
|
||||
return 0;
|
||||
|
||||
fail_unreg_iodev:
|
||||
mutex_lock(&kvm->slots_lock);
|
||||
kvm_io_bus_unregister_dev(kvm, KVM_MMIO_BUS, &aplic->iodev);
|
||||
mutex_unlock(&kvm->slots_lock);
|
||||
fail_free_aplic_irqs:
|
||||
kfree(aplic->irqs);
|
||||
fail_free_aplic:
|
||||
kvm->arch.aia.aplic_state = NULL;
|
||||
kfree(aplic);
|
||||
return ret;
|
||||
}
|
||||
|
||||
void kvm_riscv_aia_aplic_cleanup(struct kvm *kvm)
|
||||
{
|
||||
struct aplic *aplic = kvm->arch.aia.aplic_state;
|
||||
|
||||
if (!aplic)
|
||||
return;
|
||||
|
||||
mutex_lock(&kvm->slots_lock);
|
||||
kvm_io_bus_unregister_dev(kvm, KVM_MMIO_BUS, &aplic->iodev);
|
||||
mutex_unlock(&kvm->slots_lock);
|
||||
|
||||
kfree(aplic->irqs);
|
||||
|
||||
kvm->arch.aia.aplic_state = NULL;
|
||||
kfree(aplic);
|
||||
}
|
||||
Loading…
Reference in New Issue
Block a user