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phy: renesas: Add Renesas Ethernet SERDES driver for R-Car S4-8
Add Renesas Ethernet SERDES driver for R-Car S4-8 (r8a779f0). The datasheet describes initialization procedure without any information about registers' name/bits. So, this is all black magic to initialize the hardware. Especially, all channels should be initialized at once. Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Link: https://lore.kernel.org/r/20221108005500.3011449-3-yoshihiro.shimoda.uh@renesas.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
This commit is contained in:
Yoshihiro Shimoda
Vinod Koul
parent
d7abac0845
commit
742859441d
@ -2,6 +2,14 @@
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#
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# Phy drivers for Renesas platforms
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#
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# NOTE: Please sorted config names alphabetically.
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config PHY_R8A779F0_ETHERNET_SERDES
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tristate "Renesas R-Car S4-8 Ethernet SERDES driver"
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depends on ARCH_RENESAS || COMPILE_TEST
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select GENERIC_PHY
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help
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Support for Ethernet SERDES found on Renesas R-Car S4-8 SoCs.
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config PHY_RCAR_GEN2
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tristate "Renesas R-Car generation 2 USB PHY driver"
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depends on ARCH_RENESAS
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@ -1,4 +1,5 @@
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# SPDX-License-Identifier: GPL-2.0
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obj-$(CONFIG_PHY_R8A779F0_ETHERNET_SERDES) += r8a779f0-ether-serdes.o
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obj-$(CONFIG_PHY_RCAR_GEN2) += phy-rcar-gen2.o
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obj-$(CONFIG_PHY_RCAR_GEN3_PCIE) += phy-rcar-gen3-pcie.o
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obj-$(CONFIG_PHY_RCAR_GEN3_USB2) += phy-rcar-gen3-usb2.o
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417
drivers/phy/renesas/r8a779f0-ether-serdes.c
Normal file
417
drivers/phy/renesas/r8a779f0-ether-serdes.c
Normal file
@ -0,0 +1,417 @@
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// SPDX-License-Identifier: GPL-2.0
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/* Renesas Ethernet SERDES device driver
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*
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* Copyright (C) 2022 Renesas Electronics Corporation
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*/
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#include <linux/delay.h>
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#include <linux/err.h>
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#include <linux/iopoll.h>
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#include <linux/kernel.h>
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#include <linux/phy.h>
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#include <linux/phy/phy.h>
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#include <linux/platform_device.h>
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#include <linux/reset.h>
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#define R8A779F0_ETH_SERDES_NUM 3
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#define R8A779F0_ETH_SERDES_OFFSET 0x0400
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#define R8A779F0_ETH_SERDES_BANK_SELECT 0x03fc
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#define R8A779F0_ETH_SERDES_TIMEOUT_US 100000
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#define R8A779F0_ETH_SERDES_NUM_RETRY_LINKUP 3
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#define R8A779F0_ETH_SERDES_NUM_RETRY_INIT 3
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struct r8a779f0_eth_serdes_drv_data;
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struct r8a779f0_eth_serdes_channel {
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struct r8a779f0_eth_serdes_drv_data *dd;
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struct phy *phy;
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void __iomem *addr;
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phy_interface_t phy_interface;
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int speed;
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int index;
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};
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struct r8a779f0_eth_serdes_drv_data {
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void __iomem *addr;
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struct platform_device *pdev;
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struct reset_control *reset;
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struct r8a779f0_eth_serdes_channel channel[R8A779F0_ETH_SERDES_NUM];
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bool initialized;
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};
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/*
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* The datasheet describes initialization procedure without any information
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* about registers' name/bits. So, this is all black magic to initialize
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* the hardware.
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*/
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static void r8a779f0_eth_serdes_write32(void __iomem *addr, u32 offs, u32 bank, u32 data)
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{
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iowrite32(bank, addr + R8A779F0_ETH_SERDES_BANK_SELECT);
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iowrite32(data, addr + offs);
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}
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static int
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r8a779f0_eth_serdes_reg_wait(struct r8a779f0_eth_serdes_channel *channel,
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u32 offs, u32 bank, u32 mask, u32 expected)
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{
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int ret;
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u32 val;
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iowrite32(bank, channel->addr + R8A779F0_ETH_SERDES_BANK_SELECT);
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ret = readl_poll_timeout_atomic(channel->addr + offs, val,
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(val & mask) == expected,
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1, R8A779F0_ETH_SERDES_TIMEOUT_US);
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if (ret)
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dev_dbg(&channel->phy->dev,
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"%s: index %d, offs %x, bank %x, mask %x, expected %x\n",
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__func__, channel->index, offs, bank, mask, expected);
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return ret;
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}
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static int
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r8a779f0_eth_serdes_common_init_ram(struct r8a779f0_eth_serdes_drv_data *dd)
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{
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struct r8a779f0_eth_serdes_channel *channel;
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int i, ret;
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for (i = 0; i < R8A779F0_ETH_SERDES_NUM; i++) {
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channel = &dd->channel[i];
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ret = r8a779f0_eth_serdes_reg_wait(channel, 0x026c, 0x180, BIT(0), 0x01);
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if (ret)
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return ret;
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}
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r8a779f0_eth_serdes_write32(dd->addr, 0x026c, 0x180, 0x03);
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return ret;
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}
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static int
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r8a779f0_eth_serdes_common_setting(struct r8a779f0_eth_serdes_channel *channel)
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{
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struct r8a779f0_eth_serdes_drv_data *dd = channel->dd;
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switch (channel->phy_interface) {
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case PHY_INTERFACE_MODE_SGMII:
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r8a779f0_eth_serdes_write32(dd->addr, 0x0244, 0x180, 0x0097);
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r8a779f0_eth_serdes_write32(dd->addr, 0x01d0, 0x180, 0x0060);
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r8a779f0_eth_serdes_write32(dd->addr, 0x01d8, 0x180, 0x2200);
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r8a779f0_eth_serdes_write32(dd->addr, 0x01d4, 0x180, 0x0000);
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r8a779f0_eth_serdes_write32(dd->addr, 0x01e0, 0x180, 0x003d);
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return 0;
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default:
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return -EOPNOTSUPP;
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}
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}
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static int
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r8a779f0_eth_serdes_chan_setting(struct r8a779f0_eth_serdes_channel *channel)
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{
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int ret;
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switch (channel->phy_interface) {
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case PHY_INTERFACE_MODE_SGMII:
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r8a779f0_eth_serdes_write32(channel->addr, 0x0000, 0x380, 0x2000);
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r8a779f0_eth_serdes_write32(channel->addr, 0x01c0, 0x180, 0x0011);
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r8a779f0_eth_serdes_write32(channel->addr, 0x0248, 0x180, 0x0540);
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r8a779f0_eth_serdes_write32(channel->addr, 0x0258, 0x180, 0x0015);
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r8a779f0_eth_serdes_write32(channel->addr, 0x0144, 0x180, 0x0100);
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r8a779f0_eth_serdes_write32(channel->addr, 0x01a0, 0x180, 0x0000);
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r8a779f0_eth_serdes_write32(channel->addr, 0x00d0, 0x180, 0x0002);
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r8a779f0_eth_serdes_write32(channel->addr, 0x0150, 0x180, 0x0003);
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r8a779f0_eth_serdes_write32(channel->addr, 0x00c8, 0x180, 0x0100);
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r8a779f0_eth_serdes_write32(channel->addr, 0x0148, 0x180, 0x0100);
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r8a779f0_eth_serdes_write32(channel->addr, 0x0174, 0x180, 0x0000);
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r8a779f0_eth_serdes_write32(channel->addr, 0x0160, 0x180, 0x0007);
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r8a779f0_eth_serdes_write32(channel->addr, 0x01ac, 0x180, 0x0000);
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r8a779f0_eth_serdes_write32(channel->addr, 0x00c4, 0x180, 0x0310);
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r8a779f0_eth_serdes_write32(channel->addr, 0x00c8, 0x380, 0x0101);
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ret = r8a779f0_eth_serdes_reg_wait(channel, 0x00c8, 0x0180, BIT(0), 0);
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if (ret)
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return ret;
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r8a779f0_eth_serdes_write32(channel->addr, 0x0148, 0x180, 0x0101);
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ret = r8a779f0_eth_serdes_reg_wait(channel, 0x0148, 0x0180, BIT(0), 0);
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if (ret)
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return ret;
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r8a779f0_eth_serdes_write32(channel->addr, 0x00c4, 0x180, 0x1310);
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r8a779f0_eth_serdes_write32(channel->addr, 0x00d8, 0x180, 0x1800);
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r8a779f0_eth_serdes_write32(channel->addr, 0x00dc, 0x180, 0x0000);
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r8a779f0_eth_serdes_write32(channel->addr, 0x001c, 0x300, 0x0001);
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r8a779f0_eth_serdes_write32(channel->addr, 0x0000, 0x380, 0x2100);
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ret = r8a779f0_eth_serdes_reg_wait(channel, 0x0000, 0x0380, BIT(8), 0);
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if (ret)
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return ret;
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if (channel->speed == 1000)
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r8a779f0_eth_serdes_write32(channel->addr, 0x0000, 0x1f00, 0x0140);
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else if (channel->speed == 100)
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r8a779f0_eth_serdes_write32(channel->addr, 0x0000, 0x1f00, 0x2100);
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/* For AN_ON */
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r8a779f0_eth_serdes_write32(channel->addr, 0x0004, 0x1f80, 0x0005);
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r8a779f0_eth_serdes_write32(channel->addr, 0x0028, 0x1f80, 0x07a1);
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r8a779f0_eth_serdes_write32(channel->addr, 0x0000, 0x1f80, 0x0208);
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break;
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default:
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return -EOPNOTSUPP;
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}
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return 0;
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}
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static int
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r8a779f0_eth_serdes_chan_speed(struct r8a779f0_eth_serdes_channel *channel)
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{
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int ret;
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switch (channel->phy_interface) {
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case PHY_INTERFACE_MODE_SGMII:
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/* For AN_ON */
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if (channel->speed == 1000)
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r8a779f0_eth_serdes_write32(channel->addr, 0x0000, 0x1f00, 0x1140);
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else if (channel->speed == 100)
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r8a779f0_eth_serdes_write32(channel->addr, 0x0000, 0x1f00, 0x3100);
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ret = r8a779f0_eth_serdes_reg_wait(channel, 0x0008, 0x1f80, BIT(0), 1);
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if (ret)
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return ret;
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r8a779f0_eth_serdes_write32(channel->addr, 0x0008, 0x1f80, 0x0000);
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break;
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default:
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return -EOPNOTSUPP;
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}
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return 0;
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}
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static int r8a779f0_eth_serdes_monitor_linkup(struct r8a779f0_eth_serdes_channel *channel)
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{
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int i, ret;
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for (i = 0; i < R8A779F0_ETH_SERDES_NUM_RETRY_LINKUP; i++) {
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ret = r8a779f0_eth_serdes_reg_wait(channel, 0x0004, 0x300,
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BIT(2), BIT(2));
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if (!ret)
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break;
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/* restart */
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r8a779f0_eth_serdes_write32(channel->addr, 0x0144, 0x180, 0x0100);
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udelay(1);
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r8a779f0_eth_serdes_write32(channel->addr, 0x0144, 0x180, 0x0000);
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}
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return ret;
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}
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static int r8a779f0_eth_serdes_hw_init(struct r8a779f0_eth_serdes_channel *channel)
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{
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struct r8a779f0_eth_serdes_drv_data *dd = channel->dd;
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int i, ret;
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if (dd->initialized)
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return 0;
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ret = r8a779f0_eth_serdes_common_init_ram(dd);
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if (ret)
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return ret;
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for (i = 0; i < R8A779F0_ETH_SERDES_NUM; i++) {
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ret = r8a779f0_eth_serdes_reg_wait(&dd->channel[i], 0x0000,
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0x300, BIT(15), 0);
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if (ret)
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return ret;
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}
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for (i = 0; i < R8A779F0_ETH_SERDES_NUM; i++)
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r8a779f0_eth_serdes_write32(dd->channel[i].addr, 0x03d4, 0x380, 0x0443);
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ret = r8a779f0_eth_serdes_common_setting(channel);
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if (ret)
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return ret;
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for (i = 0; i < R8A779F0_ETH_SERDES_NUM; i++)
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r8a779f0_eth_serdes_write32(dd->channel[i].addr, 0x03d0, 0x380, 0x0001);
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r8a779f0_eth_serdes_write32(dd->addr, 0x0000, 0x380, 0x8000);
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ret = r8a779f0_eth_serdes_common_init_ram(dd);
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if (ret)
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return ret;
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ret = r8a779f0_eth_serdes_reg_wait(&dd->channel[0], 0x0000, 0x380, BIT(15), 0);
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if (ret)
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return ret;
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for (i = 0; i < R8A779F0_ETH_SERDES_NUM; i++) {
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ret = r8a779f0_eth_serdes_chan_setting(&dd->channel[i]);
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if (ret)
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return ret;
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}
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for (i = 0; i < R8A779F0_ETH_SERDES_NUM; i++) {
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ret = r8a779f0_eth_serdes_chan_speed(&dd->channel[i]);
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if (ret)
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return ret;
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}
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for (i = 0; i < R8A779F0_ETH_SERDES_NUM; i++)
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r8a779f0_eth_serdes_write32(dd->channel[i].addr, 0x03c0, 0x380, 0x0000);
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for (i = 0; i < R8A779F0_ETH_SERDES_NUM; i++)
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r8a779f0_eth_serdes_write32(dd->channel[i].addr, 0x03d0, 0x380, 0x0000);
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for (i = 0; i < R8A779F0_ETH_SERDES_NUM; i++) {
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ret = r8a779f0_eth_serdes_monitor_linkup(&dd->channel[i]);
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if (ret)
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return ret;
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}
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return 0;
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}
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static int r8a779f0_eth_serdes_init(struct phy *p)
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{
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struct r8a779f0_eth_serdes_channel *channel = phy_get_drvdata(p);
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int i, ret;
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for (i = 0; i < R8A779F0_ETH_SERDES_NUM_RETRY_INIT; i++) {
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ret = r8a779f0_eth_serdes_hw_init(channel);
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if (!ret) {
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channel->dd->initialized = true;
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break;
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}
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usleep_range(1000, 2000);
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}
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return ret;
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}
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static int r8a779f0_eth_serdes_set_mode(struct phy *p, enum phy_mode mode,
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int submode)
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{
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struct r8a779f0_eth_serdes_channel *channel = phy_get_drvdata(p);
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if (mode != PHY_MODE_ETHERNET)
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return -EOPNOTSUPP;
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switch (submode) {
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case PHY_INTERFACE_MODE_GMII:
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case PHY_INTERFACE_MODE_SGMII:
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case PHY_INTERFACE_MODE_USXGMII:
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channel->phy_interface = submode;
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return 0;
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default:
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return -EOPNOTSUPP;
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}
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}
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static int r8a779f0_eth_serdes_set_speed(struct phy *p, int speed)
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{
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struct r8a779f0_eth_serdes_channel *channel = phy_get_drvdata(p);
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channel->speed = speed;
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return 0;
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}
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static const struct phy_ops r8a779f0_eth_serdes_ops = {
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.init = r8a779f0_eth_serdes_init,
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.set_mode = r8a779f0_eth_serdes_set_mode,
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.set_speed = r8a779f0_eth_serdes_set_speed,
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};
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static struct phy *r8a779f0_eth_serdes_xlate(struct device *dev,
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struct of_phandle_args *args)
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{
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struct r8a779f0_eth_serdes_drv_data *dd = dev_get_drvdata(dev);
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if (args->args[0] >= R8A779F0_ETH_SERDES_NUM)
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return ERR_PTR(-ENODEV);
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return dd->channel[args->args[0]].phy;
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}
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static const struct of_device_id r8a779f0_eth_serdes_of_table[] = {
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{ .compatible = "renesas,r8a779f0-ether-serdes", },
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{ }
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};
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MODULE_DEVICE_TABLE(of, r8a779f0_eth_serdes_of_table);
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static int r8a779f0_eth_serdes_probe(struct platform_device *pdev)
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{
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struct r8a779f0_eth_serdes_drv_data *dd;
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struct phy_provider *provider;
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struct resource *res;
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int i;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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if (!res) {
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dev_err(&pdev->dev, "invalid resource\n");
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return -EINVAL;
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}
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dd = devm_kzalloc(&pdev->dev, sizeof(*dd), GFP_KERNEL);
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if (!dd)
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return -ENOMEM;
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platform_set_drvdata(pdev, dd);
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dd->pdev = pdev;
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dd->addr = devm_ioremap_resource(&pdev->dev, res);
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if (IS_ERR(dd->addr))
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return PTR_ERR(dd->addr);
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|
||||
dd->reset = devm_reset_control_get(&pdev->dev, NULL);
|
||||
if (IS_ERR(dd->reset))
|
||||
return PTR_ERR(dd->reset);
|
||||
|
||||
reset_control_reset(dd->reset);
|
||||
|
||||
for (i = 0; i < R8A779F0_ETH_SERDES_NUM; i++) {
|
||||
struct r8a779f0_eth_serdes_channel *channel = &dd->channel[i];
|
||||
|
||||
channel->phy = devm_phy_create(&pdev->dev, NULL,
|
||||
&r8a779f0_eth_serdes_ops);
|
||||
if (IS_ERR(channel->phy))
|
||||
return PTR_ERR(channel->phy);
|
||||
channel->addr = dd->addr + R8A779F0_ETH_SERDES_OFFSET * i;
|
||||
channel->dd = dd;
|
||||
channel->index = i;
|
||||
phy_set_drvdata(channel->phy, channel);
|
||||
}
|
||||
|
||||
provider = devm_of_phy_provider_register(&pdev->dev,
|
||||
r8a779f0_eth_serdes_xlate);
|
||||
if (IS_ERR(provider))
|
||||
return PTR_ERR(provider);
|
||||
|
||||
pm_runtime_enable(&pdev->dev);
|
||||
pm_runtime_get_sync(&pdev->dev);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int r8a779f0_eth_serdes_remove(struct platform_device *pdev)
|
||||
{
|
||||
pm_runtime_put(&pdev->dev);
|
||||
pm_runtime_disable(&pdev->dev);
|
||||
|
||||
platform_set_drvdata(pdev, NULL);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct platform_driver r8a779f0_eth_serdes_driver_platform = {
|
||||
.probe = r8a779f0_eth_serdes_probe,
|
||||
.remove = r8a779f0_eth_serdes_remove,
|
||||
.driver = {
|
||||
.name = "r8a779f0_eth_serdes",
|
||||
.of_match_table = r8a779f0_eth_serdes_of_table,
|
||||
}
|
||||
};
|
||||
module_platform_driver(r8a779f0_eth_serdes_driver_platform);
|
||||
MODULE_AUTHOR("Yoshihiro Shimoda");
|
||||
MODULE_DESCRIPTION("Renesas Ethernet SERDES device driver");
|
||||
MODULE_LICENSE("GPL");
|
||||
Loading…
Reference in New Issue
Block a user