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drm/nv50: use correct PRAMIN flush register on original nv50
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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0edeb0c024
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@ -1028,6 +1028,7 @@ extern void nv50_instmem_clear(struct drm_device *, struct nouveau_gpuobj *);
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extern int nv50_instmem_bind(struct drm_device *, struct nouveau_gpuobj *);
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extern int nv50_instmem_unbind(struct drm_device *, struct nouveau_gpuobj *);
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extern void nv50_instmem_flush(struct drm_device *);
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extern void nv84_instmem_flush(struct drm_device *);
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extern void nv50_vm_flush(struct drm_device *, int engine);
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/* nv04_mc.c */
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@ -266,7 +266,10 @@ static int nouveau_init_engine_ptrs(struct drm_device *dev)
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engine->instmem.clear = nv50_instmem_clear;
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engine->instmem.bind = nv50_instmem_bind;
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engine->instmem.unbind = nv50_instmem_unbind;
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engine->instmem.flush = nv50_instmem_flush;
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if (dev_priv->chipset == 0x50)
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engine->instmem.flush = nv50_instmem_flush;
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else
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engine->instmem.flush = nv84_instmem_flush;
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engine->mc.init = nv50_mc_init;
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engine->mc.takedown = nv50_mc_takedown;
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engine->timer.init = nv04_timer_init;
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@ -485,6 +485,14 @@ nv50_instmem_unbind(struct drm_device *dev, struct nouveau_gpuobj *gpuobj)
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void
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nv50_instmem_flush(struct drm_device *dev)
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{
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nv_wr32(dev, 0x00330c, 0x00000001);
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if (!nv_wait(0x00330c, 0x00000001, 0x00000000))
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NV_ERROR(dev, "PRAMIN flush timeout\n");
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}
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void
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nv84_instmem_flush(struct drm_device *dev)
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{
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nv_wr32(dev, 0x070000, 0x00000001);
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if (!nv_wait(0x070000, 0x00000001, 0x00000000))
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