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clk: qcom: msm8960: fix ce3_core clk enable register

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This patch corrects the enable register offset which is actually 0x36cc
instead of 0x36c4

Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Fixes: 5f775498bd ("clk: qcom: Fully support apq8064 global clock control")
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
This commit is contained in:
Srinivas Kandagatla 2016-02-22 11:43:39 +00:00 committed by Stephen Boyd
parent f073cd8a3e
commit 732d691369
1 changed files with 1 additions and 1 deletions
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2
drivers/clk/qcom/gcc-msm8960.c
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@ -2769,7 +2769,7 @@ static struct clk_branch ce3_core_clk = {
.halt_reg = 0x2fdc, .halt_reg = 0x2fdc,
.halt_bit = 5, .halt_bit = 5,
.clkr = { .clkr = {
.enable_reg = 0x36c4, .enable_reg = 0x36cc,
.enable_mask = BIT(4), .enable_mask = BIT(4),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "ce3_core_clk", .name = "ce3_core_clk",