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spi: spi-gxp: Add support for HPE GXP SoCs
The GXP supports 3 separate SPI interfaces to accommodate the system flash, core flash, and other functions. The SPI engine supports variable clock frequency, selectable 3-byte or 4-byte addressing and a configurable x1, x2, and x4 command/address/data modes. The memory buffer for reading and writing ranges between 256 bytes and 8KB. This driver supports access to the core flash and bios part. Signed-off-by: Nick Hawkins <nick.hawkins@hpe.com> Link: https://lore.kernel.org/r/20220728161459.7738-2-nick.hawkins@hpe.com Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Nick Hawkins
Mark Brown
parent
233363aba7
commit
730bc8ba5e
@ -371,6 +371,13 @@ config SPI_FSL_QUADSPI
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This controller does not support generic SPI messages. It only
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supports the high-level SPI memory interface.
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config SPI_GXP
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tristate "GXP SPI driver"
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depends on ARCH_HPE || COMPILE_TEST
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help
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This enables support for the driver for GXP bus attached SPI
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controllers.
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config SPI_HISI_KUNPENG
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tristate "HiSilicon SPI Controller for Kunpeng SoCs"
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depends on (ARM64 && ACPI) || COMPILE_TEST
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@ -57,6 +57,7 @@ obj-$(CONFIG_SPI_FSL_LPSPI) += spi-fsl-lpspi.o
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obj-$(CONFIG_SPI_FSL_QUADSPI) += spi-fsl-qspi.o
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obj-$(CONFIG_SPI_FSL_SPI) += spi-fsl-spi.o
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obj-$(CONFIG_SPI_GPIO) += spi-gpio.o
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obj-$(CONFIG_SPI_GXP) += spi-gxp.o
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obj-$(CONFIG_SPI_HISI_KUNPENG) += spi-hisi-kunpeng.o
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obj-$(CONFIG_SPI_HISI_SFC_V3XX) += spi-hisi-sfc-v3xx.o
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obj-$(CONFIG_SPI_IMG_SPFI) += spi-img-spfi.o
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325
drivers/spi/spi-gxp.c
Normal file
325
drivers/spi/spi-gxp.c
Normal file
@ -0,0 +1,325 @@
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// SPDX-License-Identifier: GPL-2.0=or-later
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/* Copyright (C) 2022 Hewlett-Packard Development Company, L.P. */
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#include <linux/iopoll.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include <linux/spi/spi.h>
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#include <linux/spi/spi-mem.h>
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#define GXP_SPI0_MAX_CHIPSELECT 2
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#define GXP_SPI_SLEEP_TIME 1
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#define GXP_SPI_TIMEOUT (130 * 1000000 / GXP_SPI_SLEEP_TIME)
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#define MANUAL_MODE 0
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#define DIRECT_MODE 1
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#define SPILDAT_LEN 256
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#define OFFSET_SPIMCFG 0x0
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#define OFFSET_SPIMCTRL 0x4
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#define OFFSET_SPICMD 0x5
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#define OFFSET_SPIDCNT 0x6
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#define OFFSET_SPIADDR 0x8
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#define OFFSET_SPIINTSTS 0xc
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#define SPIMCTRL_START 0x01
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#define SPIMCTRL_BUSY 0x02
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#define SPIMCTRL_DIR 0x08
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struct gxp_spi;
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struct gxp_spi_chip {
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struct gxp_spi *spifi;
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u32 cs;
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};
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struct gxp_spi_data {
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u32 max_cs;
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u32 mode_bits;
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};
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struct gxp_spi {
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const struct gxp_spi_data *data;
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void __iomem *reg_base;
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void __iomem *dat_base;
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void __iomem *dir_base;
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struct device *dev;
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struct gxp_spi_chip chips[GXP_SPI0_MAX_CHIPSELECT];
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};
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static void gxp_spi_set_mode(struct gxp_spi *spifi, int mode)
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{
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u8 value;
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void __iomem *reg_base = spifi->reg_base;
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value = readb(reg_base + OFFSET_SPIMCTRL);
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if (mode == MANUAL_MODE) {
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writeb(0x55, reg_base + OFFSET_SPICMD);
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writeb(0xaa, reg_base + OFFSET_SPICMD);
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value &= ~0x30;
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} else {
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value |= 0x30;
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}
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writeb(value, reg_base + OFFSET_SPIMCTRL);
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}
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static int gxp_spi_read_reg(struct gxp_spi_chip *chip, const struct spi_mem_op *op)
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{
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int ret;
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struct gxp_spi *spifi = chip->spifi;
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void __iomem *reg_base = spifi->reg_base;
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u32 value;
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value = readl(reg_base + OFFSET_SPIMCFG);
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value &= ~(1 << 24);
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value |= (chip->cs << 24);
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value &= ~(0x07 << 16);
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value &= ~(0x1f << 19);
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writel(value, reg_base + OFFSET_SPIMCFG);
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writel(0, reg_base + OFFSET_SPIADDR);
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writeb(op->cmd.opcode, reg_base + OFFSET_SPICMD);
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writew(op->data.nbytes, reg_base + OFFSET_SPIDCNT);
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value = readb(reg_base + OFFSET_SPIMCTRL);
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value &= ~SPIMCTRL_DIR;
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value |= SPIMCTRL_START;
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writeb(value, reg_base + OFFSET_SPIMCTRL);
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ret = readb_poll_timeout(reg_base + OFFSET_SPIMCTRL, value,
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!(value & SPIMCTRL_BUSY),
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GXP_SPI_SLEEP_TIME, GXP_SPI_TIMEOUT);
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if (ret) {
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dev_warn(spifi->dev, "read reg busy time out\n");
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return ret;
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}
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memcpy_fromio(op->data.buf.in, spifi->dat_base, op->data.nbytes);
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return ret;
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}
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static int gxp_spi_write_reg(struct gxp_spi_chip *chip, const struct spi_mem_op *op)
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{
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int ret;
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struct gxp_spi *spifi = chip->spifi;
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void __iomem *reg_base = spifi->reg_base;
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u32 value;
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value = readl(reg_base + OFFSET_SPIMCFG);
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value &= ~(1 << 24);
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value |= (chip->cs << 24);
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value &= ~(0x07 << 16);
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value &= ~(0x1f << 19);
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writel(value, reg_base + OFFSET_SPIMCFG);
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writel(0, reg_base + OFFSET_SPIADDR);
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writeb(op->cmd.opcode, reg_base + OFFSET_SPICMD);
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memcpy_toio(spifi->dat_base, op->data.buf.in, op->data.nbytes);
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writew(op->data.nbytes, reg_base + OFFSET_SPIDCNT);
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value = readb(reg_base + OFFSET_SPIMCTRL);
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value |= SPIMCTRL_DIR;
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value |= SPIMCTRL_START;
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writeb(value, reg_base + OFFSET_SPIMCTRL);
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ret = readb_poll_timeout(reg_base + OFFSET_SPIMCTRL, value,
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!(value & SPIMCTRL_BUSY),
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GXP_SPI_SLEEP_TIME, GXP_SPI_TIMEOUT);
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if (ret)
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dev_warn(spifi->dev, "write reg busy time out\n");
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return ret;
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}
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static ssize_t gxp_spi_read(struct gxp_spi_chip *chip, const struct spi_mem_op *op)
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{
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struct gxp_spi *spifi = chip->spifi;
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u32 offset = op->addr.val;
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if (chip->cs == 0)
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offset += 0x4000000;
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memcpy_fromio(op->data.buf.in, spifi->dir_base + offset, op->data.nbytes);
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return 0;
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}
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static ssize_t gxp_spi_write(struct gxp_spi_chip *chip, const struct spi_mem_op *op)
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{
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struct gxp_spi *spifi = chip->spifi;
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void __iomem *reg_base = spifi->reg_base;
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u32 write_len;
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u32 value;
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int ret;
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write_len = op->data.nbytes;
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if (write_len > SPILDAT_LEN)
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write_len = SPILDAT_LEN;
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value = readl(reg_base + OFFSET_SPIMCFG);
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value &= ~(1 << 24);
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value |= (chip->cs << 24);
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value &= ~(0x07 << 16);
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value |= (op->addr.nbytes << 16);
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value &= ~(0x1f << 19);
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writel(value, reg_base + OFFSET_SPIMCFG);
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writel(op->addr.val, reg_base + OFFSET_SPIADDR);
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writeb(op->cmd.opcode, reg_base + OFFSET_SPICMD);
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writew(write_len, reg_base + OFFSET_SPIDCNT);
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memcpy_toio(spifi->dat_base, op->data.buf.in, write_len);
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value = readb(reg_base + OFFSET_SPIMCTRL);
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value |= SPIMCTRL_DIR;
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value |= SPIMCTRL_START;
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writeb(value, reg_base + OFFSET_SPIMCTRL);
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ret = readb_poll_timeout(reg_base + OFFSET_SPIMCTRL, value,
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!(value & SPIMCTRL_BUSY),
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GXP_SPI_SLEEP_TIME, GXP_SPI_TIMEOUT);
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if (ret) {
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dev_warn(spifi->dev, "write busy time out\n");
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return ret;
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}
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return write_len;
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}
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static int do_gxp_exec_mem_op(struct spi_mem *mem, const struct spi_mem_op *op)
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{
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struct gxp_spi *spifi = spi_controller_get_devdata(mem->spi->master);
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struct gxp_spi_chip *chip = &spifi->chips[mem->spi->chip_select];
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int ret;
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if (op->data.dir == SPI_MEM_DATA_IN) {
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if (!op->addr.nbytes)
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ret = gxp_spi_read_reg(chip, op);
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else
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ret = gxp_spi_read(chip, op);
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} else {
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if (!op->addr.nbytes)
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ret = gxp_spi_write_reg(chip, op);
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else
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ret = gxp_spi_write(chip, op);
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}
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return ret;
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}
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static int gxp_exec_mem_op(struct spi_mem *mem, const struct spi_mem_op *op)
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{
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int ret;
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ret = do_gxp_exec_mem_op(mem, op);
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if (ret)
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dev_err(&mem->spi->dev, "operation failed: %d", ret);
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return ret;
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}
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static const struct spi_controller_mem_ops gxp_spi_mem_ops = {
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.exec_op = gxp_exec_mem_op,
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};
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static int gxp_spi_setup(struct spi_device *spi)
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{
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struct gxp_spi *spifi = spi_controller_get_devdata(spi->master);
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unsigned int cs = spi->chip_select;
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struct gxp_spi_chip *chip = &spifi->chips[cs];
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chip->spifi = spifi;
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chip->cs = cs;
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gxp_spi_set_mode(spifi, MANUAL_MODE);
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return 0;
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}
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static int gxp_spifi_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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const struct gxp_spi_data *data;
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struct spi_controller *ctlr;
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struct gxp_spi *spifi;
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struct resource *res;
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int ret;
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data = of_device_get_match_data(&pdev->dev);
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ctlr = devm_spi_alloc_master(dev, sizeof(*spifi));
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if (!ctlr)
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return -ENOMEM;
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spifi = spi_controller_get_devdata(ctlr);
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platform_set_drvdata(pdev, spifi);
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spifi->data = data;
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spifi->dev = dev;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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spifi->reg_base = devm_ioremap_resource(&pdev->dev, res);
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if (IS_ERR(spifi->reg_base))
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return PTR_ERR(spifi->reg_base);
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res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
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spifi->dat_base = devm_ioremap_resource(&pdev->dev, res);
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if (IS_ERR(spifi->dat_base))
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return PTR_ERR(spifi->dat_base);
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res = platform_get_resource(pdev, IORESOURCE_MEM, 2);
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spifi->dir_base = devm_ioremap_resource(&pdev->dev, res);
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if (IS_ERR(spifi->dir_base))
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return PTR_ERR(spifi->dir_base);
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ctlr->mode_bits = data->mode_bits;
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ctlr->bus_num = pdev->id;
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ctlr->mem_ops = &gxp_spi_mem_ops;
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ctlr->setup = gxp_spi_setup;
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ctlr->num_chipselect = data->max_cs;
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ctlr->dev.of_node = dev->of_node;
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ret = devm_spi_register_controller(dev, ctlr);
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if (ret) {
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return dev_err_probe(&pdev->dev, ret,
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"failed to register spi controller\n");
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}
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return 0;
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}
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static const struct gxp_spi_data gxp_spifi_data = {
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.max_cs = 2,
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.mode_bits = 0,
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};
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static const struct of_device_id gxp_spifi_match[] = {
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{.compatible = "hpe,gxp-spifi", .data = &gxp_spifi_data },
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{ /* null */ }
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};
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MODULE_DEVICE_TABLE(of, gxp_spifi_match);
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static struct platform_driver gxp_spifi_driver = {
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.probe = gxp_spifi_probe,
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.driver = {
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.name = "gxp-spifi",
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.of_match_table = gxp_spifi_match,
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},
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};
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module_platform_driver(gxp_spifi_driver);
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MODULE_DESCRIPTION("HPE GXP SPI Flash Interface driver");
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MODULE_AUTHOR("Nick Hawkins <nick.hawkins@hpe.com>");
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MODULE_LICENSE("GPL");
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