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pinctrl: pinctrl-cy8c95x0: Fix regcache

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The size of the mux stride was off by one, which could result in
invalid pin configuration on the device side or invalid state
readings on the software side.

While on it also update the code and:
- Increase the mux stride size to 16
- Align the virtual muxed regmap range to 16
- Start the regmap window at the selector
- Mark reserved registers as not-readable

Fixes: 8670de9fae ("pinctrl: cy8c95x0: Use regmap ranges")
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reported-by: Andy Shevchenko <andy@kernel.org>
Reviewed-by: Andy Shevchenko <andy@kernel.org>
Link: https://lore.kernel.org/20240902072859.583490-1-patrick.rudolph@9elements.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This commit is contained in:
Patrick Rudolph 2024-09-02 09:28:58 +02:00 committed by Linus Walleij
parent d7c9ec3b07
commit 71e4001a04
1 changed files with 9 additions and 5 deletions
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14
drivers/pinctrl/pinctrl-cy8c95x0.c
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@ -62,11 +62,11 @@
#define MAX_BANK 8 #define MAX_BANK 8
#define BANK_SZ 8 #define BANK_SZ 8
#define MAX_LINE (MAX_BANK * BANK_SZ) #define MAX_LINE (MAX_BANK * BANK_SZ)
#define MUXED_STRIDE (CY8C95X0_DRV_HIZ - CY8C95X0_INTMASK) #define MUXED_STRIDE 16
#define CY8C95X0_GPIO_MASK GENMASK(7, 0) #define CY8C95X0_GPIO_MASK GENMASK(7, 0)
#define CY8C95X0_VIRTUAL (CY8C95X0_COMMAND + 1) #define CY8C95X0_VIRTUAL 0x40
#define CY8C95X0_MUX_REGMAP_TO_OFFSET(x, p) \ #define CY8C95X0_MUX_REGMAP_TO_OFFSET(x, p) \
(CY8C95X0_VIRTUAL + (x) - CY8C95X0_INTMASK + (p) * MUXED_STRIDE) (CY8C95X0_VIRTUAL + (x) - CY8C95X0_PORTSEL + (p) * MUXED_STRIDE)
static const struct i2c_device_id cy8c95x0_id[] = { static const struct i2c_device_id cy8c95x0_id[] = {
{ "cy8c9520", 20, }, { "cy8c9520", 20, },
@ -329,7 +329,11 @@ static int cypress_get_pin_mask(struct cy8c95x0_pinctrl *chip, unsigned int pin)
static bool cy8c95x0_readable_register(struct device *dev, unsigned int reg) static bool cy8c95x0_readable_register(struct device *dev, unsigned int reg)
{ {
if (reg >= CY8C95X0_VIRTUAL) /*
* Only 12 registers are present per port (see Table 6 in the
* datasheet).
*/
if (reg >= CY8C95X0_VIRTUAL && (reg % MUXED_STRIDE) < 12)
return true; return true;
switch (reg) { switch (reg) {
@ -444,7 +448,7 @@ static const struct regmap_range_cfg cy8c95x0_ranges[] = {
.selector_reg = CY8C95X0_PORTSEL, .selector_reg = CY8C95X0_PORTSEL,
.selector_mask = 0x07, .selector_mask = 0x07,
.selector_shift = 0x0, .selector_shift = 0x0,
.window_start = CY8C95X0_INTMASK, .window_start = CY8C95X0_PORTSEL,
.window_len = MUXED_STRIDE, .window_len = MUXED_STRIDE,
} }
}; };