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Staging: rtl8188eu: Fixed spaces before tabs and before close parentheses
Fixed all space before tab warnings and space before close parenthesis errors on rtl8188e_spec.h Signed-off-by: Tim Jester-Pfadt <t.jp@gmx.de> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Tim Jester-Pfadt
Greg Kroah-Hartman
parent
beb3d16671
commit
7194ea8773
@ -68,7 +68,7 @@
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#define DISABLE_TRXPKT_BUF_ACCESS 0x0
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/* 0x0000h ~ 0x00FFh System Configuration */
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/* 0x0000h ~ 0x00FFh System Configuration */
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#define REG_SYS_ISO_CTRL 0x0000
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#define REG_SYS_FUNC_EN 0x0002
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#define REG_APS_FSMCO 0x0004
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@ -142,7 +142,7 @@
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#define REG_MAC_PHY_CTRL_NORMAL 0x00f8
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/* 0x0100h ~ 0x01FFh MACTOP General Configuration */
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/* 0x0100h ~ 0x01FFh MACTOP General Configuration */
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#define REG_CR 0x0100
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#define REG_PBP 0x0104
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#define REG_PKT_BUFF_ACCESS_CTRL 0x0106
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@ -188,7 +188,7 @@
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#define REG_LLT_INIT 0x01E0
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/* 0x0200h ~ 0x027Fh TXDMA Configuration */
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/* 0x0200h ~ 0x027Fh TXDMA Configuration */
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#define REG_RQPN 0x0200
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#define REG_FIFOPAGE 0x0204
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#define REG_TDECTRL 0x0208
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@ -196,12 +196,12 @@
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#define REG_TXDMA_STATUS 0x0210
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#define REG_RQPN_NPQ 0x0214
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/* 0x0280h ~ 0x02FFh RXDMA Configuration */
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/* 0x0280h ~ 0x02FFh RXDMA Configuration */
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#define REG_RXDMA_AGG_PG_TH 0x0280
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#define REG_RXPKT_NUM 0x0284
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#define REG_RXDMA_STATUS 0x0288
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/* 0x0300h ~ 0x03FFh PCIe */
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/* 0x0300h ~ 0x03FFh PCIe */
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#define REG_PCIE_CTRL_REG 0x0300
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#define REG_INT_MIG 0x0304 /* Interrupt Migration */
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#define REG_BCNQ_DESA 0x0308 /* TX Beacon Descr Address */
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@ -222,7 +222,7 @@
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#define REG_PCIE_HISR 0x03A0
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/* spec version 11 */
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/* 0x0400h ~ 0x047Fh Protocol Configuration */
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/* 0x0400h ~ 0x047Fh Protocol Configuration */
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#define REG_VOQ_INFORMATION 0x0400
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#define REG_VIQ_INFORMATION 0x0404
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#define REG_BEQ_INFORMATION 0x0408
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@ -276,7 +276,7 @@
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#define REG_TX_RPT_TIME 0x04F0 /* 2 byte */
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#define REG_DUMMY 0x04FC
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/* 0x0500h ~ 0x05FFh EDCA Configuration */
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/* 0x0500h ~ 0x05FFh EDCA Configuration */
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#define REG_EDCA_VO_PARAM 0x0500
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#define REG_EDCA_VI_PARAM 0x0504
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#define REG_EDCA_BE_PARAM 0x0508
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@ -294,16 +294,16 @@
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#define REG_DIS_TXREQ_CLR 0x0523
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#define REG_RD_CTRL 0x0524
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/* Format for offset 540h-542h: */
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/* [3:0]: TBTT prohibit setup in unit of 32us. The time for HW getting
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/* [3:0]: TBTT prohibit setup in unit of 32us. The time for HW getting
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* beacon content before TBTT. */
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/* [7:4]: Reserved. */
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/* [19:8]: TBTT prohibit hold in unit of 32us. The time for HW holding
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/* [7:4]: Reserved. */
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/* [19:8]: TBTT prohibit hold in unit of 32us. The time for HW holding
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* to send the beacon packet. */
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/* [23:20]: Reserved */
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/* [23:20]: Reserved */
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/* Description: */
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/* | */
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/* | */
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/* |<--Setup--|--Hold------------>| */
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/* --------------|---------------------- */
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/* --------------|---------------------- */
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/* | */
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/* TBTT */
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/* Note: We cannot update beacon content to HW or send any AC packets during
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@ -335,7 +335,7 @@
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#define REG_FW_RESET_TSF_CNT_0 0x05FD
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#define REG_FW_BCN_DIS_CNT 0x05FE
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/* 0x0600h ~ 0x07FFh WMAC Configuration */
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/* 0x0600h ~ 0x07FFh WMAC Configuration */
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#define REG_APSD_CTRL 0x0600
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#define REG_BWOPMODE 0x0603
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#define REG_TCR 0x0604
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@ -382,7 +382,7 @@
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#define _RXERR_RPT_SEL(type) ((type) << 28)
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/* Note: */
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/* The NAV upper value is very important to WiFi 11n 5.2.3 NAV test.
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/* The NAV upper value is very important to WiFi 11n 5.2.3 NAV test.
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* The default value is always too small, but the WiFi TestPlan test
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* by 25,000 microseconds of NAV through sending CTS in the air.
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* We must update this value greater than 25,000 microseconds to pass
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@ -422,7 +422,7 @@
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#define REG_MACID1 0x0700
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#define REG_BSSID1 0x0708
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/* 0xFE00h ~ 0xFE55h USB Configuration */
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/* 0xFE00h ~ 0xFE55h USB Configuration */
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#define REG_USB_INFO 0xFE17
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#define REG_USB_SPECIAL_OPTION 0xFE55
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#define REG_USB_DMA_AGG_TO 0xFE5B
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@ -689,13 +689,13 @@ Current IOREG MAP
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0x0600h ~ 0x07FFh WMAC Configuration (512 Bytes)
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0x2000h ~ 0x3FFFh 8051 FW Download Region (8196 Bytes)
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*/
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/* 8192C (TXPAUSE) transmission pause (Offset 0x522, 8 bits) */
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/* 8192C (TXPAUSE) transmission pause (Offset 0x522, 8 bits) */
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/* Note: */
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/* The bits of stopping AC(VO/VI/BE/BK) queue in datasheet
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/* The bits of stopping AC(VO/VI/BE/BK) queue in datasheet
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* RTL8192S/RTL8192C are wrong, */
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/* the correct arragement is VO - Bit0, VI - Bit1, BE - Bit2,
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/* the correct arragement is VO - Bit0, VI - Bit1, BE - Bit2,
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* and BK - Bit3. */
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/* 8723 and 88E may be not correct either in the earlier version. */
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/* 8723 and 88E may be not correct either in the earlier version. */
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#define StopBecon BIT6
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#define StopHigh BIT5
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#define StopMgt BIT4
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@ -733,7 +733,7 @@ Current IOREG MAP
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#define RCR_MXDMA_OFFSET 8
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#define RCR_FIFO_OFFSET 13
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/* 0xFE00h ~ 0xFE55h USB Configuration */
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/* 0xFE00h ~ 0xFE55h USB Configuration */
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#define REG_USB_INFO 0xFE17
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#define REG_USB_SPECIAL_OPTION 0xFE55
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#define REG_USB_DMA_AGG_TO 0xFE5B
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@ -743,7 +743,7 @@ Current IOREG MAP
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#define REG_USB_HRPWM 0xFE58
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#define REG_USB_HCPWM 0xFE57
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/* 8192C Regsiter Bit and Content definition */
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/* 0x0000h ~ 0x00FFh System Configuration */
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/* 0x0000h ~ 0x00FFh System Configuration */
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/* 2 SYS_ISO_CTRL */
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#define ISO_MD2PP BIT(0)
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@ -914,7 +914,7 @@ Current IOREG MAP
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/* 2SYS_CFG */
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#define RTL_ID BIT(23) /* TestChip ID, 1:Test(RLE); 0:MP(RL) */
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/* 0x0100h ~ 0x01FFh MACTOP General Configuration */
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/* 0x0100h ~ 0x01FFh MACTOP General Configuration */
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/* 2 Function Enable Registers */
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/* 2 CR */
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@ -975,9 +975,9 @@ Current IOREG MAP
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#define _TXDMA_HIQ_MAP(x) (((x)&0x3) << 14)
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#define _TXDMA_MGQ_MAP(x) (((x)&0x3) << 12)
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#define _TXDMA_BKQ_MAP(x) (((x)&0x3) << 10)
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#define _TXDMA_BEQ_MAP(x) (((x)&0x3) << 8 )
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#define _TXDMA_VIQ_MAP(x) (((x)&0x3) << 6 )
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#define _TXDMA_VOQ_MAP(x) (((x)&0x3) << 4 )
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#define _TXDMA_BEQ_MAP(x) (((x)&0x3) << 8)
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#define _TXDMA_VIQ_MAP(x) (((x)&0x3) << 6)
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#define _TXDMA_VOQ_MAP(x) (((x)&0x3) << 4)
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#define QUEUE_LOW 1
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#define QUEUE_NORMAL 2
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@ -995,7 +995,7 @@ Current IOREG MAP
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#define _LLT_OP(x) (((x) & 0x3) << 30)
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#define _LLT_OP_VALUE(x) (((x) >> 30) & 0x3)
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/* 0x0200h ~ 0x027Fh TXDMA Configuration */
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/* 0x0200h ~ 0x027Fh TXDMA Configuration */
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/* 2RQPN */
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#define _HPQ(x) ((x) & 0xFF)
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#define _LPQ(x) (((x) & 0xFF) << 8)
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@ -1019,7 +1019,7 @@ Current IOREG MAP
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/* 2 TXDMA_OFFSET_CHK */
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#define DROP_DATA_EN BIT(9)
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/* 0x0280h ~ 0x028Bh RX DMA Configuration */
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/* 0x0280h ~ 0x028Bh RX DMA Configuration */
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/* REG_RXDMA_CONTROL, 0x0286h */
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@ -1028,7 +1028,7 @@ Current IOREG MAP
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#define RXDMA_IDLE BIT(17)
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#define RW_RELEASE_EN BIT(18)
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/* 0x0400h ~ 0x047Fh Protocol Configuration */
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/* 0x0400h ~ 0x047Fh Protocol Configuration */
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/* 2 FWHW_TXQ_CTRL */
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#define EN_AMPDU_RTY_NEW BIT(7)
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@ -1040,7 +1040,7 @@ Current IOREG MAP
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#define RETRY_LIMIT_SHORT_SHIFT 8
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#define RETRY_LIMIT_LONG_SHIFT 0
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/* 0x0500h ~ 0x05FFh EDCA Configuration */
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/* 0x0500h ~ 0x05FFh EDCA Configuration */
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/* 2 EDCA setting */
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#define AC_PARAM_TXOP_LIMIT_OFFSET 16
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@ -1071,7 +1071,7 @@ Current IOREG MAP
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#define AcmHw_ViqStatus BIT(5)
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#define AcmHw_VoqStatus BIT(6)
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/* 0x0600h ~ 0x07FFh WMAC Configuration */
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/* 0x0600h ~ 0x07FFh WMAC Configuration */
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/* 2APSD_CTRL */
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#define APSDOFF BIT(6)
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#define APSDOFF_STATUS BIT(7)
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@ -1128,7 +1128,7 @@ Current IOREG MAP
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#define SCR_TXBCUSEDK BIT(6) /* Force Tx Bcast pkt Use Default Key */
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#define SCR_RXBCUSEDK BIT(7) /* Force Rx Bcast pkt Use Default Key */
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/* RTL8188E SDIO Configuration */
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/* RTL8188E SDIO Configuration */
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/* I/O bus domain address mapping */
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#define SDIO_LOCAL_BASE 0x10250000
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@ -1264,7 +1264,7 @@ Current IOREG MAP
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#define SDIO_TX_FREE_PG_QUEUE 4
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#define SDIO_TX_FIFO_PAGE_SZ 128
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/* 0xFE00h ~ 0xFE55h USB Configuration */
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/* 0xFE00h ~ 0xFE55h USB Configuration */
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/* 2 USB Information (0xFE17) */
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#define USB_IS_HIGH_SPEED 0
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@ -1331,7 +1331,7 @@ Current IOREG MAP
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/* 8192C EEPROM/EFUSE share register definition. */
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/* EEPROM/Efuse PG Offset for 88EE/88EU/88ES */
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/* EEPROM/Efuse PG Offset for 88EE/88EU/88ES */
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#define EEPROM_TX_PWR_INX_88E 0x10
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#define EEPROM_ChannelPlan_88E 0xB8
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@ -1362,7 +1362,7 @@ Current IOREG MAP
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/* RTL88ES */
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#define EEPROM_MAC_ADDR_88ES 0x11A
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/* EEPROM/Efuse Value Type */
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/* EEPROM/Efuse Value Type */
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#define EETYPE_TX_PWR 0x0
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/* Default Value for EEPROM or EFUSE!!! */
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