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i7300_edac: convert driver to use the new edac ABI
The legacy edac ABI is going to be removed. Port the driver to use and benefit from the new API functionality. Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
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@ -464,17 +464,14 @@ static void i7300_process_fbd_error(struct mem_ctl_info *mci)
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FERR_FAT_FBD, error_reg);
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snprintf(pvt->tmp_prt_buffer, PAGE_SIZE,
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"FATAL (Branch=%d DRAM-Bank=%d %s "
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"RAS=%d CAS=%d Err=0x%lx (%s))",
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branch, bank,
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is_wr ? "RDWR" : "RD",
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ras, cas,
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errors, specific);
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"Bank=%d RAS=%d CAS=%d Err=0x%lx (%s))",
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bank, ras, cas, errors, specific);
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edac_mc_handle_error(HW_EVENT_ERR_FATAL, mci, 0, 0, 0,
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branch, -1, rank,
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is_wr ? "Write error" : "Read error",
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pvt->tmp_prt_buffer, NULL);
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/* Call the helper to output message */
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edac_mc_handle_fbd_ue(mci, rank, branch << 1,
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(branch << 1) + 1,
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pvt->tmp_prt_buffer);
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}
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/* read in the 1st NON-FATAL error register */
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@ -513,23 +510,14 @@ static void i7300_process_fbd_error(struct mem_ctl_info *mci)
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/* Form out message */
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snprintf(pvt->tmp_prt_buffer, PAGE_SIZE,
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"Corrected error (Branch=%d, Channel %d), "
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" DRAM-Bank=%d %s "
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"RAS=%d CAS=%d, CE Err=0x%lx, Syndrome=0x%08x(%s))",
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branch, channel,
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bank,
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is_wr ? "RDWR" : "RD",
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ras, cas,
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errors, syndrome, specific);
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"DRAM-Bank=%d RAS=%d CAS=%d, Err=0x%lx (%s))",
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bank, ras, cas, errors, specific);
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/*
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* Call the helper to output message
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* NOTE: Errors are reported per-branch, and not per-channel
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* Currently, we don't know how to identify the right
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* channel.
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*/
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edac_mc_handle_fbd_ce(mci, rank, channel,
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pvt->tmp_prt_buffer);
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edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, 0, 0,
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syndrome,
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branch >> 1, channel % 2, rank,
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is_wr ? "Write error" : "Read error",
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pvt->tmp_prt_buffer, NULL);
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}
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return;
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}
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@ -807,9 +795,10 @@ static int i7300_init_csrows(struct mem_ctl_info *mci)
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for (ch = 0; ch < MAX_CH_PER_BRANCH; ch++) {
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int channel = to_channel(ch, branch);
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dinfo = &pvt->dimm_info[slot][channel];
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dimm = EDAC_DIMM_PTR(mci->layers, mci->dimms,
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mci->n_layers, branch, ch, slot);
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dimm = mci->csrows[slot].channels[branch * MAX_CH_PER_BRANCH + ch].dimm;
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dinfo = &pvt->dimm_info[slot][channel];
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mtr = decode_mtr(pvt, slot, ch, branch,
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dinfo, dimm);
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@ -1034,10 +1023,8 @@ static int __devinit i7300_init_one(struct pci_dev *pdev,
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const struct pci_device_id *id)
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{
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struct mem_ctl_info *mci;
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struct edac_mc_layer layers[3];
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struct i7300_pvt *pvt;
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int num_channels;
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int num_dimms_per_channel;
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int num_csrows;
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int rc;
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/* wake up device */
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@ -1054,22 +1041,17 @@ static int __devinit i7300_init_one(struct pci_dev *pdev,
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if (PCI_FUNC(pdev->devfn) != 0)
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return -ENODEV;
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/* As we don't have a motherboard identification routine to determine
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* actual number of slots/dimms per channel, we thus utilize the
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* resource as specified by the chipset. Thus, we might have
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* have more DIMMs per channel than actually on the mobo, but this
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* allows the driver to support up to the chipset max, without
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* some fancy mobo determination.
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*/
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num_dimms_per_channel = MAX_SLOTS;
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num_channels = MAX_CHANNELS;
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num_csrows = MAX_SLOTS * MAX_CHANNELS;
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debugf0("MC: %s(): Number of - Channels= %d DIMMS= %d CSROWS= %d\n",
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__func__, num_channels, num_dimms_per_channel, num_csrows);
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/* allocate a new MC control structure */
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mci = edac_mc_alloc(sizeof(*pvt), num_csrows, num_channels, 0);
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layers[0].type = EDAC_MC_LAYER_BRANCH;
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layers[0].size = MAX_BRANCHES;
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layers[0].is_virt_csrow = false;
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layers[1].type = EDAC_MC_LAYER_CHANNEL;
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layers[1].size = MAX_CH_PER_BRANCH;
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layers[1].is_virt_csrow = true;
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layers[2].type = EDAC_MC_LAYER_SLOT;
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layers[2].size = MAX_SLOTS;
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layers[2].is_virt_csrow = true;
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mci = new_edac_mc_alloc(0, ARRAY_SIZE(layers), layers, sizeof(*pvt));
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if (mci == NULL)
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return -ENOMEM;
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