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ioat: add some dev_dbg() calls
Provide some output for debugging the driver. Signed-off-by: Maciej Sosnowski <maciej.sosnowski@intel.com> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
This commit is contained in:
Dan Williams
parent
38e12f64a1
commit
6df9183a15
@ -134,6 +134,7 @@ static int ioat1_enumerate_channels(struct ioatdma_device *device)
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dma->chancnt = readb(device->reg_base + IOAT_CHANCNT_OFFSET);
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xfercap_scale = readb(device->reg_base + IOAT_XFERCAP_OFFSET);
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xfercap = (xfercap_scale == 0 ? -1 : (1UL << xfercap_scale));
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dev_dbg(dev, "%s: xfercap = %d\n", __func__, xfercap);
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#ifdef CONFIG_I7300_IDLE_IOAT_CHANNEL
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if (i7300_idle_platform_probe(NULL, NULL, 1) == 0)
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@ -167,6 +168,8 @@ __ioat1_dma_memcpy_issue_pending(struct ioat_dma_chan *ioat)
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{
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void __iomem *reg_base = ioat->base.reg_base;
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dev_dbg(to_dev(&ioat->base), "%s: pending: %d\n",
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__func__, ioat->pending);
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ioat->pending = 0;
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writeb(IOAT_CHANCMD_APPEND, reg_base + IOAT1_CHANCMD_OFFSET);
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}
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@ -251,6 +254,7 @@ static void ioat1_reset_channel(struct ioat_dma_chan *ioat)
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if (!ioat->used_desc.prev)
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return;
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dev_dbg(to_dev(chan), "%s\n", __func__);
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chanerr = readl(reg_base + IOAT_CHANERR_OFFSET);
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chansts = (chan->completion_virt->low
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& IOAT_CHANSTS_DMA_TRANSFER_STATUS);
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@ -382,6 +386,7 @@ static dma_cookie_t ioat1_tx_submit(struct dma_async_tx_descriptor *tx)
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cookie = 1;
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c->cookie = cookie;
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tx->cookie = cookie;
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dev_dbg(to_dev(&ioat->base), "%s: cookie: %d\n", __func__, cookie);
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/* write address into NextDescriptor field of last desc in chain */
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first = to_ioat_desc(tx->tx_list.next);
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@ -390,6 +395,8 @@ static dma_cookie_t ioat1_tx_submit(struct dma_async_tx_descriptor *tx)
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wmb();
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chain_tail->hw->next = first->txd.phys;
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list_splice_tail_init(&tx->tx_list, &ioat->used_desc);
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dump_desc_dbg(ioat, chain_tail);
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dump_desc_dbg(ioat, first);
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ioat->pending += desc->tx_cnt;
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if (ioat->pending >= ioat_pending_level)
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@ -429,6 +436,7 @@ ioat_dma_alloc_descriptor(struct ioat_dma_chan *ioat, gfp_t flags)
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desc_sw->txd.tx_submit = ioat1_tx_submit;
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desc_sw->hw = desc;
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desc_sw->txd.phys = phys;
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set_desc_id(desc_sw, -1);
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return desc_sw;
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}
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@ -474,6 +482,7 @@ static int ioat1_dma_alloc_chan_resources(struct dma_chan *c)
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dev_err(to_dev(chan), "Only %d initial descriptors\n", i);
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break;
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}
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set_desc_id(desc, i);
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list_add_tail(&desc->node, &tmp_list);
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}
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spin_lock_bh(&ioat->desc_lock);
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@ -495,6 +504,8 @@ static int ioat1_dma_alloc_chan_resources(struct dma_chan *c)
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tasklet_enable(&chan->cleanup_task);
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ioat1_dma_start_null_desc(ioat); /* give chain to dma device */
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dev_dbg(to_dev(chan), "%s: allocated %d descriptors\n",
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__func__, ioat->desccount);
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return ioat->desccount;
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}
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@ -527,8 +538,10 @@ static void ioat1_dma_free_chan_resources(struct dma_chan *c)
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mdelay(100);
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spin_lock_bh(&ioat->desc_lock);
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list_for_each_entry_safe(desc, _desc,
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&ioat->used_desc, node) {
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list_for_each_entry_safe(desc, _desc, &ioat->used_desc, node) {
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dev_dbg(to_dev(chan), "%s: freeing %d from used list\n",
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__func__, desc_id(desc));
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dump_desc_dbg(ioat, desc);
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in_use_descs++;
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list_del(&desc->node);
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pci_pool_free(ioatdma_device->dma_pool, desc->hw,
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@ -585,7 +598,8 @@ ioat1_dma_get_next_descriptor(struct ioat_dma_chan *ioat)
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return NULL;
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}
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}
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dev_dbg(to_dev(&ioat->base), "%s: allocated: %d\n",
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__func__, desc_id(new));
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prefetch(new->hw);
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return new;
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}
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@ -630,6 +644,7 @@ ioat1_dma_prep_memcpy(struct dma_chan *c, dma_addr_t dma_dest,
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async_tx_ack(&desc->txd);
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next = ioat1_dma_get_next_descriptor(ioat);
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hw->next = next ? next->txd.phys : 0;
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dump_desc_dbg(ioat, desc);
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desc = next;
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} else
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hw->next = 0;
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@ -652,6 +667,7 @@ ioat1_dma_prep_memcpy(struct dma_chan *c, dma_addr_t dma_dest,
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list_splice(&chain, &desc->txd.tx_list);
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hw->ctl_f.int_en = !!(flags & DMA_PREP_INTERRUPT);
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hw->ctl_f.compl_write = 1;
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dump_desc_dbg(ioat, desc);
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return &desc->txd;
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}
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@ -707,6 +723,9 @@ unsigned long ioat_get_current_completion(struct ioat_chan_common *chan)
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phys_complete = chan->completion_virt->low & IOAT_LOW_COMPLETION_MASK;
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#endif
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dev_dbg(to_dev(chan), "%s: phys_complete: %#llx\n", __func__,
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(unsigned long long) phys_complete);
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if ((chan->completion_virt->full
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& IOAT_CHANSTS_DMA_TRANSFER_STATUS) ==
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IOAT_CHANSTS_DMA_TRANSFER_STATUS_HALTED) {
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@ -758,6 +777,8 @@ static void ioat1_cleanup(struct ioat_dma_chan *ioat)
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return;
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}
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dev_dbg(to_dev(chan), "%s: phys_complete: %lx\n",
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__func__, phys_complete);
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list_for_each_entry_safe(desc, _desc, &ioat->used_desc, node) {
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tx = &desc->txd;
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/*
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@ -765,6 +786,7 @@ static void ioat1_cleanup(struct ioat_dma_chan *ioat)
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* due to exceeding xfercap, perhaps. If so, only the
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* last one will have a cookie, and require unmapping.
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*/
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dump_desc_dbg(ioat, desc);
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if (tx->cookie) {
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cookie = tx->cookie;
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ioat_dma_unmap(chan, tx->flags, desc->len, desc->hw);
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@ -848,6 +870,7 @@ static void ioat1_dma_start_null_desc(struct ioat_dma_chan *ioat)
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async_tx_ack(&desc->txd);
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hw->next = 0;
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list_add_tail(&desc->node, &ioat->used_desc);
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dump_desc_dbg(ioat, desc);
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writel(((u64) desc->txd.phys) & 0x00000000FFFFFFFF,
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chan->reg_base + IOAT1_CHAINADDR_OFFSET_LOW);
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@ -173,6 +173,7 @@ ioat_is_complete(struct dma_chan *c, dma_cookie_t cookie,
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* or attached to a transaction list (async_tx.tx_list)
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* @tx_cnt: number of descriptors required to complete the transaction
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* @txd: the generic software descriptor for all engines
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* @id: identifier for debug
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*/
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struct ioat_desc_sw {
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struct ioat_dma_descriptor *hw;
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@ -180,8 +181,35 @@ struct ioat_desc_sw {
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int tx_cnt;
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size_t len;
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struct dma_async_tx_descriptor txd;
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#ifdef DEBUG
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int id;
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#endif
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};
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#ifdef DEBUG
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#define set_desc_id(desc, i) ((desc)->id = (i))
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#define desc_id(desc) ((desc)->id)
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#else
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#define set_desc_id(desc, i)
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#define desc_id(desc) (0)
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#endif
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static inline void
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__dump_desc_dbg(struct ioat_chan_common *chan, struct ioat_dma_descriptor *hw,
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struct dma_async_tx_descriptor *tx, int id)
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{
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struct device *dev = to_dev(chan);
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dev_dbg(dev, "desc[%d]: (%#llx->%#llx) cookie: %d flags: %#x"
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" ctl: %#x (op: %d int_en: %d compl: %d)\n", id,
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(unsigned long long) tx->phys,
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(unsigned long long) hw->next, tx->cookie, tx->flags,
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hw->ctl, hw->ctl_f.op, hw->ctl_f.int_en, hw->ctl_f.compl_write);
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}
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#define dump_desc_dbg(c, d) \
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({ if (d) __dump_desc_dbg(&c->base, d->hw, &d->txd, desc_id(d)); 0; })
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static inline void ioat_set_tcp_copy_break(unsigned long copybreak)
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{
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#ifdef CONFIG_NET_DMA
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@ -54,7 +54,9 @@ static void __ioat2_issue_pending(struct ioat2_dma_chan *ioat)
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/* make descriptor updates globally visible before notifying channel */
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wmb();
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writew(ioat->dmacount, reg_base + IOAT_CHAN_DMACOUNT_OFFSET);
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dev_dbg(to_dev(&ioat->base),
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"%s: head: %#x tail: %#x issued: %#x count: %#x\n",
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__func__, ioat->head, ioat->tail, ioat->issued, ioat->dmacount);
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}
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static void ioat2_issue_pending(struct dma_chan *chan)
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@ -101,6 +103,8 @@ static void __ioat2_start_null_desc(struct ioat2_dma_chan *ioat)
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return;
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}
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dev_dbg(to_dev(&ioat->base), "%s: head: %#x tail: %#x issued: %#x\n",
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__func__, ioat->head, ioat->tail, ioat->issued);
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idx = ioat2_desc_alloc(ioat, 1);
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desc = ioat2_get_ring_ent(ioat, idx);
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@ -118,6 +122,7 @@ static void __ioat2_start_null_desc(struct ioat2_dma_chan *ioat)
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reg_base + IOAT2_CHAINADDR_OFFSET_LOW);
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writel(((u64) desc->txd.phys) >> 32,
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reg_base + IOAT2_CHAINADDR_OFFSET_HIGH);
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dump_desc_dbg(ioat, desc);
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__ioat2_issue_pending(ioat);
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}
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@ -154,6 +159,10 @@ static void ioat2_reset_part2(struct work_struct *work)
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ioat->issued = ioat->tail;
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ioat->dmacount = 0;
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dev_dbg(to_dev(&ioat->base),
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"%s: head: %#x tail: %#x issued: %#x count: %#x\n",
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__func__, ioat->head, ioat->tail, ioat->issued, ioat->dmacount);
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if (ioat2_ring_pending(ioat)) {
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struct ioat_ring_ent *desc;
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@ -221,6 +230,8 @@ static void ioat2_chan_watchdog(struct work_struct *work)
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u16 active;
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int i;
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dev_dbg(&device->pdev->dev, "%s\n", __func__);
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for (i = 0; i < device->common.chancnt; i++) {
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chan = ioat_chan_by_index(device, i);
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ioat = container_of(chan, struct ioat2_dma_chan, base);
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@ -295,11 +306,15 @@ static void ioat2_cleanup(struct ioat2_dma_chan *ioat)
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spin_lock_bh(&ioat->ring_lock);
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dev_dbg(to_dev(chan), "%s: head: %#x tail: %#x issued: %#x\n",
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__func__, ioat->head, ioat->tail, ioat->issued);
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active = ioat2_ring_active(ioat);
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for (i = 0; i < active && !seen_current; i++) {
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prefetch(ioat2_get_ring_ent(ioat, ioat->tail + i + 1));
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desc = ioat2_get_ring_ent(ioat, ioat->tail + i);
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tx = &desc->txd;
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dump_desc_dbg(ioat, desc);
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if (tx->cookie) {
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ioat_dma_unmap(chan, tx->flags, desc->len, desc->hw);
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chan->completed_cookie = tx->cookie;
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@ -348,6 +363,7 @@ static int ioat2_enumerate_channels(struct ioatdma_device *device)
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xfercap_log = readb(device->reg_base + IOAT_XFERCAP_OFFSET);
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if (xfercap_log == 0)
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return 0;
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dev_dbg(dev, "%s: xfercap = %d\n", __func__, 1 << xfercap_log);
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/* FIXME which i/oat version is i7300? */
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#ifdef CONFIG_I7300_IDLE_IOAT_CHANNEL
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@ -381,6 +397,8 @@ static dma_cookie_t ioat2_tx_submit_unlock(struct dma_async_tx_descriptor *tx)
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cookie = 1;
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tx->cookie = cookie;
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c->cookie = cookie;
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dev_dbg(to_dev(&ioat->base), "%s: cookie: %d\n", __func__, cookie);
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ioat2_update_pending(ioat);
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spin_unlock_bh(&ioat->ring_lock);
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@ -480,6 +498,7 @@ static int ioat2_alloc_chan_resources(struct dma_chan *c)
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kfree(ring);
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return -ENOMEM;
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}
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set_desc_id(ring[i], i);
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}
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/* link descs */
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@ -571,12 +590,14 @@ ioat2_dma_prep_memcpy_lock(struct dma_chan *c, dma_addr_t dma_dest,
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len -= copy;
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dst += copy;
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src += copy;
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dump_desc_dbg(ioat, desc);
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}
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desc->txd.flags = flags;
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desc->len = total_len;
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hw->ctl_f.int_en = !!(flags & DMA_PREP_INTERRUPT);
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hw->ctl_f.compl_write = 1;
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dump_desc_dbg(ioat, desc);
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/* we leave the channel locked to ensure in order submission */
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return &desc->txd;
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@ -614,6 +635,7 @@ static void ioat2_free_chan_resources(struct dma_chan *c)
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spin_lock_bh(&ioat->ring_lock);
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descs = ioat2_ring_space(ioat);
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dev_dbg(to_dev(chan), "freeing %d idle descriptors\n", descs);
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for (i = 0; i < descs; i++) {
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desc = ioat2_get_ring_ent(ioat, ioat->head + i);
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ioat2_free_ring_ent(desc, c);
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@ -625,6 +647,7 @@ static void ioat2_free_chan_resources(struct dma_chan *c)
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for (i = 0; i < total_descs - descs; i++) {
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desc = ioat2_get_ring_ent(ioat, ioat->tail + i);
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dump_desc_dbg(ioat, desc);
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ioat2_free_ring_ent(desc, c);
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}
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@ -116,6 +116,9 @@ struct ioat_ring_ent {
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struct ioat_dma_descriptor *hw;
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struct dma_async_tx_descriptor txd;
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size_t len;
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#ifdef DEBUG
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int id;
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#endif
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};
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static inline struct ioat_ring_ent *
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