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Merge of davem@nuts.davemloft.net:/disk1/GIT/sparc-2.6/.git/

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This commit is contained in:
David S. Miller 2005-05-24 18:08:07 -07:00
commit 6df16d0c35
4 changed files with 36 additions and 0 deletions
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11
arch/sparc64/kernel/setup.c
View File

@ -383,6 +383,17 @@ static void __init process_switch(char c)
/* Use PROM debug console. */
register_console(&prom_debug_console);
break;
case 'P':
/* Force UltraSPARC-III P-Cache on. */
if (tlb_type != cheetah) {
printk("BOOT: Ignoring P-Cache force option.\n");
break;
}
cheetah_pcache_forced_on = 1;
add_taint(TAINT_MACHINE_CHECK);
cheetah_enable_pcache();
break;
default:
printk("Unknown boot switch (-%c)\n", c);
break;

3
arch/sparc64/kernel/smp.c
View File

@ -123,6 +123,9 @@ void __init smp_callin(void)
smp_setup_percpu_timer();
if (cheetah_pcache_forced_on)
cheetah_enable_pcache();
local_irq_enable();
calibrate_delay();

19
arch/sparc64/kernel/traps.c
View File

@ -421,6 +421,25 @@ asmlinkage void cee_log(unsigned long ce_status,
}
}
int cheetah_pcache_forced_on;
void cheetah_enable_pcache(void)
{
unsigned long dcr;
printk("CHEETAH: Enabling P-Cache on cpu %d.\n",
smp_processor_id());
__asm__ __volatile__("ldxa [%%g0] %1, %0"
: "=r" (dcr)
: "i" (ASI_DCU_CONTROL_REG));
dcr |= (DCU_PE | DCU_HPE | DCU_SPE | DCU_SL);
__asm__ __volatile__("stxa %0, [%%g0] %1\n\t"
"membar #Sync"
: /* no outputs */
: "r" (dcr), "i" (ASI_DCU_CONTROL_REG));
}
/* Cheetah error trap handling. */
static unsigned long ecache_flush_physbase;
static unsigned long ecache_flush_linesize;

3
include/asm-sparc64/spitfire.h
View File

@ -48,6 +48,9 @@ enum ultra_tlb_layout {
extern enum ultra_tlb_layout tlb_type;
extern int cheetah_pcache_forced_on;
extern void cheetah_enable_pcache(void);
#define sparc64_highest_locked_tlbent() \
(tlb_type == spitfire ? \
SPITFIRE_HIGHEST_LOCKED_TLBENT : \