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Cross-driver (xe-core) Changes:

Browse Source 
- Require BMG scanout buffers to be 64k physically aligned (Maarten)
 
 Core (drm) Changes:
 - Introducing Xe2 ccs modifiers for integrated and discrete graphics (Juha-Pekka)
 
 Driver Changes:
 - General cleanup and more work moving towards intel_display isolation (Jani)
 - New display workaround (Suraj)
 - Use correct cp_irq_count on HDCP (Suraj)
 - eDP PSR fix when CRC is enabled (Jouni)
 - Fix DP MST state after a sink reset (Imre)
 - Fix Arrow Lake GSC firmware version (John)
 - Use chained DSBs for LUT programming (Ville)
 -----BEGIN PGP SIGNATURE-----
 
 iQEzBAABCAAdFiEEbSBwaO7dZQkcLOKj+mJfZA7rE8oFAmbQf+AACgkQ+mJfZA7r
 E8pKQQf+K6n6lMhtpfNUYkFS6IFkNDMuWZV6R262AWNFIJkBumfiqb+LLsfoxfb8
 jcrYHKw9cPsx2BWg645KbImhT1L6iISfY0OKkUmDLCyUUV8uhbbnKScF8OK01HVW
 XWeZo9LB9gM8SmVJMljHsko+4JCiOq8+99Jm/GjVCZmW69tQ2fFfjeF3Nh9v32uI
 +DcGlFP33Htp7oynOJxyfqGK1RfKjkJSZEQKODNHKJ7Q+2LRkA85xs3yfHkUkBX8
 AjNI82r1SqAodhCgw8k19yeawvsAx8eu0h6Cal5UQzHlnAYEjfh+flbIDJv7YAZX
 Nh5lpn71LBBGCytCI/MvnsmUtcor7A==
 =tLyy
 -----END PGP SIGNATURE-----

Merge tag 'drm-intel-next-2024-08-29' of https://gitlab.freedesktop.org/drm/i915/kernel into drm-next

Cross-driver (xe-core) Changes:
- Require BMG scanout buffers to be 64k physically aligned (Maarten)

Core (drm) Changes:
- Introducing Xe2 ccs modifiers for integrated and discrete graphics (Juha-Pekka)

Driver Changes:
- General cleanup and more work moving towards intel_display isolation (Jani)
- New display workaround (Suraj)
- Use correct cp_irq_count on HDCP (Suraj)
- eDP PSR fix when CRC is enabled (Jouni)
- Fix DP MST state after a sink reset (Imre)
- Fix Arrow Lake GSC firmware version (John)
- Use chained DSBs for LUT programming (Ville)

Signed-off-by: Dave Airlie <airlied@redhat.com>

From: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/ZtCC0lJ0Zf3MoSdW@intel.com
This commit is contained in:
Dave Airlie 2024-08-30 13:41:26 +10:00
commit 6d0ebb3904
80 changed files with 1516 additions and 776 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

54
drivers/gpu/drm/i915/display/intel_alpm.c
View File

@ -139,7 +139,7 @@ static int
_lnl_compute_aux_less_alpm_params(struct intel_dp *intel_dp,
const struct intel_crtc_state *crtc_state)
{
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
struct intel_display *display = to_intel_display(intel_dp);
int aux_less_wake_time, aux_less_wake_lines, silence_period,
lfps_half_cycle;
@ -158,7 +158,7 @@ _lnl_compute_aux_less_alpm_params(struct intel_dp *intel_dp,
lfps_half_cycle > PORT_ALPM_LFPS_CTL_LAST_LFPS_HALF_CYCLE_DURATION_MASK)
return false;
if (i915->display.params.psr_safest_params)
if (display->params.psr_safest_params)
aux_less_wake_lines = ALPM_CTL_AUX_LESS_WAKE_TIME_MASK;
intel_dp->alpm_parameters.aux_less_wake_lines = aux_less_wake_lines;
@ -171,10 +171,10 @@ _lnl_compute_aux_less_alpm_params(struct intel_dp *intel_dp,
static bool _lnl_compute_alpm_params(struct intel_dp *intel_dp,
const struct intel_crtc_state *crtc_state)
{
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
struct intel_display *display = to_intel_display(intel_dp);
int check_entry_lines;
if (DISPLAY_VER(i915) < 20)
if (DISPLAY_VER(display) < 20)
return true;
/* ALPM Entry Check = 2 + CEILING( 5us /tline ) */
@ -187,7 +187,7 @@ static bool _lnl_compute_alpm_params(struct intel_dp *intel_dp,
if (!_lnl_compute_aux_less_alpm_params(intel_dp, crtc_state))
return false;
if (i915->display.params.psr_safest_params)
if (display->params.psr_safest_params)
check_entry_lines = 15;
intel_dp->alpm_parameters.check_entry_lines = check_entry_lines;
@ -212,9 +212,9 @@ static int tgl_io_buffer_wake_time(void)
static int io_buffer_wake_time(const struct intel_crtc_state *crtc_state)
{
struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
struct intel_display *display = to_intel_display(crtc_state);
if (DISPLAY_VER(i915) >= 12)
if (DISPLAY_VER(display) >= 12)
return tgl_io_buffer_wake_time();
else
return skl_io_buffer_wake_time();
@ -223,7 +223,7 @@ static int io_buffer_wake_time(const struct intel_crtc_state *crtc_state)
bool intel_alpm_compute_params(struct intel_dp *intel_dp,
const struct intel_crtc_state *crtc_state)
{
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
struct intel_display *display = to_intel_display(intel_dp);
int io_wake_lines, io_wake_time, fast_wake_lines, fast_wake_time;
int tfw_exit_latency = 20; /* eDP spec */
int phy_wake = 4; /* eDP spec */
@ -236,9 +236,9 @@ bool intel_alpm_compute_params(struct intel_dp *intel_dp,
fast_wake_time = precharge + preamble + phy_wake +
tfw_exit_latency;
if (DISPLAY_VER(i915) >= 20)
if (DISPLAY_VER(display) >= 20)
max_wake_lines = 68;
else if (DISPLAY_VER(i915) >= 12)
else if (DISPLAY_VER(display) >= 12)
max_wake_lines = 12;
else
max_wake_lines = 8;
@ -255,7 +255,7 @@ bool intel_alpm_compute_params(struct intel_dp *intel_dp,
if (!_lnl_compute_alpm_params(intel_dp, crtc_state))
return false;
if (i915->display.params.psr_safest_params)
if (display->params.psr_safest_params)
io_wake_lines = fast_wake_lines = max_wake_lines;
/* According to Bspec lower limit should be set as 7 lines. */
@ -269,7 +269,7 @@ void intel_alpm_lobf_compute_config(struct intel_dp *intel_dp,
struct intel_crtc_state *crtc_state,
struct drm_connector_state *conn_state)
{
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
struct intel_display *display = to_intel_display(intel_dp);
struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
int waketime_in_lines, first_sdp_position;
int context_latency, guardband;
@ -277,7 +277,7 @@ void intel_alpm_lobf_compute_config(struct intel_dp *intel_dp,
if (!intel_dp_is_edp(intel_dp))
return;
if (DISPLAY_VER(i915) < 20)
if (DISPLAY_VER(display) < 20)
return;
if (!intel_dp->as_sdp_supported)
@ -309,13 +309,13 @@ void intel_alpm_lobf_compute_config(struct intel_dp *intel_dp,
static void lnl_alpm_configure(struct intel_dp *intel_dp,
const struct intel_crtc_state *crtc_state)
{
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
struct intel_display *display = to_intel_display(intel_dp);
enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
enum port port = dp_to_dig_port(intel_dp)->base.port;
u32 alpm_ctl;
if (DISPLAY_VER(dev_priv) < 20 || (!intel_dp->psr.sel_update_enabled &&
!intel_dp_is_edp(intel_dp)))
if (DISPLAY_VER(display) < 20 ||
(!intel_dp->psr.sel_update_enabled && !intel_dp_is_edp(intel_dp)))
return;
/*
@ -329,16 +329,16 @@ static void lnl_alpm_configure(struct intel_dp *intel_dp,
ALPM_CTL_AUX_LESS_SLEEP_HOLD_TIME_50_SYMBOLS |
ALPM_CTL_AUX_LESS_WAKE_TIME(intel_dp->alpm_parameters.aux_less_wake_lines);
intel_de_write(dev_priv,
PORT_ALPM_CTL(dev_priv, port),
intel_de_write(display,
PORT_ALPM_CTL(display, port),
PORT_ALPM_CTL_ALPM_AUX_LESS_ENABLE |
PORT_ALPM_CTL_MAX_PHY_SWING_SETUP(15) |
PORT_ALPM_CTL_MAX_PHY_SWING_HOLD(0) |
PORT_ALPM_CTL_SILENCE_PERIOD(
intel_dp->alpm_parameters.silence_period_sym_clocks));
intel_de_write(dev_priv,
PORT_ALPM_LFPS_CTL(dev_priv, port),
intel_de_write(display,
PORT_ALPM_LFPS_CTL(display, port),
PORT_ALPM_LFPS_CTL_LFPS_CYCLE_COUNT(10) |
PORT_ALPM_LFPS_CTL_LFPS_HALF_CYCLE_DURATION(
intel_dp->alpm_parameters.lfps_half_cycle_num_of_syms) |
@ -356,7 +356,7 @@ static void lnl_alpm_configure(struct intel_dp *intel_dp,
alpm_ctl |= ALPM_CTL_ALPM_ENTRY_CHECK(intel_dp->alpm_parameters.check_entry_lines);
intel_de_write(dev_priv, ALPM_CTL(dev_priv, cpu_transcoder), alpm_ctl);
intel_de_write(display, ALPM_CTL(display, cpu_transcoder), alpm_ctl);
}
void intel_alpm_configure(struct intel_dp *intel_dp,
@ -368,14 +368,14 @@ void intel_alpm_configure(struct intel_dp *intel_dp,
static int i915_edp_lobf_info_show(struct seq_file *m, void *data)
{
struct intel_connector *connector = m->private;
struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
struct intel_display *display = to_intel_display(connector);
struct drm_crtc *crtc;
struct intel_crtc_state *crtc_state;
enum transcoder cpu_transcoder;
u32 alpm_ctl;
int ret;
ret = drm_modeset_lock_single_interruptible(&dev_priv->drm.mode_config.connection_mutex);
ret = drm_modeset_lock_single_interruptible(&display->drm->mode_config.connection_mutex);
if (ret)
return ret;
@ -387,14 +387,14 @@ static int i915_edp_lobf_info_show(struct seq_file *m, void *data)
crtc_state = to_intel_crtc_state(crtc->state);
cpu_transcoder = crtc_state->cpu_transcoder;
alpm_ctl = intel_de_read(dev_priv, ALPM_CTL(dev_priv, cpu_transcoder));
alpm_ctl = intel_de_read(display, ALPM_CTL(display, cpu_transcoder));
seq_printf(m, "LOBF status: %s\n", str_enabled_disabled(alpm_ctl & ALPM_CTL_LOBF_ENABLE));
seq_printf(m, "Aux-wake alpm status: %s\n",
str_enabled_disabled(!(alpm_ctl & ALPM_CTL_ALPM_AUX_LESS_ENABLE)));
seq_printf(m, "Aux-less alpm status: %s\n",
str_enabled_disabled(alpm_ctl & ALPM_CTL_ALPM_AUX_LESS_ENABLE));
out:
drm_modeset_unlock(&dev_priv->drm.mode_config.connection_mutex);
drm_modeset_unlock(&display->drm->mode_config.connection_mutex);
return ret;
}
@ -403,10 +403,10 @@ DEFINE_SHOW_ATTRIBUTE(i915_edp_lobf_info);
void intel_alpm_lobf_debugfs_add(struct intel_connector *connector)
{
struct drm_i915_private *i915 = to_i915(connector->base.dev);
struct intel_display *display = to_intel_display(connector);
struct dentry *root = connector->base.debugfs_entry;
if (DISPLAY_VER(i915) < 20 ||
if (DISPLAY_VER(display) < 20 ||
connector->base.connector_type != DRM_MODE_CONNECTOR_eDP)
return;

6
drivers/gpu/drm/i915/display/intel_atomic.c
View File

@ -276,7 +276,8 @@ intel_crtc_duplicate_state(struct drm_crtc *crtc)
crtc_state->do_async_flip = false;
crtc_state->fb_bits = 0;
crtc_state->update_planes = 0;
crtc_state->dsb = NULL;
crtc_state->dsb_color_vblank = NULL;
crtc_state->dsb_color_commit = NULL;
return &crtc_state->uapi;
}
@ -310,7 +311,8 @@ intel_crtc_destroy_state(struct drm_crtc *crtc,
{
struct intel_crtc_state *crtc_state = to_intel_crtc_state(state);
drm_WARN_ON(crtc->dev, crtc_state->dsb);
drm_WARN_ON(crtc->dev, crtc_state->dsb_color_vblank);
drm_WARN_ON(crtc->dev, crtc_state->dsb_color_commit);
__drm_atomic_helper_crtc_destroy_state(&crtc_state->uapi);
intel_crtc_free_hw_state(crtc_state);

10
drivers/gpu/drm/i915/display/intel_backlight.c
View File

@ -1011,7 +1011,7 @@ static u32 cnp_hz_to_pwm(struct intel_connector *connector, u32 pwm_freq_hz)
{
struct drm_i915_private *i915 = to_i915(connector->base.dev);
return DIV_ROUND_CLOSEST(KHz(RUNTIME_INFO(i915)->rawclk_freq),
return DIV_ROUND_CLOSEST(KHz(DISPLAY_RUNTIME_INFO(i915)->rawclk_freq),
pwm_freq_hz);
}
@ -1073,7 +1073,7 @@ static u32 pch_hz_to_pwm(struct intel_connector *connector, u32 pwm_freq_hz)
{
struct drm_i915_private *i915 = to_i915(connector->base.dev);
return DIV_ROUND_CLOSEST(KHz(RUNTIME_INFO(i915)->rawclk_freq),
return DIV_ROUND_CLOSEST(KHz(DISPLAY_RUNTIME_INFO(i915)->rawclk_freq),
pwm_freq_hz * 128);
}
@ -1091,7 +1091,7 @@ static u32 i9xx_hz_to_pwm(struct intel_connector *connector, u32 pwm_freq_hz)
int clock;
if (IS_PINEVIEW(i915))
clock = KHz(RUNTIME_INFO(i915)->rawclk_freq);
clock = KHz(DISPLAY_RUNTIME_INFO(i915)->rawclk_freq);
else
clock = KHz(i915->display.cdclk.hw.cdclk);
@ -1109,7 +1109,7 @@ static u32 i965_hz_to_pwm(struct intel_connector *connector, u32 pwm_freq_hz)
int clock;
if (IS_G4X(i915))
clock = KHz(RUNTIME_INFO(i915)->rawclk_freq);
clock = KHz(DISPLAY_RUNTIME_INFO(i915)->rawclk_freq);
else
clock = KHz(i915->display.cdclk.hw.cdclk);
@ -1133,7 +1133,7 @@ static u32 vlv_hz_to_pwm(struct intel_connector *connector, u32 pwm_freq_hz)
clock = MHz(25);
mul = 16;
} else {
clock = KHz(RUNTIME_INFO(i915)->rawclk_freq);
clock = KHz(DISPLAY_RUNTIME_INFO(i915)->rawclk_freq);
mul = 128;
}

56
drivers/gpu/drm/i915/display/intel_color.c
View File

@ -1313,8 +1313,8 @@ static void ilk_lut_write(const struct intel_crtc_state *crtc_state,
{
struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
if (crtc_state->dsb)
intel_dsb_reg_write(crtc_state->dsb, reg, val);
if (crtc_state->dsb_color_vblank)
intel_dsb_reg_write(crtc_state->dsb_color_vblank, reg, val);
else
intel_de_write_fw(i915, reg, val);
}
@ -1337,15 +1337,15 @@ static void ilk_load_lut_8(const struct intel_crtc_state *crtc_state,
* unless we either write each entry twice,
* or use non-posted writes
*/
if (crtc_state->dsb)
intel_dsb_nonpost_start(crtc_state->dsb);
if (crtc_state->dsb_color_vblank)
intel_dsb_nonpost_start(crtc_state->dsb_color_vblank);
for (i = 0; i < 256; i++)
ilk_lut_write(crtc_state, LGC_PALETTE(pipe, i),
i9xx_lut_8(&lut[i]));
if (crtc_state->dsb)
intel_dsb_nonpost_end(crtc_state->dsb);
if (crtc_state->dsb_color_vblank)
intel_dsb_nonpost_end(crtc_state->dsb_color_vblank);
}
static void ilk_load_lut_10(const struct intel_crtc_state *crtc_state,
@ -1870,7 +1870,7 @@ void intel_color_load_luts(const struct intel_crtc_state *crtc_state)
{
struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
if (crtc_state->dsb)
if (crtc_state->dsb_color_vblank)
return;
i915->display.funcs.color->load_luts(crtc_state);
@ -1890,8 +1890,8 @@ void intel_color_commit_arm(const struct intel_crtc_state *crtc_state)
i915->display.funcs.color->color_commit_arm(crtc_state);
if (crtc_state->dsb)
intel_dsb_commit(crtc_state->dsb, true);
if (crtc_state->dsb_color_commit)
intel_dsb_commit(crtc_state->dsb_color_commit, false);
}
void intel_color_post_update(const struct intel_crtc_state *crtc_state)
@ -1919,33 +1919,51 @@ void intel_color_prepare_commit(struct intel_atomic_state *state,
if (!crtc_state->pre_csc_lut && !crtc_state->post_csc_lut)
return;
crtc_state->dsb = intel_dsb_prepare(state, crtc, INTEL_DSB_0, 1024);
if (!crtc_state->dsb)
crtc_state->dsb_color_vblank = intel_dsb_prepare(state, crtc, INTEL_DSB_1, 1024);
if (!crtc_state->dsb_color_vblank)
return;
i915->display.funcs.color->load_luts(crtc_state);
intel_dsb_finish(crtc_state->dsb);
intel_dsb_finish(crtc_state->dsb_color_vblank);
crtc_state->dsb_color_commit = intel_dsb_prepare(state, crtc, INTEL_DSB_0, 16);
if (!crtc_state->dsb_color_commit) {
intel_dsb_cleanup(crtc_state->dsb_color_vblank);
crtc_state->dsb_color_vblank = NULL;
return;
}
intel_dsb_chain(state, crtc_state->dsb_color_commit,
crtc_state->dsb_color_vblank, true);
intel_dsb_finish(crtc_state->dsb_color_commit);
}
void intel_color_cleanup_commit(struct intel_crtc_state *crtc_state)
{
if (!crtc_state->dsb)
return;
if (crtc_state->dsb_color_commit) {
intel_dsb_cleanup(crtc_state->dsb_color_commit);
crtc_state->dsb_color_commit = NULL;
}
intel_dsb_cleanup(crtc_state->dsb);
crtc_state->dsb = NULL;
if (crtc_state->dsb_color_vblank) {
intel_dsb_cleanup(crtc_state->dsb_color_vblank);
crtc_state->dsb_color_vblank = NULL;
}
}
void intel_color_wait_commit(const struct intel_crtc_state *crtc_state)
{
if (crtc_state->dsb)
intel_dsb_wait(crtc_state->dsb);
if (crtc_state->dsb_color_commit)
intel_dsb_wait(crtc_state->dsb_color_commit);
if (crtc_state->dsb_color_vblank)
intel_dsb_wait(crtc_state->dsb_color_vblank);
}
bool intel_color_uses_dsb(const struct intel_crtc_state *crtc_state)
{
return crtc_state->dsb;
return crtc_state->dsb_color_vblank;
}
static bool intel_can_preload_luts(struct intel_atomic_state *state,

2
drivers/gpu/drm/i915/display/intel_ddi.c
View File

@ -4900,7 +4900,7 @@ void intel_ddi_init(struct intel_display *display,
* driver. In that case we should skip initializing the corresponding
* outputs.
*/
if (intel_hti_uses_phy(dev_priv, phy)) {
if (intel_hti_uses_phy(display, phy)) {
drm_dbg_kms(&dev_priv->drm, "PORT %c / PHY %c reserved by HTI\n",
port_name(port), phy_name(phy));
return;

11
drivers/gpu/drm/i915/display/intel_display.c
View File

@ -1032,8 +1032,8 @@ static bool intel_crtc_vrr_enabling(struct intel_atomic_state *state,
vrr_params_changed(old_crtc_state, new_crtc_state)));
}
static bool intel_crtc_vrr_disabling(struct intel_atomic_state *state,
struct intel_crtc *crtc)
bool intel_crtc_vrr_disabling(struct intel_atomic_state *state,
struct intel_crtc *crtc)
{
const struct intel_crtc_state *old_crtc_state =
intel_atomic_get_old_crtc_state(state, crtc);
@ -6260,6 +6260,8 @@ static int intel_async_flip_check_hw(struct intel_atomic_state *state, struct in
case I915_FORMAT_MOD_Y_TILED:
case I915_FORMAT_MOD_Yf_TILED:
case I915_FORMAT_MOD_4_TILED:
case I915_FORMAT_MOD_4_TILED_BMG_CCS:
case I915_FORMAT_MOD_4_TILED_LNL_CCS:
break;
default:
drm_dbg_kms(&i915->drm,
@ -7511,7 +7513,8 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
*
* FIXME get rid of this funny new->old swapping
*/
old_crtc_state->dsb = fetch_and_zero(&new_crtc_state->dsb);
old_crtc_state->dsb_color_vblank = fetch_and_zero(&new_crtc_state->dsb_color_vblank);
old_crtc_state->dsb_color_commit = fetch_and_zero(&new_crtc_state->dsb_color_commit);
}
/* Underruns don't always raise interrupts, so check manually */
@ -7933,7 +7936,7 @@ void intel_setup_outputs(struct drm_i915_private *dev_priv)
g4x_dp_init(dev_priv, DP_D, PORT_D);
if (SUPPORTS_TV(dev_priv))
intel_tv_init(dev_priv);
intel_tv_init(display);
} else if (DISPLAY_VER(dev_priv) == 2) {
if (IS_I85X(dev_priv))
intel_lvds_init(dev_priv);

3
drivers/gpu/drm/i915/display/intel_display.h
View File

@ -532,6 +532,9 @@ void intel_plane_fixup_bitmasks(struct intel_crtc_state *crtc_state);
void intel_update_watermarks(struct drm_i915_private *i915);
bool intel_crtc_vrr_disabling(struct intel_atomic_state *state,
struct intel_crtc *crtc);
/* modesetting */
int intel_modeset_pipes_in_mask_early(struct intel_atomic_state *state,
const char *reason, u8 pipe_mask);

2
drivers/gpu/drm/i915/display/intel_display_debugfs.c
View File

@ -1073,7 +1073,7 @@ void intel_display_debugfs_register(struct drm_i915_private *i915)
intel_opregion_debugfs_register(display);
intel_psr_debugfs_register(i915);
intel_wm_debugfs_register(i915);
intel_display_debugfs_params(i915);
intel_display_debugfs_params(display);
}
static int i915_hdcp_sink_capability_show(struct seq_file *m, void *data)

8
drivers/gpu/drm/i915/display/intel_display_debugfs_params.c
View File

@ -151,13 +151,13 @@ intel_display_debugfs_create_uint(const char *name, umode_t mode,
} while (0)
/* add a subdirectory with files for each intel display param */
void intel_display_debugfs_params(struct drm_i915_private *i915)
void intel_display_debugfs_params(struct intel_display *display)
{
struct drm_minor *minor = i915->drm.primary;
struct drm_minor *minor = display->drm->primary;
struct dentry *dir;
char dirname[16];
snprintf(dirname, sizeof(dirname), "%s_params", i915->drm.driver->name);
snprintf(dirname, sizeof(dirname), "%s_params", display->drm->driver->name);
dir = debugfs_lookup(dirname, minor->debugfs_root);
if (!dir)
dir = debugfs_create_dir(dirname, minor->debugfs_root);
@ -171,7 +171,7 @@ void intel_display_debugfs_params(struct drm_i915_private *i915)
*/
#define REGISTER(T, x, unused, mode, ...) _intel_display_param_create_file( \
dir, #x, mode, &i915->display.params.x);
dir, #x, mode, &display->params.x);
INTEL_DISPLAY_PARAMS_FOR_EACH(REGISTER);
#undef REGISTER
}

4
drivers/gpu/drm/i915/display/intel_display_debugfs_params.h
View File

@ -6,8 +6,8 @@
#ifndef __INTEL_DISPLAY_DEBUGFS_PARAMS__
#define __INTEL_DISPLAY_DEBUGFS_PARAMS__
struct drm_i915_private;
struct intel_display;
void intel_display_debugfs_params(struct drm_i915_private *i915);
void intel_display_debugfs_params(struct intel_display *display);
#endif /* __INTEL_DISPLAY_DEBUGFS_PARAMS__ */

232
drivers/gpu/drm/i915/display/intel_display_device.c
View File

@ -16,14 +16,25 @@
#include "intel_display_power.h"
#include "intel_display_reg_defs.h"
#include "intel_fbc.h"
#include "intel_step.h"
__diag_push();
__diag_ignore_all("-Woverride-init", "Allow field initialization overrides for display info");
struct stepping_desc {
const enum intel_step *map; /* revid to step map */
size_t size; /* map size */
};
#define STEP_INFO(_map) \
.step_info.map = _map, \
.step_info.size = ARRAY_SIZE(_map)
struct subplatform_desc {
enum intel_display_subplatform subplatform;
const char *name;
const u16 *pciidlist;
struct stepping_desc step_info;
};
struct platform_desc {
@ -31,6 +42,7 @@ struct platform_desc {
const char *name;
const struct subplatform_desc *subplatforms;
const struct intel_display_device_info *info; /* NULL for GMD ID */
struct stepping_desc step_info;
};
#define PLATFORM(_platform) \
@ -610,6 +622,13 @@ static const u16 skl_ulx_ids[] = {
0
};
static const enum intel_step skl_steppings[] = {
[0x6] = STEP_G0,
[0x7] = STEP_H0,
[0x9] = STEP_J0,
[0xA] = STEP_I1,
};
static const struct platform_desc skl_desc = {
PLATFORM(SKYLAKE),
.subplatforms = (const struct subplatform_desc[]) {
@ -618,6 +637,7 @@ static const struct platform_desc skl_desc = {
{},
},
.info = &skl_display,
STEP_INFO(skl_steppings),
};
static const u16 kbl_ult_ids[] = {
@ -634,6 +654,16 @@ static const u16 kbl_ulx_ids[] = {
0
};
static const enum intel_step kbl_steppings[] = {
[1] = STEP_B0,
[2] = STEP_B0,
[3] = STEP_B0,
[4] = STEP_C0,
[5] = STEP_B1,
[6] = STEP_B1,
[7] = STEP_C0,
};
static const struct platform_desc kbl_desc = {
PLATFORM(KABYLAKE),
.subplatforms = (const struct subplatform_desc[]) {
@ -642,6 +672,7 @@ static const struct platform_desc kbl_desc = {
{},
},
.info = &skl_display,
STEP_INFO(kbl_steppings),
};
static const u16 cfl_ult_ids[] = {
@ -706,6 +737,13 @@ static const struct platform_desc cml_desc = {
BIT(TRANSCODER_DSI_A) | BIT(TRANSCODER_DSI_C), \
.__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C)
static const enum intel_step bxt_steppings[] = {
[0xA] = STEP_C0,
[0xB] = STEP_C0,
[0xC] = STEP_D0,
[0xD] = STEP_E0,
};
static const struct platform_desc bxt_desc = {
PLATFORM(BROXTON),
.info = &(const struct intel_display_device_info) {
@ -714,6 +752,11 @@ static const struct platform_desc bxt_desc = {
.__runtime_defaults.ip.ver = 9,
},
STEP_INFO(bxt_steppings),
};
static const enum intel_step glk_steppings[] = {
[3] = STEP_B0,
};
static const struct platform_desc glk_desc = {
@ -725,6 +768,7 @@ static const struct platform_desc glk_desc = {
.__runtime_defaults.ip.ver = 10,
},
STEP_INFO(glk_steppings),
};
#define ICL_DISPLAY \
@ -773,6 +817,10 @@ static const u16 icl_port_f_ids[] = {
0
};
static const enum intel_step icl_steppings[] = {
[7] = STEP_D0,
};
static const struct platform_desc icl_desc = {
PLATFORM(ICELAKE),
.subplatforms = (const struct subplatform_desc[]) {
@ -784,6 +832,7 @@ static const struct platform_desc icl_desc = {
.__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D) | BIT(PORT_E),
},
STEP_INFO(icl_steppings),
};
static const struct intel_display_device_info jsl_ehl_display = {
@ -792,14 +841,21 @@ static const struct intel_display_device_info jsl_ehl_display = {
.__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D),
};
static const enum intel_step jsl_ehl_steppings[] = {
[0] = STEP_A0,
[1] = STEP_B0,
};
static const struct platform_desc jsl_desc = {
PLATFORM(JASPERLAKE),
.info = &jsl_ehl_display,
STEP_INFO(jsl_ehl_steppings),
};
static const struct platform_desc ehl_desc = {
PLATFORM(ELKHARTLAKE),
.info = &jsl_ehl_display,
STEP_INFO(jsl_ehl_steppings),
};
#define XE_D_DISPLAY \
@ -850,10 +906,23 @@ static const u16 tgl_uy_ids[] = {
0
};
static const enum intel_step tgl_steppings[] = {
[0] = STEP_B0,
[1] = STEP_D0,
};
static const enum intel_step tgl_uy_steppings[] = {
[0] = STEP_A0,
[1] = STEP_C0,
[2] = STEP_C0,
[3] = STEP_D0,
};
static const struct platform_desc tgl_desc = {
PLATFORM(TIGERLAKE),
.subplatforms = (const struct subplatform_desc[]) {
{ INTEL_DISPLAY_TIGERLAKE_UY, "UY", tgl_uy_ids },
{ INTEL_DISPLAY_TIGERLAKE_UY, "UY", tgl_uy_ids,
STEP_INFO(tgl_uy_steppings) },
{},
},
.info = &(const struct intel_display_device_info) {
@ -866,6 +935,12 @@ static const struct platform_desc tgl_desc = {
.__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) |
BIT(PORT_TC1) | BIT(PORT_TC2) | BIT(PORT_TC3) | BIT(PORT_TC4) | BIT(PORT_TC5) | BIT(PORT_TC6),
},
STEP_INFO(tgl_steppings),
};
static const enum intel_step dg1_steppings[] = {
[0] = STEP_A0,
[1] = STEP_B0,
};
static const struct platform_desc dg1_desc = {
@ -876,6 +951,13 @@ static const struct platform_desc dg1_desc = {
.__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) |
BIT(PORT_TC1) | BIT(PORT_TC2),
},
STEP_INFO(dg1_steppings),
};
static const enum intel_step rkl_steppings[] = {
[0] = STEP_A0,
[1] = STEP_B0,
[4] = STEP_C0,
};
static const struct platform_desc rkl_desc = {
@ -892,6 +974,7 @@ static const struct platform_desc rkl_desc = {
.__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) |
BIT(PORT_TC1) | BIT(PORT_TC2),
},
STEP_INFO(rkl_steppings),
};
static const u16 adls_rpls_ids[] = {
@ -899,10 +982,24 @@ static const u16 adls_rpls_ids[] = {
0
};
static const enum intel_step adl_s_steppings[] = {
[0x0] = STEP_A0,
[0x1] = STEP_A2,
[0x4] = STEP_B0,
[0x8] = STEP_B0,
[0xC] = STEP_C0,
};
static const enum intel_step adl_s_rpl_s_steppings[] = {
[0x4] = STEP_D0,
[0xC] = STEP_C0,
};
static const struct platform_desc adl_s_desc = {
PLATFORM(ALDERLAKE_S),
.subplatforms = (const struct subplatform_desc[]) {
{ INTEL_DISPLAY_ALDERLAKE_S_RAPTORLAKE_S, "RPL-S", adls_rpls_ids },
{ INTEL_DISPLAY_ALDERLAKE_S_RAPTORLAKE_S, "RPL-S", adls_rpls_ids,
STEP_INFO(adl_s_rpl_s_steppings) },
{},
},
.info = &(const struct intel_display_device_info) {
@ -913,6 +1010,7 @@ static const struct platform_desc adl_s_desc = {
.__runtime_defaults.port_mask = BIT(PORT_A) |
BIT(PORT_TC1) | BIT(PORT_TC2) | BIT(PORT_TC3) | BIT(PORT_TC4),
},
STEP_INFO(adl_s_steppings),
};
#define XE_LPD_FEATURES \
@ -986,15 +1084,34 @@ static const u16 adlp_rplp_ids[] = {
0
};
static const enum intel_step adl_p_steppings[] = {
[0x0] = STEP_A0,
[0x4] = STEP_B0,
[0x8] = STEP_C0,
[0xC] = STEP_D0,
};
static const enum intel_step adl_p_adl_n_steppings[] = {
[0x0] = STEP_D0,
};
static const enum intel_step adl_p_rpl_pu_steppings[] = {
[0x4] = STEP_E0,
};
static const struct platform_desc adl_p_desc = {
PLATFORM(ALDERLAKE_P),
.subplatforms = (const struct subplatform_desc[]) {
{ INTEL_DISPLAY_ALDERLAKE_P_ALDERLAKE_N, "ADL-N", adlp_adln_ids },
{ INTEL_DISPLAY_ALDERLAKE_P_RAPTORLAKE_U, "RPL-U", adlp_rplu_ids },
{ INTEL_DISPLAY_ALDERLAKE_P_RAPTORLAKE_P, "RPL-P", adlp_rplp_ids },
{ INTEL_DISPLAY_ALDERLAKE_P_ALDERLAKE_N, "ADL-N", adlp_adln_ids,
STEP_INFO(adl_p_adl_n_steppings) },
{ INTEL_DISPLAY_ALDERLAKE_P_RAPTORLAKE_P, "RPL-P", adlp_rplp_ids,
STEP_INFO(adl_p_rpl_pu_steppings) },
{ INTEL_DISPLAY_ALDERLAKE_P_RAPTORLAKE_U, "RPL-U", adlp_rplu_ids,
STEP_INFO(adl_p_rpl_pu_steppings) },
{},
},
.info = &xe_lpd_display,
STEP_INFO(adl_p_steppings),
};
static const struct intel_display_device_info xe_hpd_display = {
@ -1023,12 +1140,33 @@ static const u16 dg2_g12_ids[] = {
0
};
static const enum intel_step dg2_g10_steppings[] = {
[0x0] = STEP_A0,
[0x1] = STEP_A0,
[0x4] = STEP_B0,
[0x8] = STEP_C0,
};
static const enum intel_step dg2_g11_steppings[] = {
[0x0] = STEP_B0,
[0x4] = STEP_C0,
[0x5] = STEP_C0,
};
static const enum intel_step dg2_g12_steppings[] = {
[0x0] = STEP_C0,
[0x1] = STEP_C0,
};
static const struct platform_desc dg2_desc = {
PLATFORM(DG2),
.subplatforms = (const struct subplatform_desc[]) {
{ INTEL_DISPLAY_DG2_G10, "G10", dg2_g10_ids },
{ INTEL_DISPLAY_DG2_G11, "G11", dg2_g11_ids },
{ INTEL_DISPLAY_DG2_G12, "G12", dg2_g12_ids },
{ INTEL_DISPLAY_DG2_G10, "G10", dg2_g10_ids,
STEP_INFO(dg2_g10_steppings) },
{ INTEL_DISPLAY_DG2_G11, "G11", dg2_g11_ids,
STEP_INFO(dg2_g11_steppings) },
{ INTEL_DISPLAY_DG2_G12, "G12", dg2_g12_ids,
STEP_INFO(dg2_g12_steppings) },
{},
},
.info = &xe_hpd_display,
@ -1261,13 +1399,66 @@ find_subplatform_desc(struct pci_dev *pdev, const struct platform_desc *desc)
return NULL;
}
static enum intel_step get_pre_gmdid_step(struct intel_display *display,
const struct stepping_desc *main,
const struct stepping_desc *sub)
{
struct pci_dev *pdev = to_pci_dev(display->drm->dev);
const enum intel_step *map = main->map;
int size = main->size;
int revision = pdev->revision;
enum intel_step step;
/* subplatform stepping info trumps main platform info */
if (sub && sub->map && sub->size) {
map = sub->map;
size = sub->size;
}
/* not all platforms define steppings, and it's fine */
if (!map || !size)
return STEP_NONE;
if (revision < size && map[revision] != STEP_NONE) {
step = map[revision];
} else {
drm_warn(display->drm, "Unknown revision 0x%02x\n", revision);
/*
* If we hit a gap in the revision to step map, use the information
* for the next revision.
*
* This may be wrong in all sorts of ways, especially if the
* steppings in the array are not monotonically increasing, but
* it's better than defaulting to 0.
*/
while (revision < size && map[revision] == STEP_NONE)
revision++;
if (revision < size) {
drm_dbg_kms(display->drm, "Using display stepping for revision 0x%02x\n",
revision);
step = map[revision];
} else {
drm_dbg_kms(display->drm, "Using future display stepping\n");
step = STEP_FUTURE;
}
}
drm_WARN_ON(display->drm, step == STEP_NONE);
return step;
}
void intel_display_device_probe(struct drm_i915_private *i915)
{
struct intel_display *display = &i915->display;
struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
const struct intel_display_device_info *info;
struct intel_display_ip_ver ip_ver = {};
const struct platform_desc *desc;
const struct subplatform_desc *subdesc;
enum intel_step step;
/* Add drm device backpointer as early as possible. */
i915->display.drm = &i915->drm;
@ -1307,13 +1498,25 @@ void intel_display_device_probe(struct drm_i915_private *i915)
DISPLAY_RUNTIME_INFO(i915)->subplatform = subdesc->subplatform;
}
if (ip_ver.ver || ip_ver.rel || ip_ver.step)
if (ip_ver.ver || ip_ver.rel || ip_ver.step) {
DISPLAY_RUNTIME_INFO(i915)->ip = ip_ver;
step = STEP_A0 + ip_ver.step;
if (step > STEP_FUTURE) {
drm_dbg_kms(display->drm, "Using future display stepping\n");
step = STEP_FUTURE;
}
} else {
step = get_pre_gmdid_step(display, &desc->step_info,
subdesc ? &subdesc->step_info : NULL);
}
drm_info(&i915->drm, "Found %s%s%s (device ID %04x) display version %u.%02u\n",
DISPLAY_RUNTIME_INFO(i915)->step = step;
drm_info(&i915->drm, "Found %s%s%s (device ID %04x) display version %u.%02u stepping %s\n",
desc->name, subdesc ? "/" : "", subdesc ? subdesc->name : "",
pdev->device, DISPLAY_RUNTIME_INFO(i915)->ip.ver,
DISPLAY_RUNTIME_INFO(i915)->ip.rel);
DISPLAY_RUNTIME_INFO(i915)->ip.rel,
step != STEP_NONE ? intel_step_name(step) : "N/A");
return;
@ -1474,6 +1677,9 @@ static void __intel_display_device_info_runtime_init(struct drm_i915_private *i9
}
}
display_runtime->rawclk_freq = intel_read_rawclk(i915);
drm_dbg_kms(&i915->drm, "rawclk rate: %d kHz\n", display_runtime->rawclk_freq);
return;
display_fused_off:
@ -1509,6 +1715,8 @@ void intel_display_device_info_print(const struct intel_display_device_info *inf
drm_printf(p, "display version: %u\n",
runtime->ip.ver);
drm_printf(p, "display stepping: %s\n", intel_step_name(runtime->step));
#define PRINT_FLAG(name) drm_printf(p, "%s: %s\n", #name, str_yes_no(info->name))
DEV_INFO_DISPLAY_FOR_EACH_FLAG(PRINT_FLAG);
#undef PRINT_FLAG
@ -1516,6 +1724,8 @@ void intel_display_device_info_print(const struct intel_display_device_info *inf
drm_printf(p, "has_hdcp: %s\n", str_yes_no(runtime->has_hdcp));
drm_printf(p, "has_dmc: %s\n", str_yes_no(runtime->has_dmc));
drm_printf(p, "has_dsc: %s\n", str_yes_no(runtime->has_dsc));
drm_printf(p, "rawclk rate: %u kHz\n", runtime->rawclk_freq);
}
/*

21
drivers/gpu/drm/i915/display/intel_display_device.h
View File

@ -161,7 +161,7 @@ enum intel_display_subplatform {
#define SUPPORTS_TV(i915) (DISPLAY_INFO(i915)->supports_tv)
/* Check that device has a display IP version within the specific range. */
#define IS_DISPLAY_IP_RANGE(__i915, from, until) ( \
#define IS_DISPLAY_VER_FULL(__i915, from, until) ( \
BUILD_BUG_ON_ZERO((from) < IP_VER(2, 0)) + \
(DISPLAY_VER_FULL(__i915) >= (from) && \
DISPLAY_VER_FULL(__i915) <= (until)))
@ -175,14 +175,14 @@ enum intel_display_subplatform {
* hardware fix is present and the software workaround is no longer necessary.
* E.g.,
*
* IS_DISPLAY_IP_STEP(i915, IP_VER(14, 0), STEP_A0, STEP_B2)
* IS_DISPLAY_IP_STEP(i915, IP_VER(14, 0), STEP_C0, STEP_FOREVER)
* IS_DISPLAY_VER_STEP(i915, IP_VER(14, 0), STEP_A0, STEP_B2)
* IS_DISPLAY_VER_STEP(i915, IP_VER(14, 0), STEP_C0, STEP_FOREVER)
*
* "STEP_FOREVER" can be passed as "until" for workarounds that have no upper
* stepping bound for the specified IP version.
*/
#define IS_DISPLAY_IP_STEP(__i915, ipver, from, until) \
(IS_DISPLAY_IP_RANGE((__i915), (ipver), (ipver)) && \
#define IS_DISPLAY_VER_STEP(__i915, ipver, from, until) \
(IS_DISPLAY_VER_FULL((__i915), (ipver), (ipver)) && \
IS_DISPLAY_STEP((__i915), (from), (until)))
#define DISPLAY_INFO(i915) (__to_intel_display(i915)->info.__device_info)
@ -194,6 +194,12 @@ enum intel_display_subplatform {
#define IS_DISPLAY_VER(i915, from, until) \
(DISPLAY_VER(i915) >= (from) && DISPLAY_VER(i915) <= (until))
#define INTEL_DISPLAY_STEP(__i915) (DISPLAY_RUNTIME_INFO(__i915)->step)
#define IS_DISPLAY_STEP(__i915, since, until) \
(drm_WARN_ON(__to_intel_display(__i915)->drm, INTEL_DISPLAY_STEP(__i915) == STEP_NONE), \
INTEL_DISPLAY_STEP(__i915) >= (since) && INTEL_DISPLAY_STEP(__i915) < (until))
struct intel_display_runtime_info {
enum intel_display_platform platform;
enum intel_display_subplatform subplatform;
@ -201,8 +207,11 @@ struct intel_display_runtime_info {
struct intel_display_ip_ver {
u16 ver;
u16 rel;
u16 step;
u16 step; /* hardware */
} ip;
int step; /* symbolic */
u32 rawclk_freq;
u8 pipe_mask;
u8 cpu_transcoder_mask;

2
drivers/gpu/drm/i915/display/intel_display_driver.c
View File

@ -453,7 +453,7 @@ int intel_display_driver_probe_nogem(struct drm_i915_private *i915)
if (i915->display.cdclk.max_cdclk_freq == 0)
intel_update_max_cdclk(i915);
intel_hti_init(i915);
intel_hti_init(display);
/* Just disable it once at startup */
intel_vga_disable(i915);

17
drivers/gpu/drm/i915/display/intel_display_irq.c
View File

@ -14,6 +14,7 @@
#include "intel_display_trace.h"
#include "intel_display_types.h"
#include "intel_dp_aux.h"
#include "intel_dsb.h"
#include "intel_fdi_regs.h"
#include "intel_fifo_underrun.h"
#include "intel_gmbus.h"
@ -1164,6 +1165,17 @@ void gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
if (iir & gen8_de_pipe_flip_done_mask(dev_priv))
flip_done_handler(dev_priv, pipe);
if (HAS_DSB(dev_priv)) {
if (iir & GEN12_DSB_INT(INTEL_DSB_0))
intel_dsb_irq_handler(&dev_priv->display, pipe, INTEL_DSB_0);
if (iir & GEN12_DSB_INT(INTEL_DSB_1))
intel_dsb_irq_handler(&dev_priv->display, pipe, INTEL_DSB_1);
if (iir & GEN12_DSB_INT(INTEL_DSB_2))
intel_dsb_irq_handler(&dev_priv->display, pipe, INTEL_DSB_2);
}
if (iir & GEN8_PIPE_CDCLK_CRC_DONE)
hsw_pipe_crc_irq_handler(dev_priv, pipe);
@ -1736,6 +1748,11 @@ void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
de_port_masked |= DSI0_TE | DSI1_TE;
}
if (HAS_DSB(dev_priv))
de_pipe_masked |= GEN12_DSB_INT(INTEL_DSB_0) |
GEN12_DSB_INT(INTEL_DSB_1) |
GEN12_DSB_INT(INTEL_DSB_2);
de_pipe_enables = de_pipe_masked |
GEN8_PIPE_VBLANK |
gen8_de_pipe_underrun_mask(dev_priv) |

6
drivers/gpu/drm/i915/display/intel_display_params.c
View File

@ -173,14 +173,14 @@ static void _param_print_charp(struct drm_printer *p, const char *driver_name,
/**
* intel_display_params_dump - dump intel display modparams
* @i915: i915 device
* @display: display device
* @p: the &drm_printer
*
* Pretty printer for i915 modparams.
*/
void intel_display_params_dump(struct drm_i915_private *i915, struct drm_printer *p)
void intel_display_params_dump(struct intel_display *display, struct drm_printer *p)
{
#define PRINT(T, x, ...) _param_print(p, i915->drm.driver->name, #x, i915->display.params.x);
#define PRINT(T, x, ...) _param_print(p, display->drm->driver->name, #x, display->params.x);
INTEL_DISPLAY_PARAMS_FOR_EACH(PRINT);
#undef PRINT
}

4
drivers/gpu/drm/i915/display/intel_display_params.h
View File

@ -9,7 +9,7 @@
#include <linux/types.h>
struct drm_printer;
struct drm_i915_private;
struct intel_display;
/*
* Invoke param, a function-like macro, for each intel display param, with
@ -56,7 +56,7 @@ struct intel_display_params {
};
#undef MEMBER
void intel_display_params_dump(struct drm_i915_private *i915,
void intel_display_params_dump(struct intel_display *display,
struct drm_printer *p);
void intel_display_params_copy(struct intel_display_params *dest);
void intel_display_params_free(struct intel_display_params *params);

20
drivers/gpu/drm/i915/display/intel_display_power.c
View File

@ -36,7 +36,7 @@
for_each_power_well_reverse(__dev_priv, __power_well) \
for_each_if(test_bit((__domain), (__power_well)->domains.bits))
const char *
static const char *
intel_display_power_domain_str(enum intel_display_power_domain domain)
{
switch (domain) {
@ -198,20 +198,8 @@ intel_display_power_domain_str(enum intel_display_power_domain domain)
}
}
/**
* __intel_display_power_is_enabled - unlocked check for a power domain
* @dev_priv: i915 device instance
* @domain: power domain to check
*
* This is the unlocked version of intel_display_power_is_enabled() and should
* only be used from error capture and recovery code where deadlocks are
* possible.
*
* Returns:
* True when the power domain is enabled, false otherwise.
*/
bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
enum intel_display_power_domain domain)
static bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
enum intel_display_power_domain domain)
{
struct i915_power_well *power_well;
bool is_enabled;
@ -1696,7 +1684,7 @@ static void icl_display_core_init(struct drm_i915_private *dev_priv,
intel_dmc_load_program(dev_priv);
/* Wa_14011508470:tgl,dg1,rkl,adl-s,adl-p,dg2 */
if (IS_DISPLAY_IP_RANGE(dev_priv, IP_VER(12, 0), IP_VER(13, 0)))
if (IS_DISPLAY_VER_FULL(dev_priv, IP_VER(12, 0), IP_VER(13, 0)))
intel_de_rmw(dev_priv, GEN11_CHICKEN_DCPR_2, 0,
DCPR_CLEAR_MEMSTAT_DIS | DCPR_SEND_RESP_IMM |
DCPR_MASK_LPMODE | DCPR_MASK_MAXLATENCY_MEMUP_CLR);

5
drivers/gpu/drm/i915/display/intel_display_power.h
View File

@ -183,13 +183,8 @@ void intel_display_power_resume(struct drm_i915_private *i915);
void intel_display_power_set_target_dc_state(struct drm_i915_private *dev_priv,
u32 state);
const char *
intel_display_power_domain_str(enum intel_display_power_domain domain);
bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
enum intel_display_power_domain domain);
bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
enum intel_display_power_domain domain);
intel_wakeref_t intel_display_power_get(struct drm_i915_private *dev_priv,
enum intel_display_power_domain domain);
intel_wakeref_t

4
drivers/gpu/drm/i915/display/intel_display_power_well.c
View File

@ -1176,9 +1176,9 @@ static void vlv_init_display_clock_gating(struct drm_i915_private *dev_priv)
MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
intel_de_write(dev_priv, CBR1_VLV, 0);
drm_WARN_ON(&dev_priv->drm, RUNTIME_INFO(dev_priv)->rawclk_freq == 0);
drm_WARN_ON(&dev_priv->drm, DISPLAY_RUNTIME_INFO(dev_priv)->rawclk_freq == 0);
intel_de_write(dev_priv, RAWCLK_FREQ_VLV,
DIV_ROUND_CLOSEST(RUNTIME_INFO(dev_priv)->rawclk_freq,
DIV_ROUND_CLOSEST(DISPLAY_RUNTIME_INFO(dev_priv)->rawclk_freq,
1000));
}

7
drivers/gpu/drm/i915/display/intel_display_types.h
View File

@ -1396,8 +1396,8 @@ struct intel_crtc_state {
/* Only valid on TGL+ */
enum transcoder mst_master_transcoder;
/* For DSB related info */
struct intel_dsb *dsb;
/* For DSB based color LUT updates */
struct intel_dsb *dsb_color_vblank, *dsb_color_commit;
u32 psr2_man_track_ctl;
@ -2206,6 +2206,8 @@ to_intel_frontbuffer(struct drm_framebuffer *fb)
*/
#define __drm_device_to_intel_display(p) \
(&to_i915(p)->display)
#define __intel_atomic_state_to_intel_display(p) \
__drm_device_to_intel_display((p)->base.dev)
#define __intel_connector_to_intel_display(p) \
__drm_device_to_intel_display((p)->base.dev)
#define __intel_crtc_to_intel_display(p) \
@ -2229,6 +2231,7 @@ to_intel_frontbuffer(struct drm_framebuffer *fb)
#define to_intel_display(p) \
_Generic(*p, \
__assoc(drm_device, p), \
__assoc(intel_atomic_state, p), \
__assoc(intel_connector, p), \
__assoc(intel_crtc, p), \
__assoc(intel_crtc_state, p), \

2
drivers/gpu/drm/i915/display/intel_dmc.c
View File

@ -391,7 +391,7 @@ static const struct stepping_info *
intel_get_stepping_info(struct drm_i915_private *i915,
struct stepping_info *si)
{
const char *step_name = intel_display_step_name(i915);
const char *step_name = intel_step_name(INTEL_DISPLAY_STEP(i915));
si->stepping = step_name[0];
si->substepping = step_name[1];

12
drivers/gpu/drm/i915/display/intel_dp.c
View File

@ -5999,6 +5999,18 @@ intel_dp_detect(struct drm_connector *connector,
else
status = connector_status_disconnected;
if (status != connector_status_disconnected &&
!intel_dp_mst_verify_dpcd_state(intel_dp))
/*
* This requires retrying detection for instance to re-enable
* the MST mode that got reset via a long HPD pulse. The retry
* will happen either via the hotplug handler's retry logic,
* ensured by setting the connector here to SST/disconnected,
* or via a userspace connector probing in response to the
* hotplug uevent sent when removing the MST connectors.
*/
status = connector_status_disconnected;
if (status == connector_status_disconnected) {
memset(&intel_dp->compliance, 0, sizeof(intel_dp->compliance));
memset(intel_connector->dp.dsc_dpcd, 0, sizeof(intel_connector->dp.dsc_dpcd));

4
drivers/gpu/drm/i915/display/intel_dp_aux.c
View File

@ -83,7 +83,7 @@ static u32 g4x_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
* The clock divider is based off the hrawclk, and would like to run at
* 2MHz. So, take the hrawclk value and divide by 2000 and use that
*/
return DIV_ROUND_CLOSEST(RUNTIME_INFO(i915)->rawclk_freq, 2000);
return DIV_ROUND_CLOSEST(DISPLAY_RUNTIME_INFO(i915)->rawclk_freq, 2000);
}
static u32 ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
@ -103,7 +103,7 @@ static u32 ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
if (dig_port->aux_ch == AUX_CH_A)
freq = i915->display.cdclk.hw.cdclk;
else
freq = RUNTIME_INFO(i915)->rawclk_freq;
freq = DISPLAY_RUNTIME_INFO(i915)->rawclk_freq;
return DIV_ROUND_CLOSEST(freq, 2000);
}

70
drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
View File

@ -109,7 +109,7 @@ static bool is_intel_tcon_cap(const u8 tcon_cap[4])
static bool
intel_dp_aux_supports_hdr_backlight(struct intel_connector *connector)
{
struct drm_i915_private *i915 = to_i915(connector->base.dev);
struct intel_display *display = to_intel_display(connector);
struct intel_dp *intel_dp = enc_to_intel_dp(connector->encoder);
struct drm_dp_aux *aux = &intel_dp->aux;
struct intel_panel *panel = &connector->panel;
@ -122,7 +122,8 @@ intel_dp_aux_supports_hdr_backlight(struct intel_connector *connector)
if (ret != sizeof(tcon_cap))
return false;
drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s] Detected %s HDR backlight interface version %d\n",
drm_dbg_kms(display->drm,
"[CONNECTOR:%d:%s] Detected %s HDR backlight interface version %d\n",
connector->base.base.id, connector->base.name,
is_intel_tcon_cap(tcon_cap) ? "Intel" : "unsupported", tcon_cap[0]);
@ -141,10 +142,10 @@ intel_dp_aux_supports_hdr_backlight(struct intel_connector *connector)
* HDR static metadata we need to start maintaining table of
* ranges for such panels.
*/
if (i915->display.params.enable_dpcd_backlight != INTEL_DP_AUX_BACKLIGHT_FORCE_INTEL &&
if (display->params.enable_dpcd_backlight != INTEL_DP_AUX_BACKLIGHT_FORCE_INTEL &&
!(connector->base.hdr_sink_metadata.hdmi_type1.metadata_type &
BIT(HDMI_STATIC_METADATA_TYPE1))) {
drm_info(&i915->drm,
drm_info(display->drm,
"[CONNECTOR:%d:%s] Panel is missing HDR static metadata. Possible support for Intel HDR backlight interface is not used. If your backlight controls don't work try booting with i915.enable_dpcd_backlight=%d. needs this, please file a _new_ bug report on drm/i915, see " FDO_BUG_URL " for details.\n",
connector->base.base.id, connector->base.name,
INTEL_DP_AUX_BACKLIGHT_FORCE_INTEL);
@ -170,14 +171,15 @@ intel_dp_aux_supports_hdr_backlight(struct intel_connector *connector)
static u32
intel_dp_aux_hdr_get_backlight(struct intel_connector *connector, enum pipe pipe)
{
struct drm_i915_private *i915 = to_i915(connector->base.dev);
struct intel_display *display = to_intel_display(connector);
struct intel_panel *panel = &connector->panel;
struct intel_dp *intel_dp = enc_to_intel_dp(connector->encoder);
u8 tmp;
u8 buf[2] = {};
if (drm_dp_dpcd_readb(&intel_dp->aux, INTEL_EDP_HDR_GETSET_CTRL_PARAMS, &tmp) != 1) {
drm_err(&i915->drm, "[CONNECTOR:%d:%s] Failed to read current backlight mode from DPCD\n",
drm_err(display->drm,
"[CONNECTOR:%d:%s] Failed to read current backlight mode from DPCD\n",
connector->base.base.id, connector->base.name);
return 0;
}
@ -195,7 +197,8 @@ intel_dp_aux_hdr_get_backlight(struct intel_connector *connector, enum pipe pipe
if (drm_dp_dpcd_read(&intel_dp->aux, INTEL_EDP_BRIGHTNESS_NITS_LSB, buf,
sizeof(buf)) != sizeof(buf)) {
drm_err(&i915->drm, "[CONNECTOR:%d:%s] Failed to read brightness from DPCD\n",
drm_err(display->drm,
"[CONNECTOR:%d:%s] Failed to read brightness from DPCD\n",
connector->base.base.id, connector->base.name);
return 0;
}
@ -253,8 +256,8 @@ static void
intel_dp_aux_write_content_luminance(struct intel_connector *connector,
struct hdr_output_metadata *hdr_metadata)
{
struct intel_display *display = to_intel_display(connector);
struct intel_dp *intel_dp = enc_to_intel_dp(connector->encoder);
struct drm_i915_private *i915 = to_i915(connector->base.dev);
int ret;
u8 buf[4];
@ -270,7 +273,7 @@ intel_dp_aux_write_content_luminance(struct intel_connector *connector,
INTEL_EDP_HDR_CONTENT_LUMINANCE,
buf, sizeof(buf));
if (ret < 0)
drm_dbg_kms(&i915->drm,
drm_dbg_kms(display->drm,
"Content Luminance DPCD reg write failed, err:-%d\n",
ret);
}
@ -280,7 +283,7 @@ intel_dp_aux_fill_hdr_tcon_params(const struct drm_connector_state *conn_state,
{
struct intel_connector *connector = to_intel_connector(conn_state->connector);
struct intel_panel *panel = &connector->panel;
struct drm_i915_private *i915 = to_i915(connector->base.dev);
struct intel_display *display = to_intel_display(connector);
/*
* According to spec segmented backlight needs to be set whenever panel is in
@ -291,7 +294,7 @@ intel_dp_aux_fill_hdr_tcon_params(const struct drm_connector_state *conn_state,
*ctrl |= INTEL_EDP_HDR_TCON_2084_DECODE_ENABLE;
}
if (DISPLAY_VER(i915) < 11)
if (DISPLAY_VER(display) < 11)
*ctrl &= ~INTEL_EDP_HDR_TCON_TONE_MAPPING_ENABLE;
if (panel->backlight.edp.intel_cap.supports_2020_gamut &&
@ -311,9 +314,9 @@ static void
intel_dp_aux_hdr_enable_backlight(const struct intel_crtc_state *crtc_state,
const struct drm_connector_state *conn_state, u32 level)
{
struct intel_display *display = to_intel_display(crtc_state);
struct intel_connector *connector = to_intel_connector(conn_state->connector);
struct intel_panel *panel = &connector->panel;
struct drm_i915_private *i915 = to_i915(connector->base.dev);
struct intel_dp *intel_dp = enc_to_intel_dp(connector->encoder);
struct hdr_output_metadata *hdr_metadata;
int ret;
@ -323,7 +326,8 @@ intel_dp_aux_hdr_enable_backlight(const struct intel_crtc_state *crtc_state,
ret = drm_dp_dpcd_readb(&intel_dp->aux, INTEL_EDP_HDR_GETSET_CTRL_PARAMS, &old_ctrl);
if (ret != 1) {
drm_err(&i915->drm, "[CONNECTOR:%d:%s] Failed to read current backlight control mode: %d\n",
drm_err(display->drm,
"[CONNECTOR:%d:%s] Failed to read current backlight control mode: %d\n",
connector->base.base.id, connector->base.name, ret);
return;
}
@ -346,7 +350,8 @@ intel_dp_aux_hdr_enable_backlight(const struct intel_crtc_state *crtc_state,
if (ctrl != old_ctrl &&
drm_dp_dpcd_writeb(&intel_dp->aux, INTEL_EDP_HDR_GETSET_CTRL_PARAMS, ctrl) != 1)
drm_err(&i915->drm, "[CONNECTOR:%d:%s] Failed to configure DPCD brightness controls\n",
drm_err(display->drm,
"[CONNECTOR:%d:%s] Failed to configure DPCD brightness controls\n",
connector->base.base.id, connector->base.name);
if (intel_dp_in_hdr_mode(conn_state)) {
@ -377,7 +382,7 @@ static const char *dpcd_vs_pwm_str(bool aux)
static void
intel_dp_aux_write_panel_luminance_override(struct intel_connector *connector)
{
struct drm_i915_private *i915 = to_i915(connector->base.dev);
struct intel_display *display = to_intel_display(connector);
struct intel_panel *panel = &connector->panel;
struct intel_dp *intel_dp = enc_to_intel_dp(connector->encoder);
int ret;
@ -392,7 +397,7 @@ intel_dp_aux_write_panel_luminance_override(struct intel_connector *connector)
INTEL_EDP_HDR_PANEL_LUMINANCE_OVERRIDE,
buf, sizeof(buf));
if (ret < 0)
drm_dbg_kms(&i915->drm,
drm_dbg_kms(display->drm,
"Panel Luminance DPCD reg write failed, err:-%d\n",
ret);
}
@ -400,20 +405,21 @@ intel_dp_aux_write_panel_luminance_override(struct intel_connector *connector)
static int
intel_dp_aux_hdr_setup_backlight(struct intel_connector *connector, enum pipe pipe)
{
struct drm_i915_private *i915 = to_i915(connector->base.dev);
struct intel_display *display = to_intel_display(connector);
struct intel_panel *panel = &connector->panel;
struct drm_luminance_range_info *luminance_range =
&connector->base.display_info.luminance_range;
int ret;
drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s] SDR backlight is controlled through %s\n",
drm_dbg_kms(display->drm,
"[CONNECTOR:%d:%s] SDR backlight is controlled through %s\n",
connector->base.base.id, connector->base.name,
dpcd_vs_pwm_str(panel->backlight.edp.intel_cap.sdr_uses_aux));
if (!panel->backlight.edp.intel_cap.sdr_uses_aux) {
ret = panel->backlight.pwm_funcs->setup(connector, pipe);
if (ret < 0) {
drm_err(&i915->drm,
drm_err(display->drm,
"[CONNECTOR:%d:%s] Failed to setup SDR backlight controls through PWM: %d\n",
connector->base.base.id, connector->base.name, ret);
return ret;
@ -430,7 +436,8 @@ intel_dp_aux_hdr_setup_backlight(struct intel_connector *connector, enum pipe pi
intel_dp_aux_write_panel_luminance_override(connector);
drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s] Using AUX HDR interface for backlight control (range %d..%d)\n",
drm_dbg_kms(display->drm,
"[CONNECTOR:%d:%s] Using AUX HDR interface for backlight control (range %d..%d)\n",
connector->base.base.id, connector->base.name,
panel->backlight.min, panel->backlight.max);
@ -501,9 +508,9 @@ static void intel_dp_aux_vesa_disable_backlight(const struct drm_connector_state
static int intel_dp_aux_vesa_setup_backlight(struct intel_connector *connector, enum pipe pipe)
{
struct intel_display *display = to_intel_display(connector);
struct intel_dp *intel_dp = intel_attached_dp(connector);
struct intel_panel *panel = &connector->panel;
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
u16 current_level;
u8 current_mode;
int ret;
@ -514,17 +521,19 @@ static int intel_dp_aux_vesa_setup_backlight(struct intel_connector *connector,
if (ret < 0)
return ret;
drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s] AUX VESA backlight enable is controlled through %s\n",
drm_dbg_kms(display->drm,
"[CONNECTOR:%d:%s] AUX VESA backlight enable is controlled through %s\n",
connector->base.base.id, connector->base.name,
dpcd_vs_pwm_str(panel->backlight.edp.vesa.info.aux_enable));
drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s] AUX VESA backlight level is controlled through %s\n",
drm_dbg_kms(display->drm,
"[CONNECTOR:%d:%s] AUX VESA backlight level is controlled through %s\n",
connector->base.base.id, connector->base.name,
dpcd_vs_pwm_str(panel->backlight.edp.vesa.info.aux_set));
if (!panel->backlight.edp.vesa.info.aux_set || !panel->backlight.edp.vesa.info.aux_enable) {
ret = panel->backlight.pwm_funcs->setup(connector, pipe);
if (ret < 0) {
drm_err(&i915->drm,
drm_err(display->drm,
"[CONNECTOR:%d:%s] Failed to setup PWM backlight controls for eDP backlight: %d\n",
connector->base.base.id, connector->base.name, ret);
return ret;
@ -553,7 +562,8 @@ static int intel_dp_aux_vesa_setup_backlight(struct intel_connector *connector,
}
}
drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s] Using AUX VESA interface for backlight control\n",
drm_dbg_kms(display->drm,
"[CONNECTOR:%d:%s] Using AUX VESA interface for backlight control\n",
connector->base.base.id, connector->base.name);
return 0;
@ -562,11 +572,12 @@ static int intel_dp_aux_vesa_setup_backlight(struct intel_connector *connector,
static bool
intel_dp_aux_supports_vesa_backlight(struct intel_connector *connector)
{
struct intel_display *display = to_intel_display(connector);
struct intel_dp *intel_dp = intel_attached_dp(connector);
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
if (drm_edp_backlight_supported(intel_dp->edp_dpcd)) {
drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s] AUX Backlight Control Supported!\n",
drm_dbg_kms(display->drm,
"[CONNECTOR:%d:%s] AUX Backlight Control Supported!\n",
connector->base.base.id, connector->base.name);
return true;
}
@ -591,16 +602,15 @@ static const struct intel_panel_bl_funcs intel_dp_vesa_bl_funcs = {
int intel_dp_aux_init_backlight_funcs(struct intel_connector *connector)
{
struct intel_display *display = to_intel_display(connector);
struct drm_device *dev = connector->base.dev;
struct intel_panel *panel = &connector->panel;
struct intel_dp *intel_dp = enc_to_intel_dp(connector->encoder);
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
bool try_intel_interface = false, try_vesa_interface = false;
/* Check the VBT and user's module parameters to figure out which
* interfaces to probe
*/
switch (i915->display.params.enable_dpcd_backlight) {
switch (display->params.enable_dpcd_backlight) {
case INTEL_DP_AUX_BACKLIGHT_OFF:
return -ENODEV;
case INTEL_DP_AUX_BACKLIGHT_AUTO:

40
drivers/gpu/drm/i915/display/intel_dp_mst.c
View File

@ -2062,3 +2062,43 @@ void intel_dp_mst_prepare_probe(struct intel_dp *intel_dp)
intel_mst_set_probed_link_params(intel_dp, link_rate, lane_count);
}
/*
* intel_dp_mst_verify_dpcd_state - verify the MST SW enabled state wrt. the DPCD
* @intel_dp: DP port object
*
* Verify if @intel_dp's MST enabled SW state matches the corresponding DPCD
* state. A long HPD pulse - not long enough to be detected as a disconnected
* state - could've reset the DPCD state, which requires tearing
* down/recreating the MST topology.
*
* Returns %true if the SW MST enabled and DPCD states match, %false
* otherwise.
*/
bool intel_dp_mst_verify_dpcd_state(struct intel_dp *intel_dp)
{
struct intel_display *display = to_intel_display(intel_dp);
struct intel_connector *connector = intel_dp->attached_connector;
struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
struct intel_encoder *encoder = &dig_port->base;
int ret;
u8 val;
if (!intel_dp->is_mst)
return true;
ret = drm_dp_dpcd_readb(intel_dp->mst_mgr.aux, DP_MSTM_CTRL, &val);
/* Adjust the expected register value for SST + SideBand. */
if (ret < 0 || val != (DP_MST_EN | DP_UP_REQ_EN | DP_UPSTREAM_IS_SRC)) {
drm_dbg_kms(display->drm,
"[CONNECTOR:%d:%s][ENCODER:%d:%s] MST mode got reset, removing topology (ret=%d, ctrl=0x%02x)\n",
connector->base.base.id, connector->base.name,
encoder->base.base.id, encoder->base.name,
ret, val);
return false;
}
return true;
}

1
drivers/gpu/drm/i915/display/intel_dp_mst.h
View File

@ -28,5 +28,6 @@ int intel_dp_mst_atomic_check_link(struct intel_atomic_state *state,
bool intel_dp_mst_crtc_needs_modeset(struct intel_atomic_state *state,
struct intel_crtc *crtc);
void intel_dp_mst_prepare_probe(struct intel_dp *intel_dp);
bool intel_dp_mst_verify_dpcd_state(struct intel_dp *intel_dp);
#endif /* __INTEL_DP_MST_H__ */

3
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
View File

@ -3339,6 +3339,7 @@ static int icl_get_combo_phy_dpll(struct intel_atomic_state *state,
struct intel_crtc *crtc,
struct intel_encoder *encoder)
{
struct intel_display *display = to_intel_display(crtc);
struct drm_i915_private *i915 = to_i915(crtc->base.dev);
struct intel_crtc_state *crtc_state =
intel_atomic_get_new_crtc_state(state, crtc);
@ -3379,7 +3380,7 @@ static int icl_get_combo_phy_dpll(struct intel_atomic_state *state,
}
/* Eliminate DPLLs from consideration if reserved by HTI */
dpll_mask &= ~intel_hti_dpll_mask(i915);
dpll_mask &= ~intel_hti_dpll_mask(display);
port_dpll->pll = intel_find_shared_dpll(state, crtc,
&port_dpll->hw_state,

325
drivers/gpu/drm/i915/display/intel_dsb.c
View File

@ -6,6 +6,7 @@
#include "i915_drv.h"
#include "i915_irq.h"
#include "i915_reg.h"
#include "intel_crtc.h"
#include "intel_de.h"
#include "intel_display_types.h"
@ -42,7 +43,8 @@ struct intel_dsb {
*/
unsigned int ins_start_offset;
int dewake_scanline;
u32 chicken;
int hw_dewake_scanline;
};
/**
@ -82,6 +84,93 @@ struct intel_dsb {
#define DSB_OPCODE_POLL 0xA
/* see DSB_REG_VALUE_MASK */
static bool pre_commit_is_vrr_active(struct intel_atomic_state *state,
struct intel_crtc *crtc)
{
const struct intel_crtc_state *old_crtc_state =
intel_atomic_get_old_crtc_state(state, crtc);
const struct intel_crtc_state *new_crtc_state =
intel_atomic_get_new_crtc_state(state, crtc);
/* VRR will be enabled afterwards, if necessary */
if (intel_crtc_needs_modeset(new_crtc_state))
return false;
/* VRR will have been disabled during intel_pre_plane_update() */
return old_crtc_state->vrr.enable && !intel_crtc_vrr_disabling(state, crtc);
}
static const struct intel_crtc_state *
pre_commit_crtc_state(struct intel_atomic_state *state,
struct intel_crtc *crtc)
{
const struct intel_crtc_state *old_crtc_state =
intel_atomic_get_old_crtc_state(state, crtc);
const struct intel_crtc_state *new_crtc_state =
intel_atomic_get_new_crtc_state(state, crtc);
/*
* During fastsets/etc. the transcoder is still
* running with the old timings at this point.
*/
if (intel_crtc_needs_modeset(new_crtc_state))
return new_crtc_state;
else
return old_crtc_state;
}
static int dsb_vtotal(struct intel_atomic_state *state,
struct intel_crtc *crtc)
{
const struct intel_crtc_state *crtc_state = pre_commit_crtc_state(state, crtc);
if (pre_commit_is_vrr_active(state, crtc))
return crtc_state->vrr.vmax;
else
return intel_mode_vtotal(&crtc_state->hw.adjusted_mode);
}
static int dsb_dewake_scanline_start(struct intel_atomic_state *state,
struct intel_crtc *crtc)
{
const struct intel_crtc_state *crtc_state = pre_commit_crtc_state(state, crtc);
struct drm_i915_private *i915 = to_i915(state->base.dev);
unsigned int latency = skl_watermark_max_latency(i915, 0);
return intel_mode_vdisplay(&crtc_state->hw.adjusted_mode) -
intel_usecs_to_scanlines(&crtc_state->hw.adjusted_mode, latency);
}
static int dsb_dewake_scanline_end(struct intel_atomic_state *state,
struct intel_crtc *crtc)
{
const struct intel_crtc_state *crtc_state = pre_commit_crtc_state(state, crtc);
return intel_mode_vdisplay(&crtc_state->hw.adjusted_mode);
}
static int dsb_scanline_to_hw(struct intel_atomic_state *state,
struct intel_crtc *crtc, int scanline)
{
const struct intel_crtc_state *crtc_state = pre_commit_crtc_state(state, crtc);
int vtotal = dsb_vtotal(state, crtc);
return (scanline + vtotal - intel_crtc_scanline_offset(crtc_state)) % vtotal;
}
static u32 dsb_chicken(struct intel_atomic_state *state,
struct intel_crtc *crtc)
{
if (pre_commit_is_vrr_active(state, crtc))
return DSB_SKIP_WAITS_EN |
DSB_CTRL_WAIT_SAFE_WINDOW |
DSB_CTRL_NO_WAIT_VBLANK |
DSB_INST_WAIT_SAFE_WINDOW |
DSB_INST_NO_WAIT_VBLANK;
else
return DSB_SKIP_WAITS_EN;
}
static bool assert_dsb_has_room(struct intel_dsb *dsb)
{
struct intel_crtc *crtc = dsb->crtc;
@ -281,6 +370,79 @@ void intel_dsb_nonpost_end(struct intel_dsb *dsb)
intel_dsb_noop(dsb, 4);
}
static void intel_dsb_emit_wait_dsl(struct intel_dsb *dsb,
u32 opcode, int lower, int upper)
{
u64 window = ((u64)upper << DSB_SCANLINE_UPPER_SHIFT) |
((u64)lower << DSB_SCANLINE_LOWER_SHIFT);
intel_dsb_emit(dsb, lower_32_bits(window),
(opcode << DSB_OPCODE_SHIFT) |
upper_32_bits(window));
}
static void intel_dsb_wait_dsl(struct intel_atomic_state *state,
struct intel_dsb *dsb,
int lower_in, int upper_in,
int lower_out, int upper_out)
{
struct intel_crtc *crtc = dsb->crtc;
lower_in = dsb_scanline_to_hw(state, crtc, lower_in);
upper_in = dsb_scanline_to_hw(state, crtc, upper_in);
lower_out = dsb_scanline_to_hw(state, crtc, lower_out);
upper_out = dsb_scanline_to_hw(state, crtc, upper_out);
if (upper_in >= lower_in)
intel_dsb_emit_wait_dsl(dsb, DSB_OPCODE_WAIT_DSL_IN,
lower_in, upper_in);
else if (upper_out >= lower_out)
intel_dsb_emit_wait_dsl(dsb, DSB_OPCODE_WAIT_DSL_OUT,
lower_out, upper_out);
else
drm_WARN_ON(crtc->base.dev, 1); /* assert_dsl_ok() should have caught it already */
}
static void assert_dsl_ok(struct intel_atomic_state *state,
struct intel_dsb *dsb,
int start, int end)
{
struct intel_crtc *crtc = dsb->crtc;
int vtotal = dsb_vtotal(state, crtc);
/*
* Waiting for the entire frame doesn't make sense,
* (IN==don't wait, OUT=wait forever).
*/
drm_WARN(crtc->base.dev, (end - start + vtotal) % vtotal == vtotal - 1,
"[CRTC:%d:%s] DSB %d bad scanline window wait: %d-%d (vt=%d)\n",
crtc->base.base.id, crtc->base.name, dsb->id,
start, end, vtotal);
}
void intel_dsb_wait_scanline_in(struct intel_atomic_state *state,
struct intel_dsb *dsb,
int start, int end)
{
assert_dsl_ok(state, dsb, start, end);
intel_dsb_wait_dsl(state, dsb,
start, end,
end + 1, start - 1);
}
void intel_dsb_wait_scanline_out(struct intel_atomic_state *state,
struct intel_dsb *dsb,
int start, int end)
{
assert_dsl_ok(state, dsb, start, end);
intel_dsb_wait_dsl(state, dsb,
end + 1, start - 1,
start, end);
}
static void intel_dsb_align_tail(struct intel_dsb *dsb)
{
u32 aligned_tail, tail;
@ -302,8 +464,10 @@ void intel_dsb_finish(struct intel_dsb *dsb)
/*
* DSB_FORCE_DEWAKE remains active even after DSB is
* disabled, so make sure to clear it (if set during
* intel_dsb_commit()).
* intel_dsb_commit()). And clear DSB_ENABLE_DEWAKE as
* well for good measure.
*/
intel_dsb_reg_write(dsb, DSB_PMCTRL(crtc->pipe, dsb->id), 0);
intel_dsb_reg_write_masked(dsb, DSB_PMCTRL_2(crtc->pipe, dsb->id),
DSB_FORCE_DEWAKE, 0);
@ -312,35 +476,109 @@ void intel_dsb_finish(struct intel_dsb *dsb)
intel_dsb_buffer_flush_map(&dsb->dsb_buf);
}
static int intel_dsb_dewake_scanline(const struct intel_crtc_state *crtc_state)
static u32 dsb_error_int_status(struct intel_display *display)
{
struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
unsigned int latency = skl_watermark_max_latency(i915, 0);
int vblank_start;
u32 errors;
if (crtc_state->vrr.enable)
vblank_start = intel_vrr_vmin_vblank_start(crtc_state);
else
vblank_start = intel_mode_vblank_start(adjusted_mode);
errors = DSB_GTT_FAULT_INT_STATUS |
DSB_RSPTIMEOUT_INT_STATUS |
DSB_POLL_ERR_INT_STATUS;
return max(0, vblank_start - intel_usecs_to_scanlines(adjusted_mode, latency));
/*
* All the non-existing status bits operate as
* normal r/w bits, so any attempt to clear them
* will just end up setting them. Never do that so
* we won't mistake them for actual error interrupts.
*/
if (DISPLAY_VER(display) >= 14)
errors |= DSB_ATS_FAULT_INT_STATUS;
return errors;
}
static u32 dsb_chicken(struct intel_crtc *crtc)
static u32 dsb_error_int_en(struct intel_display *display)
{
if (crtc->mode_flags & I915_MODE_FLAG_VRR)
return DSB_SKIP_WAITS_EN |
DSB_CTRL_WAIT_SAFE_WINDOW |
DSB_CTRL_NO_WAIT_VBLANK |
DSB_INST_WAIT_SAFE_WINDOW |
DSB_INST_NO_WAIT_VBLANK;
else
return DSB_SKIP_WAITS_EN;
u32 errors;
errors = DSB_GTT_FAULT_INT_EN |
DSB_RSPTIMEOUT_INT_EN |
DSB_POLL_ERR_INT_EN;
if (DISPLAY_VER(display) >= 14)
errors |= DSB_ATS_FAULT_INT_EN;
return errors;
}
static void _intel_dsb_chain(struct intel_atomic_state *state,
struct intel_dsb *dsb,
struct intel_dsb *chained_dsb,
u32 ctrl)
{
struct intel_display *display = to_intel_display(state->base.dev);
struct intel_crtc *crtc = dsb->crtc;
enum pipe pipe = crtc->pipe;
u32 tail;
if (drm_WARN_ON(display->drm, dsb->id == chained_dsb->id))
return;
tail = chained_dsb->free_pos * 4;
if (drm_WARN_ON(display->drm, !IS_ALIGNED(tail, CACHELINE_BYTES)))
return;
intel_dsb_reg_write(dsb, DSB_CTRL(pipe, chained_dsb->id),
ctrl | DSB_ENABLE);
intel_dsb_reg_write(dsb, DSB_CHICKEN(pipe, chained_dsb->id),
dsb_chicken(state, crtc));
intel_dsb_reg_write(dsb, DSB_INTERRUPT(pipe, chained_dsb->id),
dsb_error_int_status(display) | DSB_PROG_INT_STATUS |
dsb_error_int_en(display));
if (ctrl & DSB_WAIT_FOR_VBLANK) {
int dewake_scanline = dsb_dewake_scanline_start(state, crtc);
int hw_dewake_scanline = dsb_scanline_to_hw(state, crtc, dewake_scanline);
intel_dsb_reg_write(dsb, DSB_PMCTRL(pipe, chained_dsb->id),
DSB_ENABLE_DEWAKE |
DSB_SCANLINE_FOR_DEWAKE(hw_dewake_scanline));
}
intel_dsb_reg_write(dsb, DSB_HEAD(pipe, chained_dsb->id),
intel_dsb_buffer_ggtt_offset(&chained_dsb->dsb_buf));
intel_dsb_reg_write(dsb, DSB_TAIL(pipe, chained_dsb->id),
intel_dsb_buffer_ggtt_offset(&chained_dsb->dsb_buf) + tail);
if (ctrl & DSB_WAIT_FOR_VBLANK) {
/*
* Keep DEwake alive via the first DSB, in
* case we're already past dewake_scanline,
* and thus DSB_ENABLE_DEWAKE on the second
* DSB won't do its job.
*/
intel_dsb_reg_write_masked(dsb, DSB_PMCTRL_2(pipe, dsb->id),
DSB_FORCE_DEWAKE, DSB_FORCE_DEWAKE);
intel_dsb_wait_scanline_out(state, dsb,
dsb_dewake_scanline_start(state, crtc),
dsb_dewake_scanline_end(state, crtc));
}
}
void intel_dsb_chain(struct intel_atomic_state *state,
struct intel_dsb *dsb,
struct intel_dsb *chained_dsb,
bool wait_for_vblank)
{
_intel_dsb_chain(state, dsb, chained_dsb,
wait_for_vblank ? DSB_WAIT_FOR_VBLANK : 0);
}
static void _intel_dsb_commit(struct intel_dsb *dsb, u32 ctrl,
int dewake_scanline)
int hw_dewake_scanline)
{
struct intel_crtc *crtc = dsb->crtc;
struct intel_display *display = to_intel_display(crtc->base.dev);
@ -361,15 +599,17 @@ static void _intel_dsb_commit(struct intel_dsb *dsb, u32 ctrl,
ctrl | DSB_ENABLE);
intel_de_write_fw(display, DSB_CHICKEN(pipe, dsb->id),
dsb_chicken(crtc));
dsb->chicken);
intel_de_write_fw(display, DSB_INTERRUPT(pipe, dsb->id),
dsb_error_int_status(display) | DSB_PROG_INT_STATUS |
dsb_error_int_en(display));
intel_de_write_fw(display, DSB_HEAD(pipe, dsb->id),
intel_dsb_buffer_ggtt_offset(&dsb->dsb_buf));
if (dewake_scanline >= 0) {
int diff, hw_dewake_scanline;
hw_dewake_scanline = intel_crtc_scanline_to_hw(crtc, dewake_scanline);
if (hw_dewake_scanline >= 0) {
int diff, position;
intel_de_write_fw(display, DSB_PMCTRL(pipe, dsb->id),
DSB_ENABLE_DEWAKE |
@ -379,7 +619,9 @@ static void _intel_dsb_commit(struct intel_dsb *dsb, u32 ctrl,
* Force DEwake immediately if we're already past
* or close to racing past the target scanline.
*/
diff = dewake_scanline - intel_get_crtc_scanline(crtc);
position = intel_de_read_fw(display, PIPEDSL(display, pipe)) & PIPEDSL_LINE_MASK;
diff = hw_dewake_scanline - position;
intel_de_write_fw(display, DSB_PMCTRL_2(pipe, dsb->id),
(diff >= 0 && diff < 5 ? DSB_FORCE_DEWAKE : 0) |
DSB_BLOCK_DEWAKE_EXTENSION);
@ -401,7 +643,7 @@ void intel_dsb_commit(struct intel_dsb *dsb,
{
_intel_dsb_commit(dsb,
wait_for_vblank ? DSB_WAIT_FOR_VBLANK : 0,
wait_for_vblank ? dsb->dewake_scanline : -1);
wait_for_vblank ? dsb->hw_dewake_scanline : -1);
}
void intel_dsb_wait(struct intel_dsb *dsb)
@ -430,6 +672,9 @@ void intel_dsb_wait(struct intel_dsb *dsb)
dsb->free_pos = 0;
dsb->ins_start_offset = 0;
intel_de_write_fw(display, DSB_CTRL(pipe, dsb->id), 0);
intel_de_write_fw(display, DSB_INTERRUPT(pipe, dsb->id),
dsb_error_int_status(display) | DSB_PROG_INT_STATUS);
}
/**
@ -451,8 +696,6 @@ struct intel_dsb *intel_dsb_prepare(struct intel_atomic_state *state,
unsigned int max_cmds)
{
struct drm_i915_private *i915 = to_i915(state->base.dev);
const struct intel_crtc_state *crtc_state =
intel_atomic_get_new_crtc_state(state, crtc);
intel_wakeref_t wakeref;
struct intel_dsb *dsb;
unsigned int size;
@ -486,7 +729,10 @@ struct intel_dsb *intel_dsb_prepare(struct intel_atomic_state *state,
dsb->size = size / 4; /* in dwords */
dsb->free_pos = 0;
dsb->ins_start_offset = 0;
dsb->dewake_scanline = intel_dsb_dewake_scanline(crtc_state);
dsb->chicken = dsb_chicken(state, crtc);
dsb->hw_dewake_scanline =
dsb_scanline_to_hw(state, crtc, dsb_dewake_scanline_start(state, crtc));
return dsb;
@ -513,3 +759,18 @@ void intel_dsb_cleanup(struct intel_dsb *dsb)
intel_dsb_buffer_cleanup(&dsb->dsb_buf);
kfree(dsb);
}
void intel_dsb_irq_handler(struct intel_display *display,
enum pipe pipe, enum intel_dsb_id dsb_id)
{
struct intel_crtc *crtc = intel_crtc_for_pipe(to_i915(display->drm), pipe);
u32 tmp, errors;
tmp = intel_de_read_fw(display, DSB_INTERRUPT(pipe, dsb_id));
intel_de_write_fw(display, DSB_INTERRUPT(pipe, dsb_id), tmp);
errors = tmp & dsb_error_int_status(display);
if (errors)
drm_err(display->drm, "[CRTC:%d:%s] DSB %d error interrupt: 0x%x\n",
crtc->base.base.id, crtc->base.name, dsb_id, errors);
}

16
drivers/gpu/drm/i915/display/intel_dsb.h
View File

@ -13,8 +13,11 @@
struct intel_atomic_state;
struct intel_crtc;
struct intel_crtc_state;
struct intel_display;
struct intel_dsb;
enum pipe;
enum intel_dsb_id {
INTEL_DSB_0,
INTEL_DSB_1,
@ -36,9 +39,22 @@ void intel_dsb_reg_write_masked(struct intel_dsb *dsb,
void intel_dsb_noop(struct intel_dsb *dsb, int count);
void intel_dsb_nonpost_start(struct intel_dsb *dsb);
void intel_dsb_nonpost_end(struct intel_dsb *dsb);
void intel_dsb_wait_scanline_in(struct intel_atomic_state *state,
struct intel_dsb *dsb,
int lower, int upper);
void intel_dsb_wait_scanline_out(struct intel_atomic_state *state,
struct intel_dsb *dsb,
int lower, int upper);
void intel_dsb_chain(struct intel_atomic_state *state,
struct intel_dsb *dsb,
struct intel_dsb *chained_dsb,
bool wait_for_vblank);
void intel_dsb_commit(struct intel_dsb *dsb,
bool wait_for_vblank);
void intel_dsb_wait(struct intel_dsb *dsb);
void intel_dsb_irq_handler(struct intel_display *display,
enum pipe pipe, enum intel_dsb_id dsb_id);
#endif

36
drivers/gpu/drm/i915/display/intel_fb.c
View File

@ -163,6 +163,14 @@ struct intel_modifier_desc {
static const struct intel_modifier_desc intel_modifiers[] = {
{
.modifier = I915_FORMAT_MOD_4_TILED_LNL_CCS,
.display_ver = { 20, -1 },
.plane_caps = INTEL_PLANE_CAP_TILING_4,
}, {
.modifier = I915_FORMAT_MOD_4_TILED_BMG_CCS,
.display_ver = { 14, -1 },
.plane_caps = INTEL_PLANE_CAP_TILING_4 | INTEL_PLANE_CAP_NEED64K_PHYS,
}, {
.modifier = I915_FORMAT_MOD_4_TILED_MTL_MC_CCS,
.display_ver = { 14, 14 },
.plane_caps = INTEL_PLANE_CAP_TILING_4 | INTEL_PLANE_CAP_CCS_MC,
@ -412,6 +420,24 @@ bool intel_fb_is_mc_ccs_modifier(u64 modifier)
INTEL_PLANE_CAP_CCS_MC);
}
/**
* intel_fb_needs_64k_phys: Check if modifier requires 64k physical placement.
* @modifier: Modifier to check
*
* Returns:
* Returns %true if @modifier requires 64k aligned physical pages.
*/
bool intel_fb_needs_64k_phys(u64 modifier)
{
const struct intel_modifier_desc *md = lookup_modifier_or_null(modifier);
if (!md)
return false;
return plane_caps_contain_any(md->plane_caps,
INTEL_PLANE_CAP_NEED64K_PHYS);
}
static bool check_modifier_display_ver_range(const struct intel_modifier_desc *md,
u8 display_ver_from, u8 display_ver_until)
{
@ -437,6 +463,14 @@ static bool plane_has_modifier(struct drm_i915_private *i915,
HAS_FLAT_CCS(i915) != !md->ccs.packed_aux_planes)
return false;
if (md->modifier == I915_FORMAT_MOD_4_TILED_BMG_CCS &&
(GRAPHICS_VER(i915) < 20 || !IS_DGFX(i915)))
return false;
if (md->modifier == I915_FORMAT_MOD_4_TILED_LNL_CCS &&
(GRAPHICS_VER(i915) < 20 || IS_DGFX(i915)))
return false;
return true;
}
@ -653,6 +687,8 @@ intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane)
return 128;
else
return 512;
case I915_FORMAT_MOD_4_TILED_BMG_CCS:
case I915_FORMAT_MOD_4_TILED_LNL_CCS:
case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS:
case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC:
case I915_FORMAT_MOD_4_TILED_DG2_MC_CCS:

2
drivers/gpu/drm/i915/display/intel_fb.h
View File

@ -28,11 +28,13 @@ struct intel_plane_state;
#define INTEL_PLANE_CAP_TILING_Y BIT(4)
#define INTEL_PLANE_CAP_TILING_Yf BIT(5)
#define INTEL_PLANE_CAP_TILING_4 BIT(6)
#define INTEL_PLANE_CAP_NEED64K_PHYS BIT(7)
bool intel_fb_is_tiled_modifier(u64 modifier);
bool intel_fb_is_ccs_modifier(u64 modifier);
bool intel_fb_is_rc_ccs_cc_modifier(u64 modifier);
bool intel_fb_is_mc_ccs_modifier(u64 modifier);
bool intel_fb_needs_64k_phys(u64 modifier);
bool intel_fb_is_ccs_aux_plane(const struct drm_framebuffer *fb, int color_plane);
int intel_fb_rc_ccs_cc_plane(const struct drm_framebuffer *fb);

2
drivers/gpu/drm/i915/display/intel_fbc.c
View File

@ -1346,7 +1346,7 @@ static int intel_fbc_check_plane(struct intel_atomic_state *state,
/* Wa_14016291713 */
if ((IS_DISPLAY_VER(display, 12, 13) ||
IS_DISPLAY_IP_STEP(i915, IP_VER(14, 0), STEP_A0, STEP_C0)) &&
IS_DISPLAY_VER_STEP(i915, IP_VER(14, 0), STEP_A0, STEP_C0)) &&
crtc_state->has_psr && !crtc_state->has_panel_replay) {
plane_state->no_fbc_reason = "PSR1 enabled (Wa_14016291713)";
return 0;

6
drivers/gpu/drm/i915/display/intel_hdcp.c
View File

@ -42,11 +42,11 @@ intel_hdcp_disable_hdcp_line_rekeying(struct intel_encoder *encoder,
return;
if (DISPLAY_VER(dev_priv) >= 14) {
if (IS_DISPLAY_IP_STEP(dev_priv, IP_VER(14, 0), STEP_D0, STEP_FOREVER))
if (IS_DISPLAY_VER_STEP(dev_priv, IP_VER(14, 0), STEP_D0, STEP_FOREVER))
intel_de_rmw(dev_priv, MTL_CHICKEN_TRANS(hdcp->cpu_transcoder),
0, HDCP_LINE_REKEY_DISABLE);
else if (IS_DISPLAY_IP_STEP(dev_priv, IP_VER(14, 1), STEP_B0, STEP_FOREVER) ||
IS_DISPLAY_IP_STEP(dev_priv, IP_VER(20, 0), STEP_B0, STEP_FOREVER))
else if (IS_DISPLAY_VER_STEP(dev_priv, IP_VER(14, 1), STEP_B0, STEP_FOREVER) ||
IS_DISPLAY_VER_STEP(dev_priv, IP_VER(20, 0), STEP_B0, STEP_FOREVER))
intel_de_rmw(dev_priv,
TRANS_DDI_FUNC_CTL(dev_priv, hdcp->cpu_transcoder),
0, TRANS_DDI_HDCP_LINE_REKEY_DISABLE);

20
drivers/gpu/drm/i915/display/intel_hti.c
View File

@ -9,33 +9,33 @@
#include "intel_hti.h"
#include "intel_hti_regs.h"
void intel_hti_init(struct drm_i915_private *i915)
void intel_hti_init(struct intel_display *display)
{
/*
* If the platform has HTI, we need to find out whether it has reserved
* any display resources before we create our display outputs.
*/
if (DISPLAY_INFO(i915)->has_hti)
i915->display.hti.state = intel_de_read(i915, HDPORT_STATE);
if (DISPLAY_INFO(display)->has_hti)
display->hti.state = intel_de_read(display, HDPORT_STATE);
}
bool intel_hti_uses_phy(struct drm_i915_private *i915, enum phy phy)
bool intel_hti_uses_phy(struct intel_display *display, enum phy phy)
{
if (drm_WARN_ON(&i915->drm, phy == PHY_NONE))
if (drm_WARN_ON(display->drm, phy == PHY_NONE))
return false;
return i915->display.hti.state & HDPORT_ENABLED &&
i915->display.hti.state & HDPORT_DDI_USED(phy);
return display->hti.state & HDPORT_ENABLED &&
display->hti.state & HDPORT_DDI_USED(phy);
}
u32 intel_hti_dpll_mask(struct drm_i915_private *i915)
u32 intel_hti_dpll_mask(struct intel_display *display)
{
if (!(i915->display.hti.state & HDPORT_ENABLED))
if (!(display->hti.state & HDPORT_ENABLED))
return 0;
/*
* Note: This is subtle. The values must coincide with what's defined
* for the platform.
*/
return REG_FIELD_GET(HDPORT_DPLL_USED_MASK, i915->display.hti.state);
return REG_FIELD_GET(HDPORT_DPLL_USED_MASK, display->hti.state);
}

8
drivers/gpu/drm/i915/display/intel_hti.h
View File

@ -8,11 +8,11 @@
#include <linux/types.h>
struct drm_i915_private;
struct intel_display;
enum phy;
void intel_hti_init(struct drm_i915_private *i915);
bool intel_hti_uses_phy(struct drm_i915_private *i915, enum phy phy);
u32 intel_hti_dpll_mask(struct drm_i915_private *i915);
void intel_hti_init(struct intel_display *display);
bool intel_hti_uses_phy(struct intel_display *display, enum phy phy);
u32 intel_hti_dpll_mask(struct intel_display *display);
#endif /* __INTEL_HTI_H__ */

25
drivers/gpu/drm/i915/display/intel_link_bw.c
View File

@ -25,12 +25,13 @@
void intel_link_bw_init_limits(struct intel_atomic_state *state,
struct intel_link_bw_limits *limits)
{
struct intel_display *display = to_intel_display(state);
struct drm_i915_private *i915 = to_i915(state->base.dev);
enum pipe pipe;
limits->force_fec_pipes = 0;
limits->bpp_limit_reached_pipes = 0;
for_each_pipe(i915, pipe) {
for_each_pipe(display, pipe) {
const struct intel_crtc_state *crtc_state =
intel_atomic_get_new_crtc_state(state,
intel_crtc_for_pipe(i915, pipe));
@ -69,12 +70,12 @@ int intel_link_bw_reduce_bpp(struct intel_atomic_state *state,
u8 pipe_mask,
const char *reason)
{
struct drm_i915_private *i915 = to_i915(state->base.dev);
struct intel_display *display = to_intel_display(state);
enum pipe max_bpp_pipe = INVALID_PIPE;
struct intel_crtc *crtc;
int max_bpp_x16 = 0;
for_each_intel_crtc_in_pipe_mask(&i915->drm, crtc, pipe_mask) {
for_each_intel_crtc_in_pipe_mask(display->drm, crtc, pipe_mask) {
struct intel_crtc_state *crtc_state;
int link_bpp_x16;
@ -136,7 +137,7 @@ intel_link_bw_set_bpp_limit_for_pipe(struct intel_atomic_state *state,
struct intel_link_bw_limits *new_limits,
enum pipe pipe)
{
struct drm_i915_private *i915 = to_i915(state->base.dev);
struct intel_display *display = to_intel_display(state);
if (pipe == INVALID_PIPE)
return false;
@ -145,7 +146,7 @@ intel_link_bw_set_bpp_limit_for_pipe(struct intel_atomic_state *state,
old_limits->max_bpp_x16[pipe])
return false;
if (drm_WARN_ON(&i915->drm,
if (drm_WARN_ON(display->drm,
new_limits->bpp_limit_reached_pipes & BIT(pipe)))
return false;
@ -178,7 +179,7 @@ static int check_all_link_config(struct intel_atomic_state *state,
}
static bool
assert_link_limit_change_valid(struct drm_i915_private *i915,
assert_link_limit_change_valid(struct intel_display *display,
const struct intel_link_bw_limits *old_limits,
const struct intel_link_bw_limits *new_limits)
{
@ -186,14 +187,14 @@ assert_link_limit_change_valid(struct drm_i915_private *i915,
enum pipe pipe;
/* FEC can't be forced off after it was forced on. */
if (drm_WARN_ON(&i915->drm,
if (drm_WARN_ON(display->drm,
(old_limits->force_fec_pipes & new_limits->force_fec_pipes) !=
old_limits->force_fec_pipes))
return false;
for_each_pipe(i915, pipe) {
for_each_pipe(display, pipe) {
/* The bpp limit can only decrease. */
if (drm_WARN_ON(&i915->drm,
if (drm_WARN_ON(display->drm,
new_limits->max_bpp_x16[pipe] >
old_limits->max_bpp_x16[pipe]))
return false;
@ -204,7 +205,7 @@ assert_link_limit_change_valid(struct drm_i915_private *i915,
}
/* At least one limit must change. */
if (drm_WARN_ON(&i915->drm,
if (drm_WARN_ON(display->drm,
!bpps_changed &&
new_limits->force_fec_pipes ==
old_limits->force_fec_pipes))
@ -232,7 +233,7 @@ assert_link_limit_change_valid(struct drm_i915_private *i915,
int intel_link_bw_atomic_check(struct intel_atomic_state *state,
struct intel_link_bw_limits *new_limits)
{
struct drm_i915_private *i915 = to_i915(state->base.dev);
struct intel_display *display = to_intel_display(state);
struct intel_link_bw_limits old_limits = *new_limits;
int ret;
@ -240,7 +241,7 @@ int intel_link_bw_atomic_check(struct intel_atomic_state *state,
if (ret != -EAGAIN)
return ret;
if (!assert_link_limit_change_valid(i915, &old_limits, new_limits))
if (!assert_link_limit_change_valid(display, &old_limits, new_limits))
return -EINVAL;
return -EAGAIN;

2
drivers/gpu/drm/i915/display/intel_link_bw.h
View File

@ -10,8 +10,6 @@
#include "intel_display_limits.h"
struct drm_i915_private;
struct intel_atomic_state;
struct intel_crtc_state;

27
drivers/gpu/drm/i915/display/intel_load_detect.c
View File

@ -48,23 +48,22 @@ struct drm_atomic_state *
intel_load_detect_get_pipe(struct drm_connector *connector,
struct drm_modeset_acquire_ctx *ctx)
{
struct intel_display *display = to_intel_display(connector->dev);
struct intel_encoder *encoder =
intel_attached_encoder(to_intel_connector(connector));
struct intel_crtc *possible_crtc;
struct intel_crtc *crtc = NULL;
struct drm_device *dev = encoder->base.dev;
struct drm_i915_private *dev_priv = to_i915(dev);
struct drm_mode_config *config = &dev->mode_config;
struct drm_mode_config *config = &display->drm->mode_config;
struct drm_atomic_state *state = NULL, *restore_state = NULL;
struct drm_connector_state *connector_state;
struct intel_crtc_state *crtc_state;
int ret;
drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
connector->base.id, connector->name,
encoder->base.base.id, encoder->base.name);
drm_WARN_ON(dev, !drm_modeset_is_locked(&config->connection_mutex));
drm_WARN_ON(display->drm, !drm_modeset_is_locked(&config->connection_mutex));
/*
* Algorithm gets a little messy:
@ -89,7 +88,7 @@ intel_load_detect_get_pipe(struct drm_connector *connector,
}
/* Find an unused one (if possible) */
for_each_intel_crtc(dev, possible_crtc) {
for_each_intel_crtc(display->drm, possible_crtc) {
if (!(encoder->base.possible_crtcs &
drm_crtc_mask(&possible_crtc->base)))
continue;
@ -111,15 +110,15 @@ intel_load_detect_get_pipe(struct drm_connector *connector,
* If we didn't find an unused CRTC, don't use any.
*/
if (!crtc) {
drm_dbg_kms(&dev_priv->drm,
drm_dbg_kms(display->drm,
"no pipe available for load-detect\n");
ret = -ENODEV;
goto fail;
}
found:
state = drm_atomic_state_alloc(dev);
restore_state = drm_atomic_state_alloc(dev);
state = drm_atomic_state_alloc(display->drm);
restore_state = drm_atomic_state_alloc(display->drm);
if (!state || !restore_state) {
ret = -ENOMEM;
goto fail;
@ -164,7 +163,7 @@ found:
if (!ret)
ret = drm_atomic_add_affected_planes(restore_state, &crtc->base);
if (ret) {
drm_dbg_kms(&dev_priv->drm,
drm_dbg_kms(display->drm,
"Failed to create a copy of old state to restore: %i\n",
ret);
goto fail;
@ -172,7 +171,7 @@ found:
ret = drm_atomic_commit(state);
if (ret) {
drm_dbg_kms(&dev_priv->drm,
drm_dbg_kms(display->drm,
"failed to set mode on load-detect pipe\n");
goto fail;
}
@ -204,13 +203,13 @@ void intel_load_detect_release_pipe(struct drm_connector *connector,
struct drm_atomic_state *state,
struct drm_modeset_acquire_ctx *ctx)
{
struct intel_display *display = to_intel_display(connector->dev);
struct intel_encoder *intel_encoder =
intel_attached_encoder(to_intel_connector(connector));
struct drm_i915_private *i915 = to_i915(intel_encoder->base.dev);
struct drm_encoder *encoder = &intel_encoder->base;
int ret;
drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
connector->base.id, connector->name,
encoder->base.id, encoder->name);
@ -219,7 +218,7 @@ void intel_load_detect_release_pipe(struct drm_connector *connector,
ret = drm_atomic_helper_commit_duplicated_state(state, ctx);
if (ret)
drm_dbg_kms(&i915->drm,
drm_dbg_kms(display->drm,
"Couldn't release load detect pipe: %i\n", ret);
drm_atomic_state_put(state);
}

115
drivers/gpu/drm/i915/display/intel_lspcon.c
View File

@ -79,33 +79,33 @@ static const char *lspcon_mode_name(enum drm_lspcon_mode mode)
static bool lspcon_detect_vendor(struct intel_lspcon *lspcon)
{
struct intel_dp *dp = lspcon_to_intel_dp(lspcon);
struct drm_i915_private *i915 = dp_to_i915(dp);
struct intel_dp *intel_dp = lspcon_to_intel_dp(lspcon);
struct intel_display *display = to_intel_display(intel_dp);
struct drm_dp_dpcd_ident *ident;
u32 vendor_oui;
if (drm_dp_read_desc(&dp->aux, &dp->desc, drm_dp_is_branch(dp->dpcd))) {
drm_err(&i915->drm, "Can't read description\n");
if (drm_dp_read_desc(&intel_dp->aux, &intel_dp->desc, drm_dp_is_branch(intel_dp->dpcd))) {
drm_err(display->drm, "Can't read description\n");
return false;
}
ident = &dp->desc.ident;
ident = &intel_dp->desc.ident;
vendor_oui = (ident->oui[0] << 16) | (ident->oui[1] << 8) |
ident->oui[2];
switch (vendor_oui) {
case LSPCON_VENDOR_MCA_OUI:
lspcon->vendor = LSPCON_VENDOR_MCA;
drm_dbg_kms(&i915->drm, "Vendor: Mega Chips\n");
drm_dbg_kms(display->drm, "Vendor: Mega Chips\n");
break;
case LSPCON_VENDOR_PARADE_OUI:
lspcon->vendor = LSPCON_VENDOR_PARADE;
drm_dbg_kms(&i915->drm, "Vendor: Parade Tech\n");
drm_dbg_kms(display->drm, "Vendor: Parade Tech\n");
break;
default:
drm_err(&i915->drm, "Invalid/Unknown vendor OUI\n");
drm_err(display->drm, "Invalid/Unknown vendor OUI\n");
return false;
}
@ -123,7 +123,7 @@ static u32 get_hdr_status_reg(struct intel_lspcon *lspcon)
void lspcon_detect_hdr_capability(struct intel_lspcon *lspcon)
{
struct intel_dp *intel_dp = lspcon_to_intel_dp(lspcon);
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
struct intel_display *display = to_intel_display(intel_dp);
u8 hdr_caps;
int ret;
@ -131,10 +131,10 @@ void lspcon_detect_hdr_capability(struct intel_lspcon *lspcon)
&hdr_caps, 1);
if (ret < 0) {
drm_dbg_kms(&i915->drm, "HDR capability detection failed\n");
drm_dbg_kms(display->drm, "HDR capability detection failed\n");
lspcon->hdr_supported = false;
} else if (hdr_caps & 0x1) {
drm_dbg_kms(&i915->drm, "LSPCON capable of HDR\n");
drm_dbg_kms(display->drm, "LSPCON capable of HDR\n");
lspcon->hdr_supported = true;
}
}
@ -142,12 +142,12 @@ void lspcon_detect_hdr_capability(struct intel_lspcon *lspcon)
static enum drm_lspcon_mode lspcon_get_current_mode(struct intel_lspcon *lspcon)
{
struct intel_dp *intel_dp = lspcon_to_intel_dp(lspcon);
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
struct intel_display *display = to_intel_display(intel_dp);
enum drm_lspcon_mode current_mode;
struct i2c_adapter *ddc = &intel_dp->aux.ddc;
if (drm_lspcon_get_mode(intel_dp->aux.drm_dev, ddc, &current_mode)) {
drm_dbg_kms(&i915->drm, "Error reading LSPCON mode\n");
drm_dbg_kms(display->drm, "Error reading LSPCON mode\n");
return DRM_LSPCON_MODE_INVALID;
}
return current_mode;
@ -169,23 +169,23 @@ static enum drm_lspcon_mode lspcon_wait_mode(struct intel_lspcon *lspcon,
enum drm_lspcon_mode mode)
{
struct intel_dp *intel_dp = lspcon_to_intel_dp(lspcon);
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
struct intel_display *display = to_intel_display(intel_dp);
enum drm_lspcon_mode current_mode;
current_mode = lspcon_get_current_mode(lspcon);
if (current_mode == mode)
goto out;
drm_dbg_kms(&i915->drm, "Waiting for LSPCON mode %s to settle\n",
drm_dbg_kms(display->drm, "Waiting for LSPCON mode %s to settle\n",
lspcon_mode_name(mode));
wait_for((current_mode = lspcon_get_current_mode(lspcon)) == mode,
lspcon_get_mode_settle_timeout(lspcon));
if (current_mode != mode)
drm_err(&i915->drm, "LSPCON mode hasn't settled\n");
drm_err(display->drm, "LSPCON mode hasn't settled\n");
out:
drm_dbg_kms(&i915->drm, "Current LSPCON mode %s\n",
drm_dbg_kms(display->drm, "Current LSPCON mode %s\n",
lspcon_mode_name(current_mode));
return current_mode;
@ -195,46 +195,46 @@ static int lspcon_change_mode(struct intel_lspcon *lspcon,
enum drm_lspcon_mode mode)
{
struct intel_dp *intel_dp = lspcon_to_intel_dp(lspcon);
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
struct intel_display *display = to_intel_display(intel_dp);
int err;
enum drm_lspcon_mode current_mode;
struct i2c_adapter *ddc = &intel_dp->aux.ddc;
err = drm_lspcon_get_mode(intel_dp->aux.drm_dev, ddc, &current_mode);
if (err) {
drm_err(&i915->drm, "Error reading LSPCON mode\n");
drm_err(display->drm, "Error reading LSPCON mode\n");
return err;
}
if (current_mode == mode) {
drm_dbg_kms(&i915->drm, "Current mode = desired LSPCON mode\n");
drm_dbg_kms(display->drm, "Current mode = desired LSPCON mode\n");
return 0;
}
err = drm_lspcon_set_mode(intel_dp->aux.drm_dev, ddc, mode);
if (err < 0) {
drm_err(&i915->drm, "LSPCON mode change failed\n");
drm_err(display->drm, "LSPCON mode change failed\n");
return err;
}
lspcon->mode = mode;
drm_dbg_kms(&i915->drm, "LSPCON mode changed done\n");
drm_dbg_kms(display->drm, "LSPCON mode changed done\n");
return 0;
}
static bool lspcon_wake_native_aux_ch(struct intel_lspcon *lspcon)
{
struct intel_dp *intel_dp = lspcon_to_intel_dp(lspcon);
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
struct intel_display *display = to_intel_display(intel_dp);
u8 rev;
if (drm_dp_dpcd_readb(&lspcon_to_intel_dp(lspcon)->aux, DP_DPCD_REV,
&rev) != 1) {
drm_dbg_kms(&i915->drm, "Native AUX CH down\n");
drm_dbg_kms(display->drm, "Native AUX CH down\n");
return false;
}
drm_dbg_kms(&i915->drm, "Native AUX CH up, DPCD version: %d.%d\n",
drm_dbg_kms(display->drm, "Native AUX CH up, DPCD version: %d.%d\n",
rev >> 4, rev & 0xf);
return true;
@ -242,12 +242,12 @@ static bool lspcon_wake_native_aux_ch(struct intel_lspcon *lspcon)
static bool lspcon_probe(struct intel_lspcon *lspcon)
{
int retry;
enum drm_dp_dual_mode_type adaptor_type;
struct intel_dp *intel_dp = lspcon_to_intel_dp(lspcon);
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
struct intel_display *display = to_intel_display(intel_dp);
struct i2c_adapter *ddc = &intel_dp->aux.ddc;
enum drm_dp_dual_mode_type adaptor_type;
enum drm_lspcon_mode expected_mode;
int retry;
expected_mode = lspcon_wake_native_aux_ch(lspcon) ?
DRM_LSPCON_MODE_PCON : DRM_LSPCON_MODE_LS;
@ -263,13 +263,13 @@ static bool lspcon_probe(struct intel_lspcon *lspcon)
}
if (adaptor_type != DRM_DP_DUAL_MODE_LSPCON) {
drm_dbg_kms(&i915->drm, "No LSPCON detected, found %s\n",
drm_dbg_kms(display->drm, "No LSPCON detected, found %s\n",
drm_dp_get_dual_mode_type_name(adaptor_type));
return false;
}
/* Yay ... got a LSPCON device */
drm_dbg_kms(&i915->drm, "LSPCON detected\n");
drm_dbg_kms(display->drm, "LSPCON detected\n");
lspcon->mode = lspcon_wait_mode(lspcon, expected_mode);
/*
@ -279,7 +279,7 @@ static bool lspcon_probe(struct intel_lspcon *lspcon)
*/
if (lspcon->mode != DRM_LSPCON_MODE_PCON) {
if (lspcon_change_mode(lspcon, DRM_LSPCON_MODE_PCON) < 0) {
drm_err(&i915->drm, "LSPCON mode change to PCON failed\n");
drm_err(display->drm, "LSPCON mode change to PCON failed\n");
return false;
}
}
@ -289,13 +289,13 @@ static bool lspcon_probe(struct intel_lspcon *lspcon)
static void lspcon_resume_in_pcon_wa(struct intel_lspcon *lspcon)
{
struct intel_dp *intel_dp = lspcon_to_intel_dp(lspcon);
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
struct intel_display *display = to_intel_display(intel_dp);
struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
unsigned long start = jiffies;
while (1) {
if (intel_digital_port_connected(&dig_port->base)) {
drm_dbg_kms(&i915->drm, "LSPCON recovering in PCON mode after %u ms\n",
drm_dbg_kms(display->drm, "LSPCON recovering in PCON mode after %u ms\n",
jiffies_to_msecs(jiffies - start));
return;
}
@ -306,7 +306,7 @@ static void lspcon_resume_in_pcon_wa(struct intel_lspcon *lspcon)
usleep_range(10000, 15000);
}
drm_dbg_kms(&i915->drm, "LSPCON DP descriptor mismatch after resume\n");
drm_dbg_kms(display->drm, "LSPCON DP descriptor mismatch after resume\n");
}
static bool lspcon_parade_fw_ready(struct drm_dp_aux *aux)
@ -477,10 +477,10 @@ void lspcon_write_infoframe(struct intel_encoder *encoder,
unsigned int type,
const void *frame, ssize_t len)
{
bool ret = true;
struct intel_display *display = to_intel_display(encoder);
struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
struct intel_lspcon *lspcon = enc_to_intel_lspcon(encoder);
bool ret = true;
switch (type) {
case HDMI_INFOFRAME_TYPE_AVI:
@ -492,7 +492,7 @@ void lspcon_write_infoframe(struct intel_encoder *encoder,
frame, len);
break;
case HDMI_PACKET_TYPE_GAMUT_METADATA:
drm_dbg_kms(&i915->drm, "Update HDR metadata for lspcon\n");
drm_dbg_kms(display->drm, "Update HDR metadata for lspcon\n");
/* It uses the legacy hsw implementation for the same */
hsw_write_infoframe(encoder, crtc_state, type, frame, len);
break;
@ -501,7 +501,7 @@ void lspcon_write_infoframe(struct intel_encoder *encoder,
}
if (!ret) {
drm_err(&i915->drm, "Failed to write infoframes\n");
drm_err(display->drm, "Failed to write infoframes\n");
return;
}
}
@ -522,17 +522,17 @@ void lspcon_set_infoframes(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state,
const struct drm_connector_state *conn_state)
{
ssize_t ret;
union hdmi_infoframe frame;
u8 buf[VIDEO_DIP_DATA_SIZE];
struct intel_display *display = to_intel_display(encoder);
struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
struct intel_lspcon *lspcon = &dig_port->lspcon;
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
const struct drm_display_mode *adjusted_mode =
&crtc_state->hw.adjusted_mode;
union hdmi_infoframe frame;
u8 buf[VIDEO_DIP_DATA_SIZE];
ssize_t ret;
if (!lspcon->active) {
drm_err(&i915->drm, "Writing infoframes while LSPCON disabled ?\n");
drm_err(display->drm, "Writing infoframes while LSPCON disabled ?\n");
return;
}
@ -542,7 +542,7 @@ void lspcon_set_infoframes(struct intel_encoder *encoder,
conn_state->connector,
adjusted_mode);
if (ret < 0) {
drm_err(&i915->drm, "couldn't fill AVI infoframe\n");
drm_err(display->drm, "couldn't fill AVI infoframe\n");
return;
}
@ -583,7 +583,7 @@ void lspcon_set_infoframes(struct intel_encoder *encoder,
ret = hdmi_infoframe_pack(&frame, buf, sizeof(buf));
if (ret < 0) {
drm_err(&i915->drm, "Failed to pack AVI IF\n");
drm_err(display->drm, "Failed to pack AVI IF\n");
return;
}
@ -624,9 +624,9 @@ static bool _lspcon_read_avi_infoframe_enabled_parade(struct drm_dp_aux *aux)
u32 lspcon_infoframes_enabled(struct intel_encoder *encoder,
const struct intel_crtc_state *pipe_config)
{
struct intel_display *display = to_intel_display(encoder);
struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
struct intel_lspcon *lspcon = enc_to_intel_lspcon(encoder);
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
bool infoframes_enabled;
u32 val = 0;
u32 mask, tmp;
@ -640,8 +640,8 @@ u32 lspcon_infoframes_enabled(struct intel_encoder *encoder,
val |= intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_AVI);
if (lspcon->hdr_supported) {
tmp = intel_de_read(dev_priv,
HSW_TVIDEO_DIP_CTL(dev_priv, pipe_config->cpu_transcoder));
tmp = intel_de_read(display,
HSW_TVIDEO_DIP_CTL(display, pipe_config->cpu_transcoder));
mask = VIDEO_DIP_ENABLE_GMP_HSW;
if (tmp & mask)
@ -658,32 +658,32 @@ void lspcon_wait_pcon_mode(struct intel_lspcon *lspcon)
bool lspcon_init(struct intel_digital_port *dig_port)
{
struct intel_display *display = to_intel_display(dig_port);
struct intel_dp *intel_dp = &dig_port->dp;
struct intel_lspcon *lspcon = &dig_port->lspcon;
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
struct drm_connector *connector = &intel_dp->attached_connector->base;
lspcon->active = false;
lspcon->mode = DRM_LSPCON_MODE_INVALID;
if (!lspcon_probe(lspcon)) {
drm_err(&i915->drm, "Failed to probe lspcon\n");
drm_err(display->drm, "Failed to probe lspcon\n");
return false;
}
if (drm_dp_read_dpcd_caps(&intel_dp->aux, intel_dp->dpcd) != 0) {
drm_err(&i915->drm, "LSPCON DPCD read failed\n");
drm_err(display->drm, "LSPCON DPCD read failed\n");
return false;
}
if (!lspcon_detect_vendor(lspcon)) {
drm_err(&i915->drm, "LSPCON vendor detection failed\n");
drm_err(display->drm, "LSPCON vendor detection failed\n");
return false;
}
connector->ycbcr_420_allowed = true;
lspcon->active = true;
drm_dbg_kms(&i915->drm, "Success: LSPCON init\n");
drm_dbg_kms(display->drm, "Success: LSPCON init\n");
return true;
}
@ -697,9 +697,8 @@ u32 intel_lspcon_infoframes_enabled(struct intel_encoder *encoder,
void lspcon_resume(struct intel_digital_port *dig_port)
{
struct intel_display *display = to_intel_display(dig_port);
struct intel_lspcon *lspcon = &dig_port->lspcon;
struct drm_device *dev = dig_port->base.base.dev;
struct drm_i915_private *i915 = to_i915(dev);
enum drm_lspcon_mode expected_mode;
if (!intel_bios_encoder_is_lspcon(dig_port->base.devdata))
@ -707,7 +706,7 @@ void lspcon_resume(struct intel_digital_port *dig_port)
if (!lspcon->active) {
if (!lspcon_init(dig_port)) {
drm_err(&i915->drm, "LSPCON init failed on port %c\n",
drm_err(display->drm, "LSPCON init failed on port %c\n",
port_name(dig_port->base.port));
return;
}
@ -724,7 +723,7 @@ void lspcon_resume(struct intel_digital_port *dig_port)
return;
if (lspcon_change_mode(lspcon, DRM_LSPCON_MODE_PCON))
drm_err(&i915->drm, "LSPCON resume failed\n");
drm_err(display->drm, "LSPCON resume failed\n");
else
drm_dbg_kms(&i915->drm, "LSPCON resume success\n");
drm_dbg_kms(display->drm, "LSPCON resume success\n");
}

31
drivers/gpu/drm/i915/display/intel_modeset_setup.c
View File

@ -326,6 +326,8 @@ static void intel_modeset_update_connector_atomic_state(struct drm_i915_private
static void intel_crtc_copy_hw_to_uapi_state(struct intel_crtc_state *crtc_state)
{
struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
if (intel_crtc_is_joiner_secondary(crtc_state))
return;
@ -337,11 +339,30 @@ static void intel_crtc_copy_hw_to_uapi_state(struct intel_crtc_state *crtc_state
crtc_state->uapi.adjusted_mode = crtc_state->hw.adjusted_mode;
crtc_state->uapi.scaling_filter = crtc_state->hw.scaling_filter;
/* assume 1:1 mapping */
drm_property_replace_blob(&crtc_state->hw.degamma_lut,
crtc_state->pre_csc_lut);
drm_property_replace_blob(&crtc_state->hw.gamma_lut,
crtc_state->post_csc_lut);
if (DISPLAY_INFO(i915)->color.degamma_lut_size) {
/* assume 1:1 mapping */
drm_property_replace_blob(&crtc_state->hw.degamma_lut,
crtc_state->pre_csc_lut);
drm_property_replace_blob(&crtc_state->hw.gamma_lut,
crtc_state->post_csc_lut);
} else {
/*
* ilk/snb hw may be configured for either pre_csc_lut
* or post_csc_lut, but we don't advertise degamma_lut as
* being available in the uapi since there is only one
* hardware LUT. Always assign the result of the readout
* to gamma_lut as that is the only valid source of LUTs
* in the uapi.
*/
drm_WARN_ON(&i915->drm, crtc_state->post_csc_lut &&
crtc_state->pre_csc_lut);
drm_property_replace_blob(&crtc_state->hw.degamma_lut,
NULL);
drm_property_replace_blob(&crtc_state->hw.gamma_lut,
crtc_state->post_csc_lut ?:
crtc_state->pre_csc_lut);
}
drm_property_replace_blob(&crtc_state->uapi.degamma_lut,
crtc_state->hw.degamma_lut);

2
drivers/gpu/drm/i915/display/intel_pmdemand.c
View File

@ -92,7 +92,7 @@ int intel_pmdemand_init(struct drm_i915_private *i915)
&pmdemand_state->base,
&intel_pmdemand_funcs);
if (IS_DISPLAY_IP_STEP(i915, IP_VER(14, 0), STEP_A0, STEP_C0))
if (IS_DISPLAY_VER_STEP(i915, IP_VER(14, 0), STEP_A0, STEP_C0))
/* Wa_14016740474 */
intel_de_rmw(i915, XELPD_CHICKEN_DCPR_3, 0, DMD_RSP_TIMEOUT_DISABLE);

14
drivers/gpu/drm/i915/display/intel_pps.c
View File

@ -951,6 +951,14 @@ void intel_pps_on_unlocked(struct intel_dp *intel_dp)
intel_de_posting_read(dev_priv, pp_ctrl_reg);
}
/*
* WA: 22019252566
* Disable DPLS gating around power sequence.
*/
if (IS_DISPLAY_VER(dev_priv, 13, 14))
intel_de_rmw(dev_priv, SOUTH_DSPCLK_GATE_D,
0, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
pp |= PANEL_POWER_ON;
if (!IS_IRONLAKE(dev_priv))
pp |= PANEL_POWER_RESET;
@ -961,6 +969,10 @@ void intel_pps_on_unlocked(struct intel_dp *intel_dp)
wait_panel_on(intel_dp);
intel_dp->pps.last_power_on = jiffies;
if (IS_DISPLAY_VER(dev_priv, 13, 14))
intel_de_rmw(dev_priv, SOUTH_DSPCLK_GATE_D,
PCH_DPLSUNIT_CLOCK_GATE_DISABLE, 0);
if (IS_IRONLAKE(dev_priv)) {
pp |= PANEL_POWER_RESET; /* restore panel reset bit */
intel_de_write(dev_priv, pp_ctrl_reg, pp);
@ -1471,7 +1483,7 @@ static void pps_init_registers(struct intel_dp *intel_dp, bool force_disable_vdd
{
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
u32 pp_on, pp_off, port_sel = 0;
int div = RUNTIME_INFO(dev_priv)->rawclk_freq / 1000;
int div = DISPLAY_RUNTIME_INFO(dev_priv)->rawclk_freq / 1000;
struct pps_registers regs;
enum port port = dp_to_dig_port(intel_dp)->base.port;
const struct edp_power_seq *seq = &intel_dp->pps.pps_delays;

14
drivers/gpu/drm/i915/display/intel_psr.c
View File

@ -1586,6 +1586,12 @@ _panel_replay_compute_config(struct intel_dp *intel_dp,
if (!alpm_config_valid(intel_dp, crtc_state, true))
return false;
if (crtc_state->crc_enabled) {
drm_dbg_kms(&i915->drm,
"Panel Replay not enabled because it would inhibit pipe CRC calculation\n");
return false;
}
return true;
}
@ -1862,14 +1868,14 @@ static void intel_psr_enable_source(struct intel_dp *intel_dp,
* cause issues if non-supported panels are used.
*/
if (!intel_dp->psr.panel_replay_enabled &&
(IS_DISPLAY_IP_STEP(dev_priv, IP_VER(14, 0), STEP_A0, STEP_B0) ||
(IS_DISPLAY_VER_STEP(dev_priv, IP_VER(14, 0), STEP_A0, STEP_B0) ||
IS_ALDERLAKE_P(dev_priv)))
intel_de_rmw(dev_priv, hsw_chicken_trans_reg(dev_priv, cpu_transcoder),
0, ADLP_1_BASED_X_GRANULARITY);
/* Wa_16012604467:adlp,mtl[a0,b0] */
if (!intel_dp->psr.panel_replay_enabled &&
IS_DISPLAY_IP_STEP(dev_priv, IP_VER(14, 0), STEP_A0, STEP_B0))
IS_DISPLAY_VER_STEP(dev_priv, IP_VER(14, 0), STEP_A0, STEP_B0))
intel_de_rmw(dev_priv,
MTL_CLKGATE_DIS_TRANS(dev_priv, cpu_transcoder),
0,
@ -2051,7 +2057,7 @@ static void intel_psr_disable_locked(struct intel_dp *intel_dp)
if (intel_dp->psr.sel_update_enabled) {
/* Wa_16012604467:adlp,mtl[a0,b0] */
if (!intel_dp->psr.panel_replay_enabled &&
IS_DISPLAY_IP_STEP(dev_priv, IP_VER(14, 0), STEP_A0, STEP_B0))
IS_DISPLAY_VER_STEP(dev_priv, IP_VER(14, 0), STEP_A0, STEP_B0))
intel_de_rmw(dev_priv,
MTL_CLKGATE_DIS_TRANS(dev_priv, cpu_transcoder),
MTL_CLKGATE_DIS_TRANS_DMASC_GATING_DIS, 0);
@ -2536,7 +2542,7 @@ int intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
/* Wa_14014971492 */
if (!crtc_state->has_panel_replay &&
((IS_DISPLAY_IP_STEP(dev_priv, IP_VER(14, 0), STEP_A0, STEP_B0) ||
((IS_DISPLAY_VER_STEP(dev_priv, IP_VER(14, 0), STEP_A0, STEP_B0) ||
IS_ALDERLAKE_P(dev_priv) || IS_TIGERLAKE(dev_priv))) &&
crtc_state->splitter.enable)
crtc_state->psr2_su_area.y1 = 0;

209
drivers/gpu/drm/i915/display/intel_sprite.c
View File

@ -48,9 +48,9 @@
#include "intel_sprite.h"
#include "intel_sprite_regs.h"
static char sprite_name(struct drm_i915_private *i915, enum pipe pipe, int sprite)
static char sprite_name(struct intel_display *display, enum pipe pipe, int sprite)
{
return pipe * DISPLAY_RUNTIME_INFO(i915)->num_sprites[pipe] + sprite + 'A';
return pipe * DISPLAY_RUNTIME_INFO(display)->num_sprites[pipe] + sprite + 'A';
}
static void i9xx_plane_linear_gamma(u16 gamma[8])
@ -67,7 +67,7 @@ static void
chv_sprite_update_csc(const struct intel_plane_state *plane_state)
{
struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
struct intel_display *display = to_intel_display(plane->base.dev);
const struct drm_framebuffer *fb = plane_state->hw.fb;
enum plane_id plane_id = plane->id;
/*
@ -100,35 +100,35 @@ chv_sprite_update_csc(const struct intel_plane_state *plane_state)
if (!fb->format->is_yuv)
return;
intel_de_write_fw(dev_priv, SPCSCYGOFF(plane_id),
intel_de_write_fw(display, SPCSCYGOFF(plane_id),
SPCSC_OOFF(0) | SPCSC_IOFF(0));
intel_de_write_fw(dev_priv, SPCSCCBOFF(plane_id),
intel_de_write_fw(display, SPCSCCBOFF(plane_id),
SPCSC_OOFF(0) | SPCSC_IOFF(0));
intel_de_write_fw(dev_priv, SPCSCCROFF(plane_id),
intel_de_write_fw(display, SPCSCCROFF(plane_id),
SPCSC_OOFF(0) | SPCSC_IOFF(0));
intel_de_write_fw(dev_priv, SPCSCC01(plane_id),
intel_de_write_fw(display, SPCSCC01(plane_id),
SPCSC_C1(csc[1]) | SPCSC_C0(csc[0]));
intel_de_write_fw(dev_priv, SPCSCC23(plane_id),
intel_de_write_fw(display, SPCSCC23(plane_id),
SPCSC_C1(csc[3]) | SPCSC_C0(csc[2]));
intel_de_write_fw(dev_priv, SPCSCC45(plane_id),
intel_de_write_fw(display, SPCSCC45(plane_id),
SPCSC_C1(csc[5]) | SPCSC_C0(csc[4]));
intel_de_write_fw(dev_priv, SPCSCC67(plane_id),
intel_de_write_fw(display, SPCSCC67(plane_id),
SPCSC_C1(csc[7]) | SPCSC_C0(csc[6]));
intel_de_write_fw(dev_priv, SPCSCC8(plane_id), SPCSC_C0(csc[8]));
intel_de_write_fw(display, SPCSCC8(plane_id), SPCSC_C0(csc[8]));
intel_de_write_fw(dev_priv, SPCSCYGICLAMP(plane_id),
intel_de_write_fw(display, SPCSCYGICLAMP(plane_id),
SPCSC_IMAX(1023) | SPCSC_IMIN(0));
intel_de_write_fw(dev_priv, SPCSCCBICLAMP(plane_id),
intel_de_write_fw(display, SPCSCCBICLAMP(plane_id),
SPCSC_IMAX(512) | SPCSC_IMIN(-512));
intel_de_write_fw(dev_priv, SPCSCCRICLAMP(plane_id),
intel_de_write_fw(display, SPCSCCRICLAMP(plane_id),
SPCSC_IMAX(512) | SPCSC_IMIN(-512));
intel_de_write_fw(dev_priv, SPCSCYGOCLAMP(plane_id),
intel_de_write_fw(display, SPCSCYGOCLAMP(plane_id),
SPCSC_OMAX(1023) | SPCSC_OMIN(0));
intel_de_write_fw(dev_priv, SPCSCCBOCLAMP(plane_id),
intel_de_write_fw(display, SPCSCCBOCLAMP(plane_id),
SPCSC_OMAX(1023) | SPCSC_OMIN(0));
intel_de_write_fw(dev_priv, SPCSCCROCLAMP(plane_id),
intel_de_write_fw(display, SPCSCCROCLAMP(plane_id),
SPCSC_OMAX(1023) | SPCSC_OMIN(0));
}
@ -139,7 +139,7 @@ static void
vlv_sprite_update_clrc(const struct intel_plane_state *plane_state)
{
struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
struct intel_display *display = to_intel_display(plane->base.dev);
const struct drm_framebuffer *fb = plane_state->hw.fb;
enum pipe pipe = plane->pipe;
enum plane_id plane_id = plane->id;
@ -168,9 +168,9 @@ vlv_sprite_update_clrc(const struct intel_plane_state *plane_state)
}
/* FIXME these register are single buffered :( */
intel_de_write_fw(dev_priv, SPCLRC0(pipe, plane_id),
intel_de_write_fw(display, SPCLRC0(pipe, plane_id),
SP_CONTRAST(contrast) | SP_BRIGHTNESS(brightness));
intel_de_write_fw(dev_priv, SPCLRC1(pipe, plane_id),
intel_de_write_fw(display, SPCLRC1(pipe, plane_id),
SP_SH_SIN(sh_sin) | SP_SH_COS(sh_cos));
}
@ -357,7 +357,7 @@ static u32 vlv_sprite_ctl(const struct intel_crtc_state *crtc_state,
static void vlv_sprite_update_gamma(const struct intel_plane_state *plane_state)
{
struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
struct intel_display *display = to_intel_display(plane->base.dev);
const struct drm_framebuffer *fb = plane_state->hw.fb;
enum pipe pipe = plane->pipe;
enum plane_id plane_id = plane->id;
@ -373,7 +373,7 @@ static void vlv_sprite_update_gamma(const struct intel_plane_state *plane_state)
/* FIXME these register are single buffered :( */
/* The two end points are implicit (0.0 and 1.0) */
for (i = 1; i < 8 - 1; i++)
intel_de_write_fw(dev_priv, SPGAMC(pipe, plane_id, i - 1),
intel_de_write_fw(display, SPGAMC(pipe, plane_id, i - 1),
gamma[i] << 16 | gamma[i] << 8 | gamma[i]);
}
@ -382,7 +382,7 @@ vlv_sprite_update_noarm(struct intel_plane *plane,
const struct intel_crtc_state *crtc_state,
const struct intel_plane_state *plane_state)
{
struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
struct intel_display *display = to_intel_display(plane->base.dev);
enum pipe pipe = plane->pipe;
enum plane_id plane_id = plane->id;
int crtc_x = plane_state->uapi.dst.x1;
@ -390,11 +390,11 @@ vlv_sprite_update_noarm(struct intel_plane *plane,
u32 crtc_w = drm_rect_width(&plane_state->uapi.dst);
u32 crtc_h = drm_rect_height(&plane_state->uapi.dst);
intel_de_write_fw(dev_priv, SPSTRIDE(pipe, plane_id),
intel_de_write_fw(display, SPSTRIDE(pipe, plane_id),
plane_state->view.color_plane[0].mapping_stride);
intel_de_write_fw(dev_priv, SPPOS(pipe, plane_id),
intel_de_write_fw(display, SPPOS(pipe, plane_id),
SP_POS_Y(crtc_y) | SP_POS_X(crtc_x));
intel_de_write_fw(dev_priv, SPSIZE(pipe, plane_id),
intel_de_write_fw(display, SPSIZE(pipe, plane_id),
SP_HEIGHT(crtc_h - 1) | SP_WIDTH(crtc_w - 1));
}
@ -403,6 +403,7 @@ vlv_sprite_update_arm(struct intel_plane *plane,
const struct intel_crtc_state *crtc_state,
const struct intel_plane_state *plane_state)
{
struct intel_display *display = to_intel_display(plane->base.dev);
struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
enum pipe pipe = plane->pipe;
enum plane_id plane_id = plane->id;
@ -420,18 +421,18 @@ vlv_sprite_update_arm(struct intel_plane *plane,
chv_sprite_update_csc(plane_state);
if (key->flags) {
intel_de_write_fw(dev_priv, SPKEYMINVAL(pipe, plane_id),
intel_de_write_fw(display, SPKEYMINVAL(pipe, plane_id),
key->min_value);
intel_de_write_fw(dev_priv, SPKEYMSK(pipe, plane_id),
intel_de_write_fw(display, SPKEYMSK(pipe, plane_id),
key->channel_mask);
intel_de_write_fw(dev_priv, SPKEYMAXVAL(pipe, plane_id),
intel_de_write_fw(display, SPKEYMAXVAL(pipe, plane_id),
key->max_value);
}
intel_de_write_fw(dev_priv, SPCONSTALPHA(pipe, plane_id), 0);
intel_de_write_fw(display, SPCONSTALPHA(pipe, plane_id), 0);
intel_de_write_fw(dev_priv, SPLINOFF(pipe, plane_id), linear_offset);
intel_de_write_fw(dev_priv, SPTILEOFF(pipe, plane_id),
intel_de_write_fw(display, SPLINOFF(pipe, plane_id), linear_offset);
intel_de_write_fw(display, SPTILEOFF(pipe, plane_id),
SP_OFFSET_Y(y) | SP_OFFSET_X(x));
/*
@ -439,8 +440,8 @@ vlv_sprite_update_arm(struct intel_plane *plane,
* disabled. Try to make the plane enable atomic by writing
* the control register just before the surface register.
*/
intel_de_write_fw(dev_priv, SPCNTR(pipe, plane_id), sprctl);
intel_de_write_fw(dev_priv, SPSURF(pipe, plane_id),
intel_de_write_fw(display, SPCNTR(pipe, plane_id), sprctl);
intel_de_write_fw(display, SPSURF(pipe, plane_id),
intel_plane_ggtt_offset(plane_state) + sprsurf_offset);
vlv_sprite_update_clrc(plane_state);
@ -451,18 +452,19 @@ static void
vlv_sprite_disable_arm(struct intel_plane *plane,
const struct intel_crtc_state *crtc_state)
{
struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
struct intel_display *display = to_intel_display(plane->base.dev);
enum pipe pipe = plane->pipe;
enum plane_id plane_id = plane->id;
intel_de_write_fw(dev_priv, SPCNTR(pipe, plane_id), 0);
intel_de_write_fw(dev_priv, SPSURF(pipe, plane_id), 0);
intel_de_write_fw(display, SPCNTR(pipe, plane_id), 0);
intel_de_write_fw(display, SPSURF(pipe, plane_id), 0);
}
static bool
vlv_sprite_get_hw_state(struct intel_plane *plane,
enum pipe *pipe)
{
struct intel_display *display = to_intel_display(plane->base.dev);
struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
enum intel_display_power_domain power_domain;
enum plane_id plane_id = plane->id;
@ -474,7 +476,7 @@ vlv_sprite_get_hw_state(struct intel_plane *plane,
if (!wakeref)
return false;
ret = intel_de_read(dev_priv, SPCNTR(plane->pipe, plane_id)) & SP_ENABLE;
ret = intel_de_read(display, SPCNTR(plane->pipe, plane_id)) & SP_ENABLE;
*pipe = plane->pipe;
@ -766,7 +768,7 @@ static void ivb_sprite_linear_gamma(const struct intel_plane_state *plane_state,
static void ivb_sprite_update_gamma(const struct intel_plane_state *plane_state)
{
struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
struct intel_display *display = to_intel_display(plane->base.dev);
enum pipe pipe = plane->pipe;
u16 gamma[18];
int i;
@ -778,17 +780,17 @@ static void ivb_sprite_update_gamma(const struct intel_plane_state *plane_state)
/* FIXME these register are single buffered :( */
for (i = 0; i < 16; i++)
intel_de_write_fw(dev_priv, SPRGAMC(pipe, i),
intel_de_write_fw(display, SPRGAMC(pipe, i),
gamma[i] << 20 | gamma[i] << 10 | gamma[i]);
intel_de_write_fw(dev_priv, SPRGAMC16(pipe, 0), gamma[i]);
intel_de_write_fw(dev_priv, SPRGAMC16(pipe, 1), gamma[i]);
intel_de_write_fw(dev_priv, SPRGAMC16(pipe, 2), gamma[i]);
intel_de_write_fw(display, SPRGAMC16(pipe, 0), gamma[i]);
intel_de_write_fw(display, SPRGAMC16(pipe, 1), gamma[i]);
intel_de_write_fw(display, SPRGAMC16(pipe, 2), gamma[i]);
i++;
intel_de_write_fw(dev_priv, SPRGAMC17(pipe, 0), gamma[i]);
intel_de_write_fw(dev_priv, SPRGAMC17(pipe, 1), gamma[i]);
intel_de_write_fw(dev_priv, SPRGAMC17(pipe, 2), gamma[i]);
intel_de_write_fw(display, SPRGAMC17(pipe, 0), gamma[i]);
intel_de_write_fw(display, SPRGAMC17(pipe, 1), gamma[i]);
intel_de_write_fw(display, SPRGAMC17(pipe, 2), gamma[i]);
i++;
}
@ -797,6 +799,7 @@ ivb_sprite_update_noarm(struct intel_plane *plane,
const struct intel_crtc_state *crtc_state,
const struct intel_plane_state *plane_state)
{
struct intel_display *display = to_intel_display(plane->base.dev);
struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
enum pipe pipe = plane->pipe;
int crtc_x = plane_state->uapi.dst.x1;
@ -812,14 +815,14 @@ ivb_sprite_update_noarm(struct intel_plane *plane,
SPRITE_SRC_WIDTH(src_w - 1) |
SPRITE_SRC_HEIGHT(src_h - 1);
intel_de_write_fw(dev_priv, SPRSTRIDE(pipe),
intel_de_write_fw(display, SPRSTRIDE(pipe),
plane_state->view.color_plane[0].mapping_stride);
intel_de_write_fw(dev_priv, SPRPOS(pipe),
intel_de_write_fw(display, SPRPOS(pipe),
SPRITE_POS_Y(crtc_y) | SPRITE_POS_X(crtc_x));
intel_de_write_fw(dev_priv, SPRSIZE(pipe),
intel_de_write_fw(display, SPRSIZE(pipe),
SPRITE_HEIGHT(crtc_h - 1) | SPRITE_WIDTH(crtc_w - 1));
if (IS_IVYBRIDGE(dev_priv))
intel_de_write_fw(dev_priv, SPRSCALE(pipe), sprscale);
intel_de_write_fw(display, SPRSCALE(pipe), sprscale);
}
static void
@ -827,6 +830,7 @@ ivb_sprite_update_arm(struct intel_plane *plane,
const struct intel_crtc_state *crtc_state,
const struct intel_plane_state *plane_state)
{
struct intel_display *display = to_intel_display(plane->base.dev);
struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
enum pipe pipe = plane->pipe;
const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
@ -840,20 +844,20 @@ ivb_sprite_update_arm(struct intel_plane *plane,
linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
if (key->flags) {
intel_de_write_fw(dev_priv, SPRKEYVAL(pipe), key->min_value);
intel_de_write_fw(dev_priv, SPRKEYMSK(pipe),
intel_de_write_fw(display, SPRKEYVAL(pipe), key->min_value);
intel_de_write_fw(display, SPRKEYMSK(pipe),
key->channel_mask);
intel_de_write_fw(dev_priv, SPRKEYMAX(pipe), key->max_value);
intel_de_write_fw(display, SPRKEYMAX(pipe), key->max_value);
}
/* HSW consolidates SPRTILEOFF and SPRLINOFF into a single SPROFFSET
* register */
if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
intel_de_write_fw(dev_priv, SPROFFSET(pipe),
intel_de_write_fw(display, SPROFFSET(pipe),
SPRITE_OFFSET_Y(y) | SPRITE_OFFSET_X(x));
} else {
intel_de_write_fw(dev_priv, SPRLINOFF(pipe), linear_offset);
intel_de_write_fw(dev_priv, SPRTILEOFF(pipe),
intel_de_write_fw(display, SPRLINOFF(pipe), linear_offset);
intel_de_write_fw(display, SPRTILEOFF(pipe),
SPRITE_OFFSET_Y(y) | SPRITE_OFFSET_X(x));
}
@ -862,8 +866,8 @@ ivb_sprite_update_arm(struct intel_plane *plane,
* disabled. Try to make the plane enable atomic by writing
* the control register just before the surface register.
*/
intel_de_write_fw(dev_priv, SPRCTL(pipe), sprctl);
intel_de_write_fw(dev_priv, SPRSURF(pipe),
intel_de_write_fw(display, SPRCTL(pipe), sprctl);
intel_de_write_fw(display, SPRSURF(pipe),
intel_plane_ggtt_offset(plane_state) + sprsurf_offset);
ivb_sprite_update_gamma(plane_state);
@ -873,20 +877,22 @@ static void
ivb_sprite_disable_arm(struct intel_plane *plane,
const struct intel_crtc_state *crtc_state)
{
struct intel_display *display = to_intel_display(plane->base.dev);
struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
enum pipe pipe = plane->pipe;
intel_de_write_fw(dev_priv, SPRCTL(pipe), 0);
intel_de_write_fw(display, SPRCTL(pipe), 0);
/* Disable the scaler */
if (IS_IVYBRIDGE(dev_priv))
intel_de_write_fw(dev_priv, SPRSCALE(pipe), 0);
intel_de_write_fw(dev_priv, SPRSURF(pipe), 0);
intel_de_write_fw(display, SPRSCALE(pipe), 0);
intel_de_write_fw(display, SPRSURF(pipe), 0);
}
static bool
ivb_sprite_get_hw_state(struct intel_plane *plane,
enum pipe *pipe)
{
struct intel_display *display = to_intel_display(plane->base.dev);
struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
enum intel_display_power_domain power_domain;
intel_wakeref_t wakeref;
@ -897,7 +903,7 @@ ivb_sprite_get_hw_state(struct intel_plane *plane,
if (!wakeref)
return false;
ret = intel_de_read(dev_priv, SPRCTL(plane->pipe)) & SPRITE_ENABLE;
ret = intel_de_read(display, SPRCTL(plane->pipe)) & SPRITE_ENABLE;
*pipe = plane->pipe;
@ -1073,7 +1079,7 @@ static u32 g4x_sprite_ctl(const struct intel_crtc_state *crtc_state,
static void g4x_sprite_update_gamma(const struct intel_plane_state *plane_state)
{
struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
struct intel_display *display = to_intel_display(plane->base.dev);
const struct drm_framebuffer *fb = plane_state->hw.fb;
enum pipe pipe = plane->pipe;
u16 gamma[8];
@ -1088,7 +1094,7 @@ static void g4x_sprite_update_gamma(const struct intel_plane_state *plane_state)
/* FIXME these register are single buffered :( */
/* The two end points are implicit (0.0 and 1.0) */
for (i = 1; i < 8 - 1; i++)
intel_de_write_fw(dev_priv, DVSGAMC_G4X(pipe, i - 1),
intel_de_write_fw(display, DVSGAMC_G4X(pipe, i - 1),
gamma[i] << 16 | gamma[i] << 8 | gamma[i]);
}
@ -1103,7 +1109,7 @@ static void ilk_sprite_linear_gamma(u16 gamma[17])
static void ilk_sprite_update_gamma(const struct intel_plane_state *plane_state)
{
struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
struct intel_display *display = to_intel_display(plane->base.dev);
const struct drm_framebuffer *fb = plane_state->hw.fb;
enum pipe pipe = plane->pipe;
u16 gamma[17];
@ -1117,12 +1123,12 @@ static void ilk_sprite_update_gamma(const struct intel_plane_state *plane_state)
/* FIXME these register are single buffered :( */
for (i = 0; i < 16; i++)
intel_de_write_fw(dev_priv, DVSGAMC_ILK(pipe, i),
intel_de_write_fw(display, DVSGAMC_ILK(pipe, i),
gamma[i] << 20 | gamma[i] << 10 | gamma[i]);
intel_de_write_fw(dev_priv, DVSGAMCMAX_ILK(pipe, 0), gamma[i]);
intel_de_write_fw(dev_priv, DVSGAMCMAX_ILK(pipe, 1), gamma[i]);
intel_de_write_fw(dev_priv, DVSGAMCMAX_ILK(pipe, 2), gamma[i]);
intel_de_write_fw(display, DVSGAMCMAX_ILK(pipe, 0), gamma[i]);
intel_de_write_fw(display, DVSGAMCMAX_ILK(pipe, 1), gamma[i]);
intel_de_write_fw(display, DVSGAMCMAX_ILK(pipe, 2), gamma[i]);
i++;
}
@ -1131,7 +1137,7 @@ g4x_sprite_update_noarm(struct intel_plane *plane,
const struct intel_crtc_state *crtc_state,
const struct intel_plane_state *plane_state)
{
struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
struct intel_display *display = to_intel_display(plane->base.dev);
enum pipe pipe = plane->pipe;
int crtc_x = plane_state->uapi.dst.x1;
int crtc_y = plane_state->uapi.dst.y1;
@ -1146,13 +1152,13 @@ g4x_sprite_update_noarm(struct intel_plane *plane,
DVS_SRC_WIDTH(src_w - 1) |
DVS_SRC_HEIGHT(src_h - 1);
intel_de_write_fw(dev_priv, DVSSTRIDE(pipe),
intel_de_write_fw(display, DVSSTRIDE(pipe),
plane_state->view.color_plane[0].mapping_stride);
intel_de_write_fw(dev_priv, DVSPOS(pipe),
intel_de_write_fw(display, DVSPOS(pipe),
DVS_POS_Y(crtc_y) | DVS_POS_X(crtc_x));
intel_de_write_fw(dev_priv, DVSSIZE(pipe),
intel_de_write_fw(display, DVSSIZE(pipe),
DVS_HEIGHT(crtc_h - 1) | DVS_WIDTH(crtc_w - 1));
intel_de_write_fw(dev_priv, DVSSCALE(pipe), dvsscale);
intel_de_write_fw(display, DVSSCALE(pipe), dvsscale);
}
static void
@ -1160,6 +1166,7 @@ g4x_sprite_update_arm(struct intel_plane *plane,
const struct intel_crtc_state *crtc_state,
const struct intel_plane_state *plane_state)
{
struct intel_display *display = to_intel_display(plane->base.dev);
struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
enum pipe pipe = plane->pipe;
const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
@ -1173,14 +1180,14 @@ g4x_sprite_update_arm(struct intel_plane *plane,
linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
if (key->flags) {
intel_de_write_fw(dev_priv, DVSKEYVAL(pipe), key->min_value);
intel_de_write_fw(dev_priv, DVSKEYMSK(pipe),
intel_de_write_fw(display, DVSKEYVAL(pipe), key->min_value);
intel_de_write_fw(display, DVSKEYMSK(pipe),
key->channel_mask);
intel_de_write_fw(dev_priv, DVSKEYMAX(pipe), key->max_value);
intel_de_write_fw(display, DVSKEYMAX(pipe), key->max_value);
}
intel_de_write_fw(dev_priv, DVSLINOFF(pipe), linear_offset);
intel_de_write_fw(dev_priv, DVSTILEOFF(pipe),
intel_de_write_fw(display, DVSLINOFF(pipe), linear_offset);
intel_de_write_fw(display, DVSTILEOFF(pipe),
DVS_OFFSET_Y(y) | DVS_OFFSET_X(x));
/*
@ -1188,8 +1195,8 @@ g4x_sprite_update_arm(struct intel_plane *plane,
* disabled. Try to make the plane enable atomic by writing
* the control register just before the surface register.
*/
intel_de_write_fw(dev_priv, DVSCNTR(pipe), dvscntr);
intel_de_write_fw(dev_priv, DVSSURF(pipe),
intel_de_write_fw(display, DVSCNTR(pipe), dvscntr);
intel_de_write_fw(display, DVSSURF(pipe),
intel_plane_ggtt_offset(plane_state) + dvssurf_offset);
if (IS_G4X(dev_priv))
@ -1202,19 +1209,20 @@ static void
g4x_sprite_disable_arm(struct intel_plane *plane,
const struct intel_crtc_state *crtc_state)
{
struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
struct intel_display *display = to_intel_display(plane->base.dev);
enum pipe pipe = plane->pipe;
intel_de_write_fw(dev_priv, DVSCNTR(pipe), 0);
intel_de_write_fw(display, DVSCNTR(pipe), 0);
/* Disable the scaler */
intel_de_write_fw(dev_priv, DVSSCALE(pipe), 0);
intel_de_write_fw(dev_priv, DVSSURF(pipe), 0);
intel_de_write_fw(display, DVSSCALE(pipe), 0);
intel_de_write_fw(display, DVSSURF(pipe), 0);
}
static bool
g4x_sprite_get_hw_state(struct intel_plane *plane,
enum pipe *pipe)
{
struct intel_display *display = to_intel_display(plane->base.dev);
struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
enum intel_display_power_domain power_domain;
intel_wakeref_t wakeref;
@ -1225,7 +1233,7 @@ g4x_sprite_get_hw_state(struct intel_plane *plane,
if (!wakeref)
return false;
ret = intel_de_read(dev_priv, DVSCNTR(plane->pipe)) & DVS_ENABLE;
ret = intel_de_read(display, DVSCNTR(plane->pipe)) & DVS_ENABLE;
*pipe = plane->pipe;
@ -1255,7 +1263,7 @@ static int
g4x_sprite_check_scaling(struct intel_crtc_state *crtc_state,
struct intel_plane_state *plane_state)
{
struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev);
struct intel_display *display = to_intel_display(crtc_state);
const struct drm_framebuffer *fb = plane_state->hw.fb;
const struct drm_rect *src = &plane_state->uapi.src;
const struct drm_rect *dst = &plane_state->uapi.dst;
@ -1281,7 +1289,8 @@ g4x_sprite_check_scaling(struct intel_crtc_state *crtc_state,
if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
if (src_h & 1) {
drm_dbg_kms(&i915->drm, "Source height must be even with interlaced modes\n");
drm_dbg_kms(display->drm,
"Source height must be even with interlaced modes\n");
return -EINVAL;
}
min_height = 6;
@ -1293,19 +1302,22 @@ g4x_sprite_check_scaling(struct intel_crtc_state *crtc_state,
if (src_w < min_width || src_h < min_height ||
src_w > 2048 || src_h > 2048) {
drm_dbg_kms(&i915->drm, "Source dimensions (%dx%d) exceed hardware limits (%dx%d - %dx%d)\n",
drm_dbg_kms(display->drm,
"Source dimensions (%dx%d) exceed hardware limits (%dx%d - %dx%d)\n",
src_w, src_h, min_width, min_height, 2048, 2048);
return -EINVAL;
}
if (width_bytes > 4096) {
drm_dbg_kms(&i915->drm, "Fetch width (%d) exceeds hardware max with scaling (%u)\n",
drm_dbg_kms(display->drm,
"Fetch width (%d) exceeds hardware max with scaling (%u)\n",
width_bytes, 4096);
return -EINVAL;
}
if (stride > 4096) {
drm_dbg_kms(&i915->drm, "Stride (%u) exceeds hardware max with scaling (%u)\n",
drm_dbg_kms(display->drm,
"Stride (%u) exceeds hardware max with scaling (%u)\n",
stride, 4096);
return -EINVAL;
}
@ -1317,6 +1329,7 @@ static int
g4x_sprite_check(struct intel_crtc_state *crtc_state,
struct intel_plane_state *plane_state)
{
struct intel_display *display = to_intel_display(crtc_state);
struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
int min_scale = DRM_PLANE_NO_SCALING;
@ -1324,7 +1337,7 @@ g4x_sprite_check(struct intel_crtc_state *crtc_state,
int ret;
if (g4x_fb_scalable(plane_state->hw.fb)) {
if (DISPLAY_VER(dev_priv) < 7) {
if (DISPLAY_VER(display) < 7) {
min_scale = 1;
max_scale = 16 << 16;
} else if (IS_IVYBRIDGE(dev_priv)) {
@ -1353,7 +1366,7 @@ g4x_sprite_check(struct intel_crtc_state *crtc_state,
if (ret)
return ret;
if (DISPLAY_VER(dev_priv) >= 7)
if (DISPLAY_VER(display) >= 7)
plane_state->ctl = ivb_sprite_ctl(crtc_state, plane_state);
else
plane_state->ctl = g4x_sprite_ctl(crtc_state, plane_state);
@ -1364,6 +1377,7 @@ g4x_sprite_check(struct intel_crtc_state *crtc_state,
int chv_plane_check_rotation(const struct intel_plane_state *plane_state)
{
struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
struct intel_display *display = to_intel_display(plane->base.dev);
struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
unsigned int rotation = plane_state->hw.rotation;
@ -1371,7 +1385,7 @@ int chv_plane_check_rotation(const struct intel_plane_state *plane_state)
if (IS_CHERRYVIEW(dev_priv) &&
rotation & DRM_MODE_ROTATE_180 &&
rotation & DRM_MODE_REFLECT_X) {
drm_dbg_kms(&dev_priv->drm,
drm_dbg_kms(display->drm,
"Cannot rotate and reflect at the same time\n");
return -EINVAL;
}
@ -1573,6 +1587,7 @@ struct intel_plane *
intel_sprite_plane_create(struct drm_i915_private *dev_priv,
enum pipe pipe, int sprite)
{
struct intel_display *display = &dev_priv->display;
struct intel_plane *plane;
const struct drm_plane_funcs *plane_funcs;
unsigned int supported_rotations;
@ -1604,7 +1619,7 @@ intel_sprite_plane_create(struct drm_i915_private *dev_priv,
}
plane_funcs = &vlv_sprite_funcs;
} else if (DISPLAY_VER(dev_priv) >= 7) {
} else if (DISPLAY_VER(display) >= 7) {
plane->update_noarm = ivb_sprite_update_noarm;
plane->update_arm = ivb_sprite_update_arm;
plane->disable_arm = ivb_sprite_disable_arm;
@ -1663,11 +1678,11 @@ intel_sprite_plane_create(struct drm_i915_private *dev_priv,
modifiers = intel_fb_plane_get_modifiers(dev_priv, INTEL_PLANE_CAP_TILING_X);
ret = drm_universal_plane_init(&dev_priv->drm, &plane->base,
ret = drm_universal_plane_init(display->drm, &plane->base,
0, plane_funcs,
formats, num_formats, modifiers,
DRM_PLANE_TYPE_OVERLAY,
"sprite %c", sprite_name(dev_priv, pipe, sprite));
"sprite %c", sprite_name(display, pipe, sprite));
kfree(modifiers);
if (ret)

203
drivers/gpu/drm/i915/display/intel_tv.c
View File

@ -914,8 +914,8 @@ static struct intel_tv *intel_attached_tv(struct intel_connector *connector)
static bool
intel_tv_get_hw_state(struct intel_encoder *encoder, enum pipe *pipe)
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
u32 tmp = intel_de_read(dev_priv, TV_CTL);
struct intel_display *display = to_intel_display(encoder);
u32 tmp = intel_de_read(display, TV_CTL);
*pipe = (tmp & TV_ENC_PIPE_SEL_MASK) >> TV_ENC_PIPE_SEL_SHIFT;
@ -928,13 +928,12 @@ intel_enable_tv(struct intel_atomic_state *state,
const struct intel_crtc_state *pipe_config,
const struct drm_connector_state *conn_state)
{
struct drm_device *dev = encoder->base.dev;
struct drm_i915_private *dev_priv = to_i915(dev);
struct intel_display *display = to_intel_display(state);
/* Prevents vblank waits from timing out in intel_tv_detect_type() */
intel_crtc_wait_for_next_vblank(to_intel_crtc(pipe_config->uapi.crtc));
intel_de_rmw(dev_priv, TV_CTL, 0, TV_ENC_ENABLE);
intel_de_rmw(display, TV_CTL, 0, TV_ENC_ENABLE);
}
static void
@ -943,10 +942,9 @@ intel_disable_tv(struct intel_atomic_state *state,
const struct intel_crtc_state *old_crtc_state,
const struct drm_connector_state *old_conn_state)
{
struct drm_device *dev = encoder->base.dev;
struct drm_i915_private *dev_priv = to_i915(dev);
struct intel_display *display = to_intel_display(state);
intel_de_rmw(dev_priv, TV_CTL, TV_ENC_ENABLE, 0);
intel_de_rmw(display, TV_CTL, TV_ENC_ENABLE, 0);
}
static const struct tv_mode *intel_tv_mode_find(const struct drm_connector_state *conn_state)
@ -960,9 +958,10 @@ static enum drm_mode_status
intel_tv_mode_valid(struct drm_connector *connector,
struct drm_display_mode *mode)
{
struct intel_display *display = to_intel_display(connector->dev);
struct drm_i915_private *i915 = to_i915(connector->dev);
const struct tv_mode *tv_mode = intel_tv_mode_find(connector->state);
int max_dotclk = i915->display.cdclk.max_dotclk_freq;
int max_dotclk = display->cdclk.max_dotclk_freq;
enum drm_mode_status status;
status = intel_cpu_transcoder_mode_valid(i915, mode);
@ -1092,6 +1091,7 @@ static void
intel_tv_get_config(struct intel_encoder *encoder,
struct intel_crtc_state *pipe_config)
{
struct intel_display *display = to_intel_display(encoder);
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
struct drm_display_mode *adjusted_mode =
&pipe_config->hw.adjusted_mode;
@ -1104,11 +1104,11 @@ intel_tv_get_config(struct intel_encoder *encoder,
pipe_config->output_types |= BIT(INTEL_OUTPUT_TVOUT);
tv_ctl = intel_de_read(dev_priv, TV_CTL);
hctl1 = intel_de_read(dev_priv, TV_H_CTL_1);
hctl3 = intel_de_read(dev_priv, TV_H_CTL_3);
vctl1 = intel_de_read(dev_priv, TV_V_CTL_1);
vctl2 = intel_de_read(dev_priv, TV_V_CTL_2);
tv_ctl = intel_de_read(display, TV_CTL);
hctl1 = intel_de_read(display, TV_H_CTL_1);
hctl3 = intel_de_read(display, TV_H_CTL_3);
vctl1 = intel_de_read(display, TV_V_CTL_1);
vctl2 = intel_de_read(display, TV_V_CTL_2);
tv_mode.htotal = (hctl1 & TV_HTOTAL_MASK) >> TV_HTOTAL_SHIFT;
tv_mode.hsync_end = (hctl1 & TV_HSYNC_END_MASK) >> TV_HSYNC_END_SHIFT;
@ -1143,17 +1143,17 @@ intel_tv_get_config(struct intel_encoder *encoder,
break;
}
tmp = intel_de_read(dev_priv, TV_WIN_POS);
tmp = intel_de_read(display, TV_WIN_POS);
xpos = tmp >> 16;
ypos = tmp & 0xffff;
tmp = intel_de_read(dev_priv, TV_WIN_SIZE);
tmp = intel_de_read(display, TV_WIN_SIZE);
xsize = tmp >> 16;
ysize = tmp & 0xffff;
intel_tv_mode_to_mode(&mode, &tv_mode, pipe_config->port_clock);
drm_dbg_kms(&dev_priv->drm, "TV mode: " DRM_MODE_FMT "\n",
drm_dbg_kms(display->drm, "TV mode: " DRM_MODE_FMT "\n",
DRM_MODE_ARG(&mode));
intel_tv_scale_mode_horiz(&mode, hdisplay,
@ -1171,10 +1171,10 @@ intel_tv_get_config(struct intel_encoder *encoder,
I915_MODE_FLAG_USE_SCANLINE_COUNTER;
}
static bool intel_tv_source_too_wide(struct drm_i915_private *dev_priv,
static bool intel_tv_source_too_wide(struct intel_display *display,
int hdisplay)
{
return DISPLAY_VER(dev_priv) == 3 && hdisplay > 1024;
return DISPLAY_VER(display) == 3 && hdisplay > 1024;
}
static bool intel_tv_vert_scaling(const struct drm_display_mode *tv_mode,
@ -1192,6 +1192,7 @@ intel_tv_compute_config(struct intel_encoder *encoder,
struct intel_crtc_state *pipe_config,
struct drm_connector_state *conn_state)
{
struct intel_display *display = to_intel_display(encoder);
struct intel_atomic_state *state =
to_intel_atomic_state(pipe_config->uapi.state);
struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
@ -1214,7 +1215,7 @@ intel_tv_compute_config(struct intel_encoder *encoder,
pipe_config->sink_format = INTEL_OUTPUT_FORMAT_RGB;
pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
drm_dbg_kms(&dev_priv->drm, "forcing bpc to 8 for TV\n");
drm_dbg_kms(display->drm, "forcing bpc to 8 for TV\n");
pipe_config->pipe_bpp = 8*3;
pipe_config->port_clock = tv_mode->clock;
@ -1228,14 +1229,14 @@ intel_tv_compute_config(struct intel_encoder *encoder,
intel_tv_mode_to_mode(adjusted_mode, tv_mode, pipe_config->port_clock);
drm_mode_set_crtcinfo(adjusted_mode, 0);
if (intel_tv_source_too_wide(dev_priv, hdisplay) ||
if (intel_tv_source_too_wide(display, hdisplay) ||
!intel_tv_vert_scaling(adjusted_mode, conn_state, vdisplay)) {
int extra, top, bottom;
extra = adjusted_mode->crtc_vdisplay - vdisplay;
if (extra < 0) {
drm_dbg_kms(&dev_priv->drm,
drm_dbg_kms(display->drm,
"No vertical scaling for >1024 pixel wide modes\n");
return -EINVAL;
}
@ -1269,7 +1270,7 @@ intel_tv_compute_config(struct intel_encoder *encoder,
tv_conn_state->bypass_vfilter = false;
}
drm_dbg_kms(&dev_priv->drm, "TV mode: " DRM_MODE_FMT "\n",
drm_dbg_kms(display->drm, "TV mode: " DRM_MODE_FMT "\n",
DRM_MODE_ARG(adjusted_mode));
/*
@ -1355,7 +1356,7 @@ intel_tv_compute_config(struct intel_encoder *encoder,
}
static void
set_tv_mode_timings(struct drm_i915_private *dev_priv,
set_tv_mode_timings(struct intel_display *display,
const struct tv_mode *tv_mode,
bool burst_ena)
{
@ -1401,32 +1402,32 @@ set_tv_mode_timings(struct drm_i915_private *dev_priv,
vctl7 = (tv_mode->vburst_start_f4 << TV_VBURST_START_F4_SHIFT) |
(tv_mode->vburst_end_f4 << TV_VBURST_END_F4_SHIFT);
intel_de_write(dev_priv, TV_H_CTL_1, hctl1);
intel_de_write(dev_priv, TV_H_CTL_2, hctl2);
intel_de_write(dev_priv, TV_H_CTL_3, hctl3);
intel_de_write(dev_priv, TV_V_CTL_1, vctl1);
intel_de_write(dev_priv, TV_V_CTL_2, vctl2);
intel_de_write(dev_priv, TV_V_CTL_3, vctl3);
intel_de_write(dev_priv, TV_V_CTL_4, vctl4);
intel_de_write(dev_priv, TV_V_CTL_5, vctl5);
intel_de_write(dev_priv, TV_V_CTL_6, vctl6);
intel_de_write(dev_priv, TV_V_CTL_7, vctl7);
intel_de_write(display, TV_H_CTL_1, hctl1);
intel_de_write(display, TV_H_CTL_2, hctl2);
intel_de_write(display, TV_H_CTL_3, hctl3);
intel_de_write(display, TV_V_CTL_1, vctl1);
intel_de_write(display, TV_V_CTL_2, vctl2);
intel_de_write(display, TV_V_CTL_3, vctl3);
intel_de_write(display, TV_V_CTL_4, vctl4);
intel_de_write(display, TV_V_CTL_5, vctl5);
intel_de_write(display, TV_V_CTL_6, vctl6);
intel_de_write(display, TV_V_CTL_7, vctl7);
}
static void set_color_conversion(struct drm_i915_private *dev_priv,
static void set_color_conversion(struct intel_display *display,
const struct color_conversion *color_conversion)
{
intel_de_write(dev_priv, TV_CSC_Y,
intel_de_write(display, TV_CSC_Y,
(color_conversion->ry << 16) | color_conversion->gy);
intel_de_write(dev_priv, TV_CSC_Y2,
intel_de_write(display, TV_CSC_Y2,
(color_conversion->by << 16) | color_conversion->ay);
intel_de_write(dev_priv, TV_CSC_U,
intel_de_write(display, TV_CSC_U,
(color_conversion->ru << 16) | color_conversion->gu);
intel_de_write(dev_priv, TV_CSC_U2,
intel_de_write(display, TV_CSC_U2,
(color_conversion->bu << 16) | color_conversion->au);
intel_de_write(dev_priv, TV_CSC_V,
intel_de_write(display, TV_CSC_V,
(color_conversion->rv << 16) | color_conversion->gv);
intel_de_write(dev_priv, TV_CSC_V2,
intel_de_write(display, TV_CSC_V2,
(color_conversion->bv << 16) | color_conversion->av);
}
@ -1435,6 +1436,7 @@ static void intel_tv_pre_enable(struct intel_atomic_state *state,
const struct intel_crtc_state *pipe_config,
const struct drm_connector_state *conn_state)
{
struct intel_display *display = to_intel_display(encoder);
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
struct intel_tv *intel_tv = enc_to_tv(encoder);
@ -1450,7 +1452,7 @@ static void intel_tv_pre_enable(struct intel_atomic_state *state,
int xpos, ypos;
unsigned int xsize, ysize;
tv_ctl = intel_de_read(dev_priv, TV_CTL);
tv_ctl = intel_de_read(display, TV_CTL);
tv_ctl &= TV_CTL_SAVE;
switch (intel_tv->type) {
@ -1525,21 +1527,21 @@ static void intel_tv_pre_enable(struct intel_atomic_state *state,
if (IS_I915GM(dev_priv))
tv_ctl |= TV_ENC_C0_FIX | TV_ENC_SDP_FIX;
set_tv_mode_timings(dev_priv, tv_mode, burst_ena);
set_tv_mode_timings(display, tv_mode, burst_ena);
intel_de_write(dev_priv, TV_SC_CTL_1, scctl1);
intel_de_write(dev_priv, TV_SC_CTL_2, scctl2);
intel_de_write(dev_priv, TV_SC_CTL_3, scctl3);
intel_de_write(display, TV_SC_CTL_1, scctl1);
intel_de_write(display, TV_SC_CTL_2, scctl2);
intel_de_write(display, TV_SC_CTL_3, scctl3);
set_color_conversion(dev_priv, color_conversion);
set_color_conversion(display, color_conversion);
if (DISPLAY_VER(dev_priv) >= 4)
intel_de_write(dev_priv, TV_CLR_KNOBS, 0x00404000);
if (DISPLAY_VER(display) >= 4)
intel_de_write(display, TV_CLR_KNOBS, 0x00404000);
else
intel_de_write(dev_priv, TV_CLR_KNOBS, 0x00606000);
intel_de_write(display, TV_CLR_KNOBS, 0x00606000);
if (video_levels)
intel_de_write(dev_priv, TV_CLR_LEVEL,
intel_de_write(display, TV_CLR_LEVEL,
((video_levels->black << TV_BLACK_LEVEL_SHIFT) | (video_levels->blank << TV_BLANK_LEVEL_SHIFT)));
assert_transcoder_disabled(dev_priv, pipe_config->cpu_transcoder);
@ -1548,7 +1550,7 @@ static void intel_tv_pre_enable(struct intel_atomic_state *state,
tv_filter_ctl = TV_AUTO_SCALE;
if (tv_conn_state->bypass_vfilter)
tv_filter_ctl |= TV_V_FILTER_BYPASS;
intel_de_write(dev_priv, TV_FILTER_CTL_1, tv_filter_ctl);
intel_de_write(display, TV_FILTER_CTL_1, tv_filter_ctl);
xsize = tv_mode->hblank_start - tv_mode->hblank_end;
ysize = intel_tv_mode_vdisplay(tv_mode);
@ -1559,31 +1561,32 @@ static void intel_tv_pre_enable(struct intel_atomic_state *state,
conn_state->tv.margins.right);
ysize -= (tv_conn_state->margins.top +
tv_conn_state->margins.bottom);
intel_de_write(dev_priv, TV_WIN_POS, (xpos << 16) | ypos);
intel_de_write(dev_priv, TV_WIN_SIZE, (xsize << 16) | ysize);
intel_de_write(display, TV_WIN_POS, (xpos << 16) | ypos);
intel_de_write(display, TV_WIN_SIZE, (xsize << 16) | ysize);
j = 0;
for (i = 0; i < 60; i++)
intel_de_write(dev_priv, TV_H_LUMA(i),
intel_de_write(display, TV_H_LUMA(i),
tv_mode->filter_table[j++]);
for (i = 0; i < 60; i++)
intel_de_write(dev_priv, TV_H_CHROMA(i),
intel_de_write(display, TV_H_CHROMA(i),
tv_mode->filter_table[j++]);
for (i = 0; i < 43; i++)
intel_de_write(dev_priv, TV_V_LUMA(i),
intel_de_write(display, TV_V_LUMA(i),
tv_mode->filter_table[j++]);
for (i = 0; i < 43; i++)
intel_de_write(dev_priv, TV_V_CHROMA(i),
intel_de_write(display, TV_V_CHROMA(i),
tv_mode->filter_table[j++]);
intel_de_write(dev_priv, TV_DAC,
intel_de_read(dev_priv, TV_DAC) & TV_DAC_SAVE);
intel_de_write(dev_priv, TV_CTL, tv_ctl);
intel_de_write(display, TV_DAC,
intel_de_read(display, TV_DAC) & TV_DAC_SAVE);
intel_de_write(display, TV_CTL, tv_ctl);
}
static int
intel_tv_detect_type(struct intel_tv *intel_tv,
struct drm_connector *connector)
{
struct intel_display *display = to_intel_display(connector->dev);
struct intel_crtc *crtc = to_intel_crtc(connector->state->crtc);
struct drm_device *dev = connector->dev;
struct drm_i915_private *dev_priv = to_i915(dev);
@ -1600,8 +1603,8 @@ intel_tv_detect_type(struct intel_tv *intel_tv,
spin_unlock_irq(&dev_priv->irq_lock);
}
save_tv_dac = tv_dac = intel_de_read(dev_priv, TV_DAC);
save_tv_ctl = tv_ctl = intel_de_read(dev_priv, TV_CTL);
save_tv_dac = tv_dac = intel_de_read(display, TV_DAC);
save_tv_ctl = tv_ctl = intel_de_read(display, TV_CTL);
/* Poll for TV detection */
tv_ctl &= ~(TV_ENC_ENABLE | TV_ENC_PIPE_SEL_MASK | TV_TEST_MODE_MASK);
@ -1627,15 +1630,15 @@ intel_tv_detect_type(struct intel_tv *intel_tv,
tv_dac &= ~(TVDAC_STATE_CHG_EN | TVDAC_A_SENSE_CTL |
TVDAC_B_SENSE_CTL | TVDAC_C_SENSE_CTL);
intel_de_write(dev_priv, TV_CTL, tv_ctl);
intel_de_write(dev_priv, TV_DAC, tv_dac);
intel_de_posting_read(dev_priv, TV_DAC);
intel_de_write(display, TV_CTL, tv_ctl);
intel_de_write(display, TV_DAC, tv_dac);
intel_de_posting_read(display, TV_DAC);
intel_crtc_wait_for_next_vblank(crtc);
type = -1;
tv_dac = intel_de_read(dev_priv, TV_DAC);
drm_dbg_kms(&dev_priv->drm, "TV detected: %x, %x\n", tv_ctl, tv_dac);
tv_dac = intel_de_read(display, TV_DAC);
drm_dbg_kms(display->drm, "TV detected: %x, %x\n", tv_ctl, tv_dac);
/*
* A B C
* 0 1 1 Composite
@ -1643,25 +1646,25 @@ intel_tv_detect_type(struct intel_tv *intel_tv,
* 0 0 0 Component
*/
if ((tv_dac & TVDAC_SENSE_MASK) == (TVDAC_B_SENSE | TVDAC_C_SENSE)) {
drm_dbg_kms(&dev_priv->drm,
drm_dbg_kms(display->drm,
"Detected Composite TV connection\n");
type = DRM_MODE_CONNECTOR_Composite;
} else if ((tv_dac & (TVDAC_A_SENSE|TVDAC_B_SENSE)) == TVDAC_A_SENSE) {
drm_dbg_kms(&dev_priv->drm,
drm_dbg_kms(display->drm,
"Detected S-Video TV connection\n");
type = DRM_MODE_CONNECTOR_SVIDEO;
} else if ((tv_dac & TVDAC_SENSE_MASK) == 0) {
drm_dbg_kms(&dev_priv->drm,
drm_dbg_kms(display->drm,
"Detected Component TV connection\n");
type = DRM_MODE_CONNECTOR_Component;
} else {
drm_dbg_kms(&dev_priv->drm, "Unrecognised TV connection\n");
drm_dbg_kms(display->drm, "Unrecognised TV connection\n");
type = -1;
}
intel_de_write(dev_priv, TV_DAC, save_tv_dac & ~TVDAC_STATE_CHG_EN);
intel_de_write(dev_priv, TV_CTL, save_tv_ctl);
intel_de_posting_read(dev_priv, TV_CTL);
intel_de_write(display, TV_DAC, save_tv_dac & ~TVDAC_STATE_CHG_EN);
intel_de_write(display, TV_CTL, save_tv_ctl);
intel_de_posting_read(display, TV_CTL);
/* For unknown reasons the hw barfs if we don't do this vblank wait. */
intel_crtc_wait_for_next_vblank(crtc);
@ -1711,12 +1714,13 @@ intel_tv_detect(struct drm_connector *connector,
struct drm_modeset_acquire_ctx *ctx,
bool force)
{
struct intel_display *display = to_intel_display(connector->dev);
struct drm_i915_private *i915 = to_i915(connector->dev);
struct intel_tv *intel_tv = intel_attached_tv(to_intel_connector(connector));
enum drm_connector_status status;
int type;
drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s] force=%d\n",
drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s] force=%d\n",
connector->base.id, connector->name, force);
if (!intel_display_device_enabled(i915))
@ -1791,7 +1795,7 @@ intel_tv_set_mode_type(struct drm_display_mode *mode,
static int
intel_tv_get_modes(struct drm_connector *connector)
{
struct drm_i915_private *dev_priv = to_i915(connector->dev);
struct intel_display *display = to_intel_display(connector->dev);
const struct tv_mode *tv_mode = intel_tv_mode_find(connector->state);
int i, count = 0;
@ -1805,7 +1809,7 @@ intel_tv_get_modes(struct drm_connector *connector)
continue;
/* no vertical scaling with wide sources on gen3 */
if (DISPLAY_VER(dev_priv) == 3 && input->w > 1024 &&
if (DISPLAY_VER(display) == 3 && input->w > 1024 &&
input->h > intel_tv_mode_vdisplay(tv_mode))
continue;
@ -1822,7 +1826,8 @@ intel_tv_get_modes(struct drm_connector *connector)
*/
intel_tv_mode_to_mode(mode, tv_mode, tv_mode->clock);
if (count == 0) {
drm_dbg_kms(&dev_priv->drm, "TV mode: " DRM_MODE_FMT "\n",
drm_dbg_kms(display->drm,
"TV mode: " DRM_MODE_FMT "\n",
DRM_MODE_ARG(mode));
}
intel_tv_scale_mode_horiz(mode, input->w, 0, 0);
@ -1887,7 +1892,7 @@ static const struct drm_encoder_funcs intel_tv_enc_funcs = {
static void intel_tv_add_properties(struct drm_connector *connector)
{
struct drm_i915_private *i915 = to_i915(connector->dev);
struct intel_display *display = to_intel_display(connector->dev);
struct drm_connector_state *conn_state = connector->state;
const char *tv_format_names[ARRAY_SIZE(tv_modes)];
int i;
@ -1903,45 +1908,44 @@ static void intel_tv_add_properties(struct drm_connector *connector)
/* Create TV properties then attach current values */
for (i = 0; i < ARRAY_SIZE(tv_modes); i++) {
/* 1080p50/1080p60 not supported on gen3 */
if (DISPLAY_VER(i915) == 3 && tv_modes[i].oversample == 1)
if (DISPLAY_VER(display) == 3 && tv_modes[i].oversample == 1)
break;
tv_format_names[i] = tv_modes[i].name;
}
drm_mode_create_tv_properties_legacy(&i915->drm, i, tv_format_names);
drm_mode_create_tv_properties_legacy(display->drm, i, tv_format_names);
drm_object_attach_property(&connector->base,
i915->drm.mode_config.legacy_tv_mode_property,
display->drm->mode_config.legacy_tv_mode_property,
conn_state->tv.legacy_mode);
drm_object_attach_property(&connector->base,
i915->drm.mode_config.tv_left_margin_property,
display->drm->mode_config.tv_left_margin_property,
conn_state->tv.margins.left);
drm_object_attach_property(&connector->base,
i915->drm.mode_config.tv_top_margin_property,
display->drm->mode_config.tv_top_margin_property,
conn_state->tv.margins.top);
drm_object_attach_property(&connector->base,
i915->drm.mode_config.tv_right_margin_property,
display->drm->mode_config.tv_right_margin_property,
conn_state->tv.margins.right);
drm_object_attach_property(&connector->base,
i915->drm.mode_config.tv_bottom_margin_property,
display->drm->mode_config.tv_bottom_margin_property,
conn_state->tv.margins.bottom);
}
void
intel_tv_init(struct drm_i915_private *dev_priv)
intel_tv_init(struct intel_display *display)
{
struct intel_display *display = &dev_priv->display;
struct drm_connector *connector;
struct intel_tv *intel_tv;
struct intel_encoder *intel_encoder;
struct intel_connector *intel_connector;
u32 tv_dac_on, tv_dac_off, save_tv_dac;
if ((intel_de_read(dev_priv, TV_CTL) & TV_FUSE_STATE_MASK) == TV_FUSE_STATE_DISABLED)
if ((intel_de_read(display, TV_CTL) & TV_FUSE_STATE_MASK) == TV_FUSE_STATE_DISABLED)
return;
if (!intel_bios_is_tv_present(display)) {
drm_dbg_kms(&dev_priv->drm, "Integrated TV is not present.\n");
drm_dbg_kms(display->drm, "Integrated TV is not present.\n");
return;
}
@ -1949,15 +1953,15 @@ intel_tv_init(struct drm_i915_private *dev_priv)
* Sanity check the TV output by checking to see if the
* DAC register holds a value
*/
save_tv_dac = intel_de_read(dev_priv, TV_DAC);
save_tv_dac = intel_de_read(display, TV_DAC);
intel_de_write(dev_priv, TV_DAC, save_tv_dac | TVDAC_STATE_CHG_EN);
tv_dac_on = intel_de_read(dev_priv, TV_DAC);
intel_de_write(display, TV_DAC, save_tv_dac | TVDAC_STATE_CHG_EN);
tv_dac_on = intel_de_read(display, TV_DAC);
intel_de_write(dev_priv, TV_DAC, save_tv_dac & ~TVDAC_STATE_CHG_EN);
tv_dac_off = intel_de_read(dev_priv, TV_DAC);
intel_de_write(display, TV_DAC, save_tv_dac & ~TVDAC_STATE_CHG_EN);
tv_dac_off = intel_de_read(display, TV_DAC);
intel_de_write(dev_priv, TV_DAC, save_tv_dac);
intel_de_write(display, TV_DAC, save_tv_dac);
/*
* If the register does not hold the state change enable
@ -1995,10 +1999,11 @@ intel_tv_init(struct drm_i915_private *dev_priv)
intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT;
intel_connector->base.polled = intel_connector->polled;
drm_connector_init(&dev_priv->drm, connector, &intel_tv_connector_funcs,
drm_connector_init(display->drm, connector, &intel_tv_connector_funcs,
DRM_MODE_CONNECTOR_SVIDEO);
drm_encoder_init(&dev_priv->drm, &intel_encoder->base, &intel_tv_enc_funcs,
drm_encoder_init(display->drm, &intel_encoder->base,
&intel_tv_enc_funcs,
DRM_MODE_ENCODER_TVDAC, "TV");
intel_encoder->compute_config = intel_tv_compute_config;

6
drivers/gpu/drm/i915/display/intel_tv.h
View File

@ -6,12 +6,12 @@
#ifndef __INTEL_TV_H__
#define __INTEL_TV_H__
struct drm_i915_private;
struct intel_display;
#ifdef I915
void intel_tv_init(struct drm_i915_private *dev_priv);
void intel_tv_init(struct intel_display *display);
#else
static inline void intel_tv_init(struct drm_i915_private *dev_priv)
static inline void intel_tv_init(struct intel_display *display)
{
}
#endif

122
drivers/gpu/drm/i915/display/intel_vblank.c
View File

@ -67,8 +67,8 @@
*/
u32 i915_get_vblank_counter(struct drm_crtc *crtc)
{
struct drm_i915_private *dev_priv = to_i915(crtc->dev);
struct drm_vblank_crtc *vblank = &dev_priv->drm.vblank[drm_crtc_index(crtc)];
struct intel_display *display = to_intel_display(crtc->dev);
struct drm_vblank_crtc *vblank = drm_crtc_vblank_crtc(crtc);
const struct drm_display_mode *mode = &vblank->hwmode;
enum pipe pipe = to_intel_crtc(crtc)->pipe;
u32 pixel, vbl_start, hsync_start, htotal;
@ -103,8 +103,8 @@ u32 i915_get_vblank_counter(struct drm_crtc *crtc)
* we get a low value that's stable across two reads of the high
* register.
*/
frame = intel_de_read64_2x32(dev_priv, PIPEFRAMEPIXEL(dev_priv, pipe),
PIPEFRAME(dev_priv, pipe));
frame = intel_de_read64_2x32(display, PIPEFRAMEPIXEL(display, pipe),
PIPEFRAME(display, pipe));
pixel = frame & PIPE_PIXEL_MASK;
frame = (frame >> PIPE_FRAME_LOW_SHIFT) & 0xffffff;
@ -119,19 +119,19 @@ u32 i915_get_vblank_counter(struct drm_crtc *crtc)
u32 g4x_get_vblank_counter(struct drm_crtc *crtc)
{
struct drm_i915_private *dev_priv = to_i915(crtc->dev);
struct drm_vblank_crtc *vblank = &dev_priv->drm.vblank[drm_crtc_index(crtc)];
struct intel_display *display = to_intel_display(crtc->dev);
struct drm_vblank_crtc *vblank = drm_crtc_vblank_crtc(crtc);
enum pipe pipe = to_intel_crtc(crtc)->pipe;
if (!vblank->max_vblank_count)
return 0;
return intel_de_read(dev_priv, PIPE_FRMCOUNT_G4X(dev_priv, pipe));
return intel_de_read(display, PIPE_FRMCOUNT_G4X(display, pipe));
}
static u32 intel_crtc_scanlines_since_frame_timestamp(struct intel_crtc *crtc)
{
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
struct intel_display *display = to_intel_display(crtc);
struct drm_vblank_crtc *vblank = drm_crtc_vblank_crtc(&crtc->base);
const struct drm_display_mode *mode = &vblank->hwmode;
u32 htotal = mode->crtc_htotal;
@ -150,16 +150,16 @@ static u32 intel_crtc_scanlines_since_frame_timestamp(struct intel_crtc *crtc)
* pipe frame time stamp. The time stamp value
* is sampled at every start of vertical blank.
*/
scan_prev_time = intel_de_read_fw(dev_priv,
scan_prev_time = intel_de_read_fw(display,
PIPE_FRMTMSTMP(crtc->pipe));
/*
* The TIMESTAMP_CTR register has the current
* time stamp value.
*/
scan_curr_time = intel_de_read_fw(dev_priv, IVB_TIMESTAMP_CTR);
scan_curr_time = intel_de_read_fw(display, IVB_TIMESTAMP_CTR);
scan_post_time = intel_de_read_fw(dev_priv,
scan_post_time = intel_de_read_fw(display,
PIPE_FRMTMSTMP(crtc->pipe));
} while (scan_post_time != scan_prev_time);
@ -190,8 +190,9 @@ static u32 __intel_get_crtc_scanline_from_timestamp(struct intel_crtc *crtc)
return scanline;
}
static int intel_crtc_scanline_offset(const struct intel_crtc_state *crtc_state)
int intel_crtc_scanline_offset(const struct intel_crtc_state *crtc_state)
{
struct intel_display *display = to_intel_display(crtc_state);
struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
/*
@ -220,7 +221,7 @@ static int intel_crtc_scanline_offset(const struct intel_crtc_state *crtc_state)
* However if queried just before the start of vblank we'll get an
* answer that's slightly in the future.
*/
if (DISPLAY_VER(i915) == 2)
if (DISPLAY_VER(display) == 2)
return -1;
else if (HAS_DDI(i915) && intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
return 2;
@ -234,8 +235,7 @@ static int intel_crtc_scanline_offset(const struct intel_crtc_state *crtc_state)
*/
static int __intel_get_crtc_scanline(struct intel_crtc *crtc)
{
struct drm_device *dev = crtc->base.dev;
struct drm_i915_private *dev_priv = to_i915(dev);
struct intel_display *display = to_intel_display(crtc);
struct drm_vblank_crtc *vblank = drm_crtc_vblank_crtc(&crtc->base);
const struct drm_display_mode *mode = &vblank->hwmode;
enum pipe pipe = crtc->pipe;
@ -249,7 +249,7 @@ static int __intel_get_crtc_scanline(struct intel_crtc *crtc)
vtotal = intel_mode_vtotal(mode);
position = intel_de_read_fw(dev_priv, PIPEDSL(dev_priv, pipe)) & PIPEDSL_LINE_MASK;
position = intel_de_read_fw(display, PIPEDSL(display, pipe)) & PIPEDSL_LINE_MASK;
/*
* On HSW, the DSL reg (0x70000) appears to return 0 if we
@ -263,13 +263,13 @@ static int __intel_get_crtc_scanline(struct intel_crtc *crtc)
* problem. We may need to extend this to include other platforms,
* but so far testing only shows the problem on HSW.
*/
if (HAS_DDI(dev_priv) && !position) {
if (HAS_DDI(display) && !position) {
int i, temp;
for (i = 0; i < 100; i++) {
udelay(1);
temp = intel_de_read_fw(dev_priv,
PIPEDSL(dev_priv, pipe)) & PIPEDSL_LINE_MASK;
temp = intel_de_read_fw(display,
PIPEDSL(display, pipe)) & PIPEDSL_LINE_MASK;
if (temp != position) {
position = temp;
break;
@ -284,15 +284,6 @@ static int __intel_get_crtc_scanline(struct intel_crtc *crtc)
return (position + vtotal + crtc->scanline_offset) % vtotal;
}
int intel_crtc_scanline_to_hw(struct intel_crtc *crtc, int scanline)
{
const struct drm_vblank_crtc *vblank = drm_crtc_vblank_crtc(&crtc->base);
const struct drm_display_mode *mode = &vblank->hwmode;
int vtotal = intel_mode_vtotal(mode);
return (scanline + vtotal - crtc->scanline_offset) % vtotal;
}
/*
* The uncore version of the spin lock functions is used to decide
* whether we need to lock the uncore lock or not. This is only
@ -303,21 +294,29 @@ int intel_crtc_scanline_to_hw(struct intel_crtc *crtc, int scanline)
* all register accesses to the same cacheline to be serialized,
* otherwise they may hang.
*/
static void intel_vblank_section_enter(struct drm_i915_private *i915)
#ifdef I915
static void intel_vblank_section_enter(struct intel_display *display)
__acquires(i915->uncore.lock)
{
#ifdef I915
struct drm_i915_private *i915 = to_i915(display->drm);
spin_lock(&i915->uncore.lock);
#endif
}
static void intel_vblank_section_exit(struct drm_i915_private *i915)
static void intel_vblank_section_exit(struct intel_display *display)
__releases(i915->uncore.lock)
{
#ifdef I915
struct drm_i915_private *i915 = to_i915(display->drm);
spin_unlock(&i915->uncore.lock);
#endif
}
#else
static void intel_vblank_section_enter(struct intel_display *display)
{
}
static void intel_vblank_section_exit(struct intel_display *display)
{
}
#endif
static bool i915_get_crtc_scanoutpos(struct drm_crtc *_crtc,
bool in_vblank_irq,
@ -325,19 +324,19 @@ static bool i915_get_crtc_scanoutpos(struct drm_crtc *_crtc,
ktime_t *stime, ktime_t *etime,
const struct drm_display_mode *mode)
{
struct drm_device *dev = _crtc->dev;
struct drm_i915_private *dev_priv = to_i915(dev);
struct intel_display *display = to_intel_display(_crtc->dev);
struct drm_i915_private *dev_priv = to_i915(display->drm);
struct intel_crtc *crtc = to_intel_crtc(_crtc);
enum pipe pipe = crtc->pipe;
int position;
int vbl_start, vbl_end, hsync_start, htotal, vtotal;
unsigned long irqflags;
bool use_scanline_counter = DISPLAY_VER(dev_priv) >= 5 ||
IS_G4X(dev_priv) || DISPLAY_VER(dev_priv) == 2 ||
bool use_scanline_counter = DISPLAY_VER(display) >= 5 ||
IS_G4X(dev_priv) || DISPLAY_VER(display) == 2 ||
crtc->mode_flags & I915_MODE_FLAG_USE_SCANLINE_COUNTER;
if (drm_WARN_ON(&dev_priv->drm, !mode->crtc_clock)) {
drm_dbg(&dev_priv->drm,
if (drm_WARN_ON(display->drm, !mode->crtc_clock)) {
drm_dbg(display->drm,
"trying to get scanoutpos for disabled pipe %c\n",
pipe_name(pipe));
return false;
@ -355,7 +354,7 @@ static bool i915_get_crtc_scanoutpos(struct drm_crtc *_crtc,
* preemption disabled, so the following code must not block.
*/
local_irq_save(irqflags);
intel_vblank_section_enter(dev_priv);
intel_vblank_section_enter(display);
/* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */
@ -387,7 +386,7 @@ static bool i915_get_crtc_scanoutpos(struct drm_crtc *_crtc,
* We can split this into vertical and horizontal
* scanout position.
*/
position = (intel_de_read_fw(dev_priv, PIPEFRAMEPIXEL(dev_priv, pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;
position = (intel_de_read_fw(display, PIPEFRAMEPIXEL(display, pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;
/* convert to pixel counts */
vbl_start *= htotal;
@ -423,7 +422,7 @@ static bool i915_get_crtc_scanoutpos(struct drm_crtc *_crtc,
/* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */
intel_vblank_section_exit(dev_priv);
intel_vblank_section_exit(display);
local_irq_restore(irqflags);
/*
@ -458,42 +457,42 @@ bool intel_crtc_get_vblank_timestamp(struct drm_crtc *crtc, int *max_error,
int intel_get_crtc_scanline(struct intel_crtc *crtc)
{
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
struct intel_display *display = to_intel_display(crtc);
unsigned long irqflags;
int position;
local_irq_save(irqflags);
intel_vblank_section_enter(dev_priv);
intel_vblank_section_enter(display);
position = __intel_get_crtc_scanline(crtc);
intel_vblank_section_exit(dev_priv);
intel_vblank_section_exit(display);
local_irq_restore(irqflags);
return position;
}
static bool pipe_scanline_is_moving(struct drm_i915_private *dev_priv,
static bool pipe_scanline_is_moving(struct intel_display *display,
enum pipe pipe)
{
i915_reg_t reg = PIPEDSL(dev_priv, pipe);
i915_reg_t reg = PIPEDSL(display, pipe);
u32 line1, line2;
line1 = intel_de_read(dev_priv, reg) & PIPEDSL_LINE_MASK;
line1 = intel_de_read(display, reg) & PIPEDSL_LINE_MASK;
msleep(5);
line2 = intel_de_read(dev_priv, reg) & PIPEDSL_LINE_MASK;
line2 = intel_de_read(display, reg) & PIPEDSL_LINE_MASK;
return line1 != line2;
}
static void wait_for_pipe_scanline_moving(struct intel_crtc *crtc, bool state)
{
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
struct intel_display *display = to_intel_display(crtc);
enum pipe pipe = crtc->pipe;
/* Wait for the display line to settle/start moving */
if (wait_for(pipe_scanline_is_moving(dev_priv, pipe) == state, 100))
drm_err(&dev_priv->drm,
if (wait_for(pipe_scanline_is_moving(display, pipe) == state, 100))
drm_err(display->drm,
"pipe %c scanline %s wait timed out\n",
pipe_name(pipe), str_on_off(state));
}
@ -511,8 +510,8 @@ void intel_wait_for_pipe_scanline_moving(struct intel_crtc *crtc)
void intel_crtc_update_active_timings(const struct intel_crtc_state *crtc_state,
bool vrr_enable)
{
struct intel_display *display = to_intel_display(crtc_state);
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_i915_private *i915 = to_i915(crtc->base.dev);
u8 mode_flags = crtc_state->mode_flags;
struct drm_display_mode adjusted_mode;
int vmax_vblank_start = 0;
@ -521,7 +520,8 @@ void intel_crtc_update_active_timings(const struct intel_crtc_state *crtc_state,
drm_mode_init(&adjusted_mode, &crtc_state->hw.adjusted_mode);
if (vrr_enable) {
drm_WARN_ON(&i915->drm, (mode_flags & I915_MODE_FLAG_VRR) == 0);
drm_WARN_ON(display->drm,
(mode_flags & I915_MODE_FLAG_VRR) == 0);
adjusted_mode.crtc_vtotal = crtc_state->vrr.vmax;
adjusted_mode.crtc_vblank_end = crtc_state->vrr.vmax;
@ -543,8 +543,8 @@ void intel_crtc_update_active_timings(const struct intel_crtc_state *crtc_state,
* __intel_get_crtc_scanline()) with vblank_time_lock?
* Need to audit everything to make sure it's safe.
*/
spin_lock_irqsave(&i915->drm.vblank_time_lock, irqflags);
intel_vblank_section_enter(i915);
spin_lock_irqsave(&display->drm->vblank_time_lock, irqflags);
intel_vblank_section_enter(display);
drm_calc_timestamping_constants(&crtc->base, &adjusted_mode);
@ -553,8 +553,8 @@ void intel_crtc_update_active_timings(const struct intel_crtc_state *crtc_state,
crtc->mode_flags = mode_flags;
crtc->scanline_offset = intel_crtc_scanline_offset(crtc_state);
intel_vblank_section_exit(i915);
spin_unlock_irqrestore(&i915->drm.vblank_time_lock, irqflags);
intel_vblank_section_exit(display);
spin_unlock_irqrestore(&display->drm->vblank_time_lock, irqflags);
}
int intel_mode_vdisplay(const struct drm_display_mode *mode)
@ -660,7 +660,7 @@ void intel_vblank_evade_init(const struct intel_crtc_state *old_crtc_state,
int intel_vblank_evade(struct intel_vblank_evade_ctx *evade)
{
struct intel_crtc *crtc = evade->crtc;
struct drm_i915_private *i915 = to_i915(crtc->base.dev);
struct intel_display *display = to_intel_display(crtc);
long timeout = msecs_to_jiffies_timeout(1);
wait_queue_head_t *wq = drm_crtc_vblank_waitqueue(&crtc->base);
DEFINE_WAIT(wait);
@ -682,7 +682,7 @@ int intel_vblank_evade(struct intel_vblank_evade_ctx *evade)
break;
if (!timeout) {
drm_err(&i915->drm,
drm_err(display->drm,
"Potential atomic update failure on pipe %c\n",
pipe_name(crtc->pipe));
break;

2
drivers/gpu/drm/i915/display/intel_vblank.h
View File

@ -40,6 +40,6 @@ void intel_wait_for_pipe_scanline_stopped(struct intel_crtc *crtc);
void intel_wait_for_pipe_scanline_moving(struct intel_crtc *crtc);
void intel_crtc_update_active_timings(const struct intel_crtc_state *crtc_state,
bool vrr_enable);
int intel_crtc_scanline_to_hw(struct intel_crtc *crtc, int scanline);
int intel_crtc_scanline_offset(const struct intel_crtc_state *crtc_state);
#endif /* __INTEL_VBLANK_H__ */

127
drivers/gpu/drm/i915/display/intel_vrr.c
View File

@ -17,8 +17,8 @@
bool intel_vrr_is_capable(struct intel_connector *connector)
{
struct intel_display *display = to_intel_display(connector);
const struct drm_display_info *info = &connector->base.display_info;
struct drm_i915_private *i915 = to_i915(connector->base.dev);
struct intel_dp *intel_dp;
/*
@ -43,7 +43,7 @@ bool intel_vrr_is_capable(struct intel_connector *connector)
return false;
}
return HAS_VRR(i915) &&
return HAS_VRR(display) &&
info->monitor_range.max_vfreq - info->monitor_range.min_vfreq > 10;
}
@ -89,10 +89,9 @@ intel_vrr_check_modeset(struct intel_atomic_state *state)
*/
static int intel_vrr_vblank_exit_length(const struct intel_crtc_state *crtc_state)
{
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_i915_private *i915 = to_i915(crtc->base.dev);
struct intel_display *display = to_intel_display(crtc_state);
if (DISPLAY_VER(i915) >= 13)
if (DISPLAY_VER(display) >= 13)
return crtc_state->vrr.guardband;
else
/* The hw imposes the extra scanline before frame start */
@ -113,11 +112,11 @@ int intel_vrr_vmax_vblank_start(const struct intel_crtc_state *crtc_state)
static bool
is_cmrr_frac_required(struct intel_crtc_state *crtc_state)
{
struct intel_display *display = to_intel_display(crtc_state);
int calculated_refresh_k, actual_refresh_k, pixel_clock_per_line;
struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
if (!HAS_CMRR(i915))
if (!HAS_CMRR(display))
return false;
actual_refresh_k =
@ -161,8 +160,7 @@ void
intel_vrr_compute_config(struct intel_crtc_state *crtc_state,
struct drm_connector_state *conn_state)
{
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_i915_private *i915 = to_i915(crtc->base.dev);
struct intel_display *display = to_intel_display(crtc_state);
struct intel_connector *connector =
to_intel_connector(conn_state->connector);
struct intel_dp *intel_dp = intel_attached_dp(connector);
@ -186,7 +184,7 @@ intel_vrr_compute_config(struct intel_crtc_state *crtc_state,
if (!crtc_state->vrr.in_range)
return;
if (HAS_LRR(i915))
if (HAS_LRR(display))
crtc_state->update_lrr = true;
vmin = DIV_ROUND_UP(adjusted_mode->crtc_clock * 1000,
@ -246,7 +244,7 @@ intel_vrr_compute_config(struct intel_crtc_state *crtc_state,
* For XE_LPD+, we use guardband and pipeline override
* is deprecated.
*/
if (DISPLAY_VER(i915) >= 13) {
if (DISPLAY_VER(display) >= 13) {
crtc_state->vrr.guardband =
crtc_state->vrr.vmin + 1 - adjusted_mode->crtc_vblank_start;
} else {
@ -258,9 +256,9 @@ intel_vrr_compute_config(struct intel_crtc_state *crtc_state,
static u32 trans_vrr_ctl(const struct intel_crtc_state *crtc_state)
{
struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
struct intel_display *display = to_intel_display(crtc_state);
if (DISPLAY_VER(i915) >= 13)
if (DISPLAY_VER(display) >= 13)
return VRR_CTL_IGN_MAX_SHIFT | VRR_CTL_FLIP_LINE_EN |
XELPD_VRR_CTL_VRR_GUARDBAND(crtc_state->vrr.guardband);
else
@ -271,7 +269,7 @@ static u32 trans_vrr_ctl(const struct intel_crtc_state *crtc_state)
void intel_vrr_set_transcoder_timings(const struct intel_crtc_state *crtc_state)
{
struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
struct intel_display *display = to_intel_display(crtc_state);
enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
/*
@ -279,133 +277,130 @@ void intel_vrr_set_transcoder_timings(const struct intel_crtc_state *crtc_state)
* TGL: generate VRR "safe window" for DSB vblank waits
* ADL/DG2: make TRANS_SET_CONTEXT_LATENCY effective with VRR
*/
if (IS_DISPLAY_VER(dev_priv, 12, 13))
intel_de_rmw(dev_priv, CHICKEN_TRANS(cpu_transcoder),
if (IS_DISPLAY_VER(display, 12, 13))
intel_de_rmw(display, CHICKEN_TRANS(cpu_transcoder),
0, PIPE_VBLANK_WITH_DELAY);
if (!crtc_state->vrr.flipline) {
intel_de_write(dev_priv,
TRANS_VRR_CTL(dev_priv, cpu_transcoder), 0);
intel_de_write(display,
TRANS_VRR_CTL(display, cpu_transcoder), 0);
return;
}
if (crtc_state->cmrr.enable) {
intel_de_write(dev_priv, TRANS_CMRR_M_HI(dev_priv, cpu_transcoder),
intel_de_write(display, TRANS_CMRR_M_HI(display, cpu_transcoder),
upper_32_bits(crtc_state->cmrr.cmrr_m));
intel_de_write(dev_priv, TRANS_CMRR_M_LO(dev_priv, cpu_transcoder),
intel_de_write(display, TRANS_CMRR_M_LO(display, cpu_transcoder),
lower_32_bits(crtc_state->cmrr.cmrr_m));
intel_de_write(dev_priv, TRANS_CMRR_N_HI(dev_priv, cpu_transcoder),
intel_de_write(display, TRANS_CMRR_N_HI(display, cpu_transcoder),
upper_32_bits(crtc_state->cmrr.cmrr_n));
intel_de_write(dev_priv, TRANS_CMRR_N_LO(dev_priv, cpu_transcoder),
intel_de_write(display, TRANS_CMRR_N_LO(display, cpu_transcoder),
lower_32_bits(crtc_state->cmrr.cmrr_n));
}
intel_de_write(dev_priv, TRANS_VRR_VMIN(dev_priv, cpu_transcoder),
intel_de_write(display, TRANS_VRR_VMIN(display, cpu_transcoder),
crtc_state->vrr.vmin - 1);
intel_de_write(dev_priv, TRANS_VRR_VMAX(dev_priv, cpu_transcoder),
intel_de_write(display, TRANS_VRR_VMAX(display, cpu_transcoder),
crtc_state->vrr.vmax - 1);
intel_de_write(dev_priv, TRANS_VRR_CTL(dev_priv, cpu_transcoder),
intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder),
trans_vrr_ctl(crtc_state));
intel_de_write(dev_priv, TRANS_VRR_FLIPLINE(dev_priv, cpu_transcoder),
intel_de_write(display, TRANS_VRR_FLIPLINE(display, cpu_transcoder),
crtc_state->vrr.flipline - 1);
}
void intel_vrr_send_push(const struct intel_crtc_state *crtc_state)
{
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
struct intel_display *display = to_intel_display(crtc_state);
enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
if (!crtc_state->vrr.enable)
return;
intel_de_write(dev_priv, TRANS_PUSH(dev_priv, cpu_transcoder),
intel_de_write(display, TRANS_PUSH(display, cpu_transcoder),
TRANS_PUSH_EN | TRANS_PUSH_SEND);
}
bool intel_vrr_is_push_sent(const struct intel_crtc_state *crtc_state)
{
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
struct intel_display *display = to_intel_display(crtc_state);
enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
if (!crtc_state->vrr.enable)
return false;
return intel_de_read(dev_priv, TRANS_PUSH(dev_priv, cpu_transcoder)) & TRANS_PUSH_SEND;
return intel_de_read(display, TRANS_PUSH(display, cpu_transcoder)) & TRANS_PUSH_SEND;
}
void intel_vrr_enable(const struct intel_crtc_state *crtc_state)
{
struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
struct intel_display *display = to_intel_display(crtc_state);
enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
if (!crtc_state->vrr.enable)
return;
intel_de_write(dev_priv, TRANS_PUSH(dev_priv, cpu_transcoder),
intel_de_write(display, TRANS_PUSH(display, cpu_transcoder),
TRANS_PUSH_EN);
if (HAS_AS_SDP(dev_priv))
intel_de_write(dev_priv,
TRANS_VRR_VSYNC(dev_priv, cpu_transcoder),
if (HAS_AS_SDP(display))
intel_de_write(display,
TRANS_VRR_VSYNC(display, cpu_transcoder),
VRR_VSYNC_END(crtc_state->vrr.vsync_end) |
VRR_VSYNC_START(crtc_state->vrr.vsync_start));
if (crtc_state->cmrr.enable) {
intel_de_write(dev_priv, TRANS_VRR_CTL(dev_priv, cpu_transcoder),
intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder),
VRR_CTL_VRR_ENABLE | VRR_CTL_CMRR_ENABLE |
trans_vrr_ctl(crtc_state));
} else {
intel_de_write(dev_priv, TRANS_VRR_CTL(dev_priv, cpu_transcoder),
intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder),
VRR_CTL_VRR_ENABLE | trans_vrr_ctl(crtc_state));
}
}
void intel_vrr_disable(const struct intel_crtc_state *old_crtc_state)
{
struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
struct intel_display *display = to_intel_display(old_crtc_state);
enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
if (!old_crtc_state->vrr.enable)
return;
intel_de_write(dev_priv, TRANS_VRR_CTL(dev_priv, cpu_transcoder),
intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder),
trans_vrr_ctl(old_crtc_state));
intel_de_wait_for_clear(dev_priv,
TRANS_VRR_STATUS(dev_priv, cpu_transcoder),
intel_de_wait_for_clear(display,
TRANS_VRR_STATUS(display, cpu_transcoder),
VRR_STATUS_VRR_EN_LIVE, 1000);
intel_de_write(dev_priv, TRANS_PUSH(dev_priv, cpu_transcoder), 0);
intel_de_write(display, TRANS_PUSH(display, cpu_transcoder), 0);
if (HAS_AS_SDP(dev_priv))
intel_de_write(dev_priv,
TRANS_VRR_VSYNC(dev_priv, cpu_transcoder), 0);
if (HAS_AS_SDP(display))
intel_de_write(display,
TRANS_VRR_VSYNC(display, cpu_transcoder), 0);
}
void intel_vrr_get_config(struct intel_crtc_state *crtc_state)
{
struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
struct intel_display *display = to_intel_display(crtc_state);
enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
u32 trans_vrr_ctl, trans_vrr_vsync;
trans_vrr_ctl = intel_de_read(dev_priv,
TRANS_VRR_CTL(dev_priv, cpu_transcoder));
trans_vrr_ctl = intel_de_read(display,
TRANS_VRR_CTL(display, cpu_transcoder));
crtc_state->vrr.enable = trans_vrr_ctl & VRR_CTL_VRR_ENABLE;
if (HAS_CMRR(dev_priv))
if (HAS_CMRR(display))
crtc_state->cmrr.enable = (trans_vrr_ctl & VRR_CTL_CMRR_ENABLE);
if (crtc_state->cmrr.enable) {
crtc_state->cmrr.cmrr_n =
intel_de_read64_2x32(dev_priv, TRANS_CMRR_N_LO(dev_priv, cpu_transcoder),
TRANS_CMRR_N_HI(dev_priv, cpu_transcoder));
intel_de_read64_2x32(display, TRANS_CMRR_N_LO(display, cpu_transcoder),
TRANS_CMRR_N_HI(display, cpu_transcoder));
crtc_state->cmrr.cmrr_m =
intel_de_read64_2x32(dev_priv, TRANS_CMRR_M_LO(dev_priv, cpu_transcoder),
TRANS_CMRR_M_HI(dev_priv, cpu_transcoder));
intel_de_read64_2x32(display, TRANS_CMRR_M_LO(display, cpu_transcoder),
TRANS_CMRR_M_HI(display, cpu_transcoder));
}
if (DISPLAY_VER(dev_priv) >= 13)
if (DISPLAY_VER(display) >= 13)
crtc_state->vrr.guardband =
REG_FIELD_GET(XELPD_VRR_CTL_VRR_GUARDBAND_MASK, trans_vrr_ctl);
else
@ -414,21 +409,21 @@ void intel_vrr_get_config(struct intel_crtc_state *crtc_state)
REG_FIELD_GET(VRR_CTL_PIPELINE_FULL_MASK, trans_vrr_ctl);
if (trans_vrr_ctl & VRR_CTL_FLIP_LINE_EN) {
crtc_state->vrr.flipline = intel_de_read(dev_priv,
TRANS_VRR_FLIPLINE(dev_priv, cpu_transcoder)) + 1;
crtc_state->vrr.vmax = intel_de_read(dev_priv,
TRANS_VRR_VMAX(dev_priv, cpu_transcoder)) + 1;
crtc_state->vrr.vmin = intel_de_read(dev_priv,
TRANS_VRR_VMIN(dev_priv, cpu_transcoder)) + 1;
crtc_state->vrr.flipline = intel_de_read(display,
TRANS_VRR_FLIPLINE(display, cpu_transcoder)) + 1;
crtc_state->vrr.vmax = intel_de_read(display,
TRANS_VRR_VMAX(display, cpu_transcoder)) + 1;
crtc_state->vrr.vmin = intel_de_read(display,
TRANS_VRR_VMIN(display, cpu_transcoder)) + 1;
}
if (crtc_state->vrr.enable) {
crtc_state->mode_flags |= I915_MODE_FLAG_VRR;
if (HAS_AS_SDP(dev_priv)) {
if (HAS_AS_SDP(display)) {
trans_vrr_vsync =
intel_de_read(dev_priv,
TRANS_VRR_VSYNC(dev_priv, cpu_transcoder));
intel_de_read(display,
TRANS_VRR_VSYNC(display, cpu_transcoder));
crtc_state->vrr.vsync_start =
REG_FIELD_GET(VRR_VSYNC_START_MASK, trans_vrr_vsync);
crtc_state->vrr.vsync_end =

10
drivers/gpu/drm/i915/display/skl_universal_plane.c
View File

@ -538,6 +538,8 @@ static u32 tgl_plane_min_alignment(struct intel_plane *plane,
case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS:
case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC:
case I915_FORMAT_MOD_4_TILED_DG2_MC_CCS:
case I915_FORMAT_MOD_4_TILED_BMG_CCS:
case I915_FORMAT_MOD_4_TILED_LNL_CCS:
/*
* Align to at least 4x1 main surface
* tiles (16K) to match 64B of AUX.
@ -949,6 +951,9 @@ static u32 skl_plane_ctl_tiling(u64 fb_modifier)
return PLANE_CTL_TILED_4 | PLANE_CTL_RENDER_DECOMPRESSION_ENABLE;
case I915_FORMAT_MOD_4_TILED_MTL_MC_CCS:
return PLANE_CTL_TILED_4 | PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE;
case I915_FORMAT_MOD_4_TILED_BMG_CCS:
case I915_FORMAT_MOD_4_TILED_LNL_CCS:
return PLANE_CTL_TILED_4 | PLANE_CTL_RENDER_DECOMPRESSION_ENABLE;
case I915_FORMAT_MOD_Y_TILED_CCS:
case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
return PLANE_CTL_TILED_Y | PLANE_CTL_RENDER_DECOMPRESSION_ENABLE;
@ -1086,11 +1091,6 @@ static u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state,
if (DISPLAY_VER(dev_priv) == 13)
plane_ctl |= adlp_plane_ctl_arb_slots(plane_state);
if (GRAPHICS_VER(dev_priv) >= 20 &&
fb->modifier == I915_FORMAT_MOD_4_TILED) {
plane_ctl |= PLANE_CTL_RENDER_DECOMPRESSION_ENABLE;
}
return plane_ctl;
}

1
drivers/gpu/drm/i915/display/vlv_dsi.c
View File

@ -1870,7 +1870,6 @@ static const struct dmi_system_id vlv_dsi_dmi_quirk_table[] = {
/* Lenovo Yoga Tab 3 Pro YT3-X90F */
.matches = {
DMI_MATCH(DMI_SYS_VENDOR, "Intel Corporation"),
DMI_MATCH(DMI_PRODUCT_NAME, "CHERRYVIEW D1 PLATFORM"),
DMI_MATCH(DMI_PRODUCT_VERSION, "Blade3-10A-001"),
},
.driver_data = (void *)vlv_dsi_lenovo_yoga_tab3_backlight_fixup,

2
drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
View File

@ -12,8 +12,6 @@
#include <drm/drm_auth.h>
#include <drm/drm_syncobj.h>
#include "display/intel_frontbuffer.h"
#include "gem/i915_gem_ioctls.h"
#include "gt/intel_context.h"
#include "gt/intel_gpu_commands.h"

1
drivers/gpu/drm/i915/gt/intel_ggtt.c
View File

@ -12,7 +12,6 @@
#include <drm/intel/i915_drm.h>
#include <drm/intel/intel-gtt.h>
#include "display/intel_display.h"
#include "gem/i915_gem_lmem.h"
#include "intel_context.h"

31
drivers/gpu/drm/i915/gt/uc/intel_gsc_fw.c
View File

@ -212,6 +212,37 @@ int intel_gsc_fw_get_binary_info(struct intel_uc_fw *gsc_fw, const void *data, s
}
}
if (IS_ARROWLAKE(gt->i915)) {
bool too_old = false;
/*
* ARL requires a newer firmware than MTL did (102.0.10.1878) but the
* firmware is actually common. So, need to do an explicit version check
* here rather than using a separate table entry. And if the older
* MTL-only version is found, then just don't use GSC rather than aborting
* the driver load.
*/
if (gsc->release.major < 102) {
too_old = true;
} else if (gsc->release.major == 102) {
if (gsc->release.minor == 0) {
if (gsc->release.patch < 10) {
too_old = true;
} else if (gsc->release.patch == 10) {
if (gsc->release.build < 1878)
too_old = true;
}
}
}
if (too_old) {
gt_info(gt, "GSC firmware too old for ARL, got %d.%d.%d.%d but need at least 102.0.10.1878",
gsc->release.major, gsc->release.minor,
gsc->release.patch, gsc->release.build);
return -EINVAL;
}
}
return 0;
}

10
drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
View File

@ -698,12 +698,18 @@ static int check_gsc_manifest(struct intel_gt *gt,
const struct firmware *fw,
struct intel_uc_fw *uc_fw)
{
int ret;
switch (uc_fw->type) {
case INTEL_UC_FW_TYPE_HUC:
intel_huc_fw_get_binary_info(uc_fw, fw->data, fw->size);
ret = intel_huc_fw_get_binary_info(uc_fw, fw->data, fw->size);
if (ret)
return ret;
break;
case INTEL_UC_FW_TYPE_GSC:
intel_gsc_fw_get_binary_info(uc_fw, fw->data, fw->size);
ret = intel_gsc_fw_get_binary_info(uc_fw, fw->data, fw->size);
if (ret)
return ret;
break;
default:
MISSING_CASE(uc_fw->type);

3
drivers/gpu/drm/i915/i915_debugfs.c
View File

@ -66,6 +66,7 @@ static inline struct drm_i915_private *node_to_i915(struct drm_info_node *node)
static int i915_capabilities(struct seq_file *m, void *data)
{
struct drm_i915_private *i915 = node_to_i915(m->private);
struct intel_display *display = &i915->display;
struct drm_printer p = drm_seq_file_printer(m);
seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(i915));
@ -77,7 +78,7 @@ static int i915_capabilities(struct seq_file *m, void *data)
kernel_param_lock(THIS_MODULE);
i915_params_dump(&i915->params, &p);
intel_display_params_dump(i915, &p);
intel_display_params_dump(display, &p);
kernel_param_unlock(THIS_MODULE);
return 0;

4
drivers/gpu/drm/i915/i915_driver.c
View File

@ -49,7 +49,7 @@
#include "display/intel_bw.h"
#include "display/intel_cdclk.h"
#include "display/intel_display_driver.h"
#include "display/intel_display_types.h"
#include "display/intel_display.h"
#include "display/intel_dmc.h"
#include "display/intel_dp.h"
#include "display/intel_dpt.h"
@ -58,10 +58,8 @@
#include "display/intel_hotplug.h"
#include "display/intel_overlay.h"
#include "display/intel_pch_refclk.h"
#include "display/intel_pipe_crc.h"
#include "display/intel_pps.h"
#include "display/intel_sprite.h"
#include "display/intel_vga.h"
#include "display/skl_watermark.h"
#include "gem/i915_gem_context.h"

12
drivers/gpu/drm/i915/i915_drv.h
View File

@ -408,14 +408,8 @@ static inline struct intel_gt *to_gt(const struct drm_i915_private *i915)
#define INTEL_REVID(i915) (to_pci_dev((i915)->drm.dev)->revision)
#define INTEL_DISPLAY_STEP(__i915) (RUNTIME_INFO(__i915)->step.display_step)
#define INTEL_GRAPHICS_STEP(__i915) (RUNTIME_INFO(__i915)->step.graphics_step)
#define INTEL_MEDIA_STEP(__i915) (RUNTIME_INFO(__i915)->step.media_step)
#define INTEL_BASEDIE_STEP(__i915) (RUNTIME_INFO(__i915)->step.basedie_step)
#define IS_DISPLAY_STEP(__i915, since, until) \
(drm_WARN_ON(&(__i915)->drm, INTEL_DISPLAY_STEP(__i915) == STEP_NONE), \
INTEL_DISPLAY_STEP(__i915) >= (since) && INTEL_DISPLAY_STEP(__i915) < (until))
#define IS_GRAPHICS_STEP(__i915, since, until) \
(drm_WARN_ON(&(__i915)->drm, INTEL_GRAPHICS_STEP(__i915) == STEP_NONE), \
@ -425,10 +419,6 @@ static inline struct intel_gt *to_gt(const struct drm_i915_private *i915)
(drm_WARN_ON(&(__i915)->drm, INTEL_MEDIA_STEP(__i915) == STEP_NONE), \
INTEL_MEDIA_STEP(__i915) >= (since) && INTEL_MEDIA_STEP(__i915) < (until))
#define IS_BASEDIE_STEP(__i915, since, until) \
(drm_WARN_ON(&(__i915)->drm, INTEL_BASEDIE_STEP(__i915) == STEP_NONE), \
INTEL_BASEDIE_STEP(__i915) >= (since) && INTEL_BASEDIE_STEP(__i915) < (until))
static __always_inline unsigned int
__platform_mask_index(const struct intel_runtime_info *info,
enum intel_platform p)
@ -546,6 +536,8 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
#define IS_LUNARLAKE(i915) (0 && i915)
#define IS_BATTLEMAGE(i915) (0 && i915)
#define IS_ARROWLAKE(i915) \
IS_SUBPLATFORM(i915, INTEL_METEORLAKE, INTEL_SUBPLATFORM_ARL)
#define IS_DG2_G10(i915) \
IS_SUBPLATFORM(i915, INTEL_DG2, INTEL_SUBPLATFORM_G10)
#define IS_DG2_G11(i915) \

2
drivers/gpu/drm/i915/i915_gem.c
View File

@ -39,8 +39,6 @@
#include <drm/drm_cache.h>
#include <drm/drm_vma_manager.h>
#include "display/intel_display.h"
#include "gem/i915_gem_clflush.h"
#include "gem/i915_gem_context.h"
#include "gem/i915_gem_ioctls.h"

1
drivers/gpu/drm/i915/i915_gem_gtt.c
View File

@ -15,7 +15,6 @@
#include <asm/set_memory.h>
#include <asm/smp.h>
#include "display/intel_frontbuffer.h"
#include "gt/intel_gt.h"
#include "gt/intel_gt_requests.h"

3
drivers/gpu/drm/i915/i915_gpu_error.c
View File

@ -660,9 +660,10 @@ static void err_print_params(struct drm_i915_error_state_buf *m,
const struct i915_params *params)
{
struct drm_printer p = i915_error_printer(m);
struct intel_display *display = &m->i915->display;
i915_params_dump(params, &p);
intel_display_params_dump(m->i915, &p);
intel_display_params_dump(display, &p);
}
static void err_print_pciid(struct drm_i915_error_state_buf *m,

1
drivers/gpu/drm/i915/i915_irq.c
View File

@ -34,7 +34,6 @@
#include <drm/drm_drv.h>
#include "display/intel_display_irq.h"
#include "display/intel_display_types.h"
#include "display/intel_hotplug.h"
#include "display/intel_hotplug_irq.h"
#include "display/intel_lpe_audio.h"

1
drivers/gpu/drm/i915/i915_pci.c
View File

@ -26,7 +26,6 @@
#include <drm/drm_drv.h>
#include <drm/intel/i915_pciids.h>
#include "display/intel_display.h"
#include "display/intel_display_driver.h"
#include "gt/intel_gt_regs.h"
#include "gt/intel_sa_media.h"

4
drivers/gpu/drm/i915/i915_reg.h
View File

@ -2516,6 +2516,10 @@
#define GEN11_PIPE_PLANE7_FLIP_DONE REG_BIT(18) /* icl/tgl */
#define GEN11_PIPE_PLANE6_FLIP_DONE REG_BIT(17) /* icl/tgl */
#define GEN11_PIPE_PLANE5_FLIP_DONE REG_BIT(16) /* icl+ */
#define GEN12_DSB_2_INT REG_BIT(15) /* tgl+ */
#define GEN12_DSB_1_INT REG_BIT(14) /* tgl+ */
#define GEN12_DSB_0_INT REG_BIT(13) /* tgl+ */
#define GEN12_DSB_INT(dsb_id) REG_BIT(13 + (dsb_id))
#define GEN9_PIPE_CURSOR_FAULT REG_BIT(11) /* skl+ */
#define GEN9_PIPE_PLANE4_FAULT REG_BIT(10) /* skl+ */
#define GEN8_PIPE_CURSOR_FAULT REG_BIT(10) /* bdw */

14
drivers/gpu/drm/i915/intel_device_info.c
View File

@ -108,8 +108,6 @@ void intel_device_info_print(const struct intel_device_info *info,
drm_printf(p, "graphics stepping: %s\n", intel_step_name(runtime->step.graphics_step));
drm_printf(p, "media stepping: %s\n", intel_step_name(runtime->step.media_step));
drm_printf(p, "display stepping: %s\n", intel_step_name(runtime->step.display_step));
drm_printf(p, "base die stepping: %s\n", intel_step_name(runtime->step.basedie_step));
drm_printf(p, "gt: %d\n", info->gt);
drm_printf(p, "memory-regions: 0x%x\n", info->memory_regions);
@ -124,7 +122,6 @@ void intel_device_info_print(const struct intel_device_info *info,
#undef PRINT_FLAG
drm_printf(p, "has_pooled_eu: %s\n", str_yes_no(runtime->has_pooled_eu));
drm_printf(p, "rawclk rate: %u kHz\n", runtime->rawclk_freq);
}
#define ID(id) (id)
@ -203,6 +200,10 @@ static const u16 subplatform_g12_ids[] = {
INTEL_DG2_G12_IDS(ID),
};
static const u16 subplatform_arl_ids[] = {
INTEL_ARL_IDS(ID),
};
static bool find_devid(u16 id, const u16 *p, unsigned int num)
{
for (; num; num--, p++) {
@ -260,6 +261,9 @@ static void intel_device_info_subplatform_init(struct drm_i915_private *i915)
} else if (find_devid(devid, subplatform_g12_ids,
ARRAY_SIZE(subplatform_g12_ids))) {
mask = BIT(INTEL_SUBPLATFORM_G12);
} else if (find_devid(devid, subplatform_arl_ids,
ARRAY_SIZE(subplatform_arl_ids))) {
mask = BIT(INTEL_SUBPLATFORM_ARL);
}
GEM_BUG_ON(mask & ~INTEL_SUBPLATFORM_MASK);
@ -370,10 +374,6 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
"Disabling ppGTT for VT-d support\n");
runtime->ppgtt_type = INTEL_PPGTT_NONE;
}
runtime->rawclk_freq = intel_read_rawclk(dev_priv);
drm_dbg(&dev_priv->drm, "rawclk rate: %d kHz\n", runtime->rawclk_freq);
}
/*

5
drivers/gpu/drm/i915/intel_device_info.h
View File

@ -127,6 +127,9 @@ enum intel_platform {
#define INTEL_SUBPLATFORM_N 1
#define INTEL_SUBPLATFORM_RPLU 2
/* MTL */
#define INTEL_SUBPLATFORM_ARL 0
enum intel_ppgtt_type {
INTEL_PPGTT_NONE = I915_GEM_PPGTT_NONE,
INTEL_PPGTT_ALIASING = I915_GEM_PPGTT_ALIASING,
@ -204,8 +207,6 @@ struct intel_runtime_info {
u16 device_id;
u32 rawclk_freq;
struct intel_step_info step;
unsigned int page_sizes; /* page sizes supported by the HW */

84
drivers/gpu/drm/i915/intel_step.c
View File

@ -23,8 +23,7 @@
* use a macro to define these to make it easier to identify the platforms
* where the two steppings can deviate.
*/
#define COMMON_STEP(x) .graphics_step = STEP_##x, .display_step = STEP_##x, .media_step = STEP_##x
#define COMMON_GT_MEDIA_STEP(x) .graphics_step = STEP_##x, .media_step = STEP_##x
#define COMMON_STEP(x) .graphics_step = STEP_##x, .media_step = STEP_##x
static const struct intel_step_info skl_revids[] = {
[0x6] = { COMMON_STEP(G0) },
@ -34,13 +33,13 @@ static const struct intel_step_info skl_revids[] = {
};
static const struct intel_step_info kbl_revids[] = {
[1] = { COMMON_GT_MEDIA_STEP(B0), .display_step = STEP_B0 },
[2] = { COMMON_GT_MEDIA_STEP(C0), .display_step = STEP_B0 },
[3] = { COMMON_GT_MEDIA_STEP(D0), .display_step = STEP_B0 },
[4] = { COMMON_GT_MEDIA_STEP(F0), .display_step = STEP_C0 },
[5] = { COMMON_GT_MEDIA_STEP(C0), .display_step = STEP_B1 },
[6] = { COMMON_GT_MEDIA_STEP(D1), .display_step = STEP_B1 },
[7] = { COMMON_GT_MEDIA_STEP(G0), .display_step = STEP_C0 },
[1] = { COMMON_STEP(B0) },
[2] = { COMMON_STEP(C0) },
[3] = { COMMON_STEP(D0) },
[4] = { COMMON_STEP(F0) },
[5] = { COMMON_STEP(C0) },
[6] = { COMMON_STEP(D1) },
[7] = { COMMON_STEP(G0) },
};
static const struct intel_step_info bxt_revids[] = {
@ -64,16 +63,16 @@ static const struct intel_step_info jsl_ehl_revids[] = {
};
static const struct intel_step_info tgl_uy_revids[] = {
[0] = { COMMON_GT_MEDIA_STEP(A0), .display_step = STEP_A0 },
[1] = { COMMON_GT_MEDIA_STEP(B0), .display_step = STEP_C0 },
[2] = { COMMON_GT_MEDIA_STEP(B1), .display_step = STEP_C0 },
[3] = { COMMON_GT_MEDIA_STEP(C0), .display_step = STEP_D0 },
[0] = { COMMON_STEP(A0) },
[1] = { COMMON_STEP(B0) },
[2] = { COMMON_STEP(B1) },
[3] = { COMMON_STEP(C0) },
};
/* Same GT stepping between tgl_uy_revids and tgl_revids don't mean the same HW */
static const struct intel_step_info tgl_revids[] = {
[0] = { COMMON_GT_MEDIA_STEP(A0), .display_step = STEP_B0 },
[1] = { COMMON_GT_MEDIA_STEP(B0), .display_step = STEP_D0 },
[0] = { COMMON_STEP(A0) },
[1] = { COMMON_STEP(B0) },
};
static const struct intel_step_info rkl_revids[] = {
@ -88,49 +87,49 @@ static const struct intel_step_info dg1_revids[] = {
};
static const struct intel_step_info adls_revids[] = {
[0x0] = { COMMON_GT_MEDIA_STEP(A0), .display_step = STEP_A0 },
[0x1] = { COMMON_GT_MEDIA_STEP(A0), .display_step = STEP_A2 },
[0x4] = { COMMON_GT_MEDIA_STEP(B0), .display_step = STEP_B0 },
[0x8] = { COMMON_GT_MEDIA_STEP(C0), .display_step = STEP_B0 },
[0xC] = { COMMON_GT_MEDIA_STEP(D0), .display_step = STEP_C0 },
[0x0] = { COMMON_STEP(A0) },
[0x1] = { COMMON_STEP(A0) },
[0x4] = { COMMON_STEP(B0) },
[0x8] = { COMMON_STEP(C0) },
[0xC] = { COMMON_STEP(D0) },
};
static const struct intel_step_info adlp_revids[] = {
[0x0] = { COMMON_GT_MEDIA_STEP(A0), .display_step = STEP_A0 },
[0x4] = { COMMON_GT_MEDIA_STEP(B0), .display_step = STEP_B0 },
[0x8] = { COMMON_GT_MEDIA_STEP(C0), .display_step = STEP_C0 },
[0xC] = { COMMON_GT_MEDIA_STEP(C0), .display_step = STEP_D0 },
[0x0] = { COMMON_STEP(A0) },
[0x4] = { COMMON_STEP(B0) },
[0x8] = { COMMON_STEP(C0) },
[0xC] = { COMMON_STEP(C0) },
};
static const struct intel_step_info dg2_g10_revid_step_tbl[] = {
[0x0] = { COMMON_GT_MEDIA_STEP(A0), .display_step = STEP_A0 },
[0x1] = { COMMON_GT_MEDIA_STEP(A1), .display_step = STEP_A0 },
[0x4] = { COMMON_GT_MEDIA_STEP(B0), .display_step = STEP_B0 },
[0x8] = { COMMON_GT_MEDIA_STEP(C0), .display_step = STEP_C0 },
[0x0] = { COMMON_STEP(A0) },
[0x1] = { COMMON_STEP(A1) },
[0x4] = { COMMON_STEP(B0) },
[0x8] = { COMMON_STEP(C0) },
};
static const struct intel_step_info dg2_g11_revid_step_tbl[] = {
[0x0] = { COMMON_GT_MEDIA_STEP(A0), .display_step = STEP_B0 },
[0x4] = { COMMON_GT_MEDIA_STEP(B0), .display_step = STEP_C0 },
[0x5] = { COMMON_GT_MEDIA_STEP(B1), .display_step = STEP_C0 },
[0x0] = { COMMON_STEP(A0) },
[0x4] = { COMMON_STEP(B0) },
[0x5] = { COMMON_STEP(B1) },
};
static const struct intel_step_info dg2_g12_revid_step_tbl[] = {
[0x0] = { COMMON_GT_MEDIA_STEP(A0), .display_step = STEP_C0 },
[0x1] = { COMMON_GT_MEDIA_STEP(A1), .display_step = STEP_C0 },
[0x0] = { COMMON_STEP(A0) },
[0x1] = { COMMON_STEP(A1) },
};
static const struct intel_step_info adls_rpls_revids[] = {
[0x4] = { COMMON_GT_MEDIA_STEP(D0), .display_step = STEP_D0 },
[0xC] = { COMMON_GT_MEDIA_STEP(D0), .display_step = STEP_C0 },
[0x4] = { COMMON_STEP(D0) },
[0xC] = { COMMON_STEP(D0) },
};
static const struct intel_step_info adlp_rplp_revids[] = {
[0x4] = { COMMON_GT_MEDIA_STEP(C0), .display_step = STEP_E0 },
[0x4] = { COMMON_STEP(C0) },
};
static const struct intel_step_info adlp_n_revids[] = {
[0x0] = { COMMON_GT_MEDIA_STEP(A0), .display_step = STEP_D0 },
[0x0] = { COMMON_STEP(A0) },
};
static u8 gmd_to_intel_step(struct drm_i915_private *i915,
@ -158,11 +157,6 @@ void intel_step_init(struct drm_i915_private *i915)
&RUNTIME_INFO(i915)->graphics.ip);
step.media_step = gmd_to_intel_step(i915,
&RUNTIME_INFO(i915)->media.ip);
step.display_step = STEP_A0 + DISPLAY_RUNTIME_INFO(i915)->ip.step;
if (step.display_step >= STEP_FUTURE) {
drm_dbg(&i915->drm, "Using future display steppings\n");
step.display_step = STEP_FUTURE;
}
RUNTIME_INFO(i915)->step = step;
@ -252,7 +246,6 @@ void intel_step_init(struct drm_i915_private *i915)
} else {
drm_dbg(&i915->drm, "Using future steppings\n");
step.graphics_step = STEP_FUTURE;
step.display_step = STEP_FUTURE;
}
}
@ -275,8 +268,3 @@ const char *intel_step_name(enum intel_step step)
return "**";
}
}
const char *intel_display_step_name(struct drm_i915_private *i915)
{
return intel_step_name(RUNTIME_INFO(i915)->step.display_step);
}

3
drivers/gpu/drm/i915/intel_step.h
View File

@ -16,9 +16,7 @@ struct intel_step_info {
* the expectation breaks gmd_to_intel_step().
*/
u8 graphics_step; /* Represents the compute tile on Xe_HPC */
u8 display_step;
u8 media_step;
u8 basedie_step;
};
#define STEP_ENUM_VAL(name) STEP_##name,
@ -78,6 +76,5 @@ enum intel_step {
void intel_step_init(struct drm_i915_private *i915);
const char *intel_step_name(enum intel_step step);
const char *intel_display_step_name(struct drm_i915_private *i915);
#endif /* __INTEL_STEP_H__ */

6
drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h
View File

@ -80,11 +80,6 @@ static inline struct drm_i915_private *kdev_to_i915(struct device *kdev)
#define IS_MOBILE(xe) (xe && 0)
#define HAS_GMD_ID(xe) GRAPHICS_VERx100(xe) >= 1270
/* Workarounds not handled yet */
#define IS_DISPLAY_STEP(xe, first, last) ({u8 __step = (xe)->info.step.display; first <= __step && __step <= last; })
#define IS_LP(xe) (0)
#define IS_GEN9_LP(xe) (0)
#define IS_GEN9_BC(xe) (0)
@ -116,7 +111,6 @@ struct i915_sched_attr {
#define i915_gem_fence_wait_priority(fence, attr) do { (void) attr; } while (0)
#define pdev_to_i915 pdev_to_xe_device
#define RUNTIME_INFO(xe) (&(xe)->info.i915_runtime)
#define FORCEWAKE_ALL XE_FORCEWAKE_ALL

10
drivers/gpu/drm/xe/compat-i915-headers/intel_step.h
View File

@ -6,15 +6,9 @@
#ifndef __INTEL_STEP_H__
#define __INTEL_STEP_H__
#include "xe_device_types.h"
#include "xe_step.h"
#define intel_display_step_name xe_display_step_name
static inline
const char *xe_display_step_name(struct xe_device *xe)
{
return xe_step_name(xe->info.step.display);
}
#define intel_step xe_step
#define intel_step_name xe_step_name
#endif /* __INTEL_STEP_H__ */

9
drivers/gpu/drm/xe/display/intel_fb_bo.c
View File

@ -7,6 +7,7 @@
#include <drm/ttm/ttm_bo.h>
#include "intel_display_types.h"
#include "intel_fb.h"
#include "intel_fb_bo.h"
#include "xe_bo.h"
@ -28,6 +29,14 @@ int intel_fb_bo_framebuffer_init(struct intel_framebuffer *intel_fb,
struct xe_device *xe = to_xe_device(bo->ttm.base.dev);
int ret;
/*
* Some modifiers require physical alignment of 64KiB VRAM pages;
* require that the BO in those cases is created correctly.
*/
if (XE_IOCTL_DBG(xe, intel_fb_needs_64k_phys(mode_cmd->modifier[0]) &&
!(bo->flags & XE_BO_FLAG_NEEDS_64K)))
return -EINVAL;
xe_bo_get(bo);
ret = ttm_bo_reserve(&bo->ttm, true, false, NULL);

7
drivers/gpu/drm/xe/xe_bo.c
View File

@ -1997,6 +1997,13 @@ int xe_gem_create_ioctl(struct drm_device *dev, void *data,
bo_flags |= args->placement << (ffs(XE_BO_FLAG_SYSTEM) - 1);
/* CCS formats need physical placement at a 64K alignment in VRAM. */
if ((bo_flags & XE_BO_FLAG_VRAM_MASK) &&
(bo_flags & XE_BO_FLAG_SCANOUT) &&
!(xe->info.vram_flags & XE_VRAM_FLAGS_NEED64K) &&
IS_ALIGNED(args->size, SZ_64K))
bo_flags |= XE_BO_FLAG_NEEDS_64K;
if (args->flags & DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM) {
if (XE_IOCTL_DBG(xe, !(bo_flags & XE_BO_FLAG_VRAM_MASK)))
return -EINVAL;

3
drivers/gpu/drm/xe/xe_debugfs.c
View File

@ -47,10 +47,9 @@ static int info(struct seq_file *m, void *data)
drm_printf(&p, "graphics_verx100 %d\n", xe->info.graphics_verx100);
drm_printf(&p, "media_verx100 %d\n", xe->info.media_verx100);
drm_printf(&p, "stepping G:%s M:%s D:%s B:%s\n",
drm_printf(&p, "stepping G:%s M:%s B:%s\n",
xe_step_name(xe->info.step.graphics),
xe_step_name(xe->info.step.media),
xe_step_name(xe->info.step.display),
xe_step_name(xe->info.step.basedie));
drm_printf(&p, "is_dgfx %s\n", str_yes_no(xe->info.is_dgfx));
drm_printf(&p, "platform %d\n", xe->info.platform);

6
drivers/gpu/drm/xe/xe_device_types.h
View File

@ -305,12 +305,6 @@ struct xe_device {
u8 has_atomic_enable_pte_bit:1;
/** @info.has_device_atomics_on_smem: Supports device atomics on SMEM */
u8 has_device_atomics_on_smem:1;
#if IS_ENABLED(CONFIG_DRM_XE_DISPLAY)
struct {
u32 rawclk_freq;
} i915_runtime;
#endif
} info;
/** @irq: device interrupt state */

3
drivers/gpu/drm/xe/xe_pci.c
View File

@ -831,10 +831,9 @@ static int xe_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
xe->info.dma_mask_size, xe->info.tile_count,
xe->info.has_heci_gscfi, xe->info.has_heci_cscfi);
drm_dbg(&xe->drm, "Stepping = (G:%s, M:%s, D:%s, B:%s)\n",
drm_dbg(&xe->drm, "Stepping = (G:%s, M:%s, B:%s)\n",
xe_step_name(xe->info.step.graphics),
xe_step_name(xe->info.step.media),
xe_step_name(xe->info.step.display),
xe_step_name(xe->info.step.basedie));
drm_dbg(&xe->drm, "SR-IOV support: %s (mode: %s)\n",

57
drivers/gpu/drm/xe/xe_step.c
View File

@ -28,23 +28,17 @@
* use a macro to define these to make it easier to identify the platforms
* where the two steppings can deviate.
*/
#define COMMON_GT_MEDIA_STEP(x_) \
#define COMMON_STEP(x_) \
.graphics = STEP_##x_, \
.media = STEP_##x_
#define COMMON_STEP(x_) \
COMMON_GT_MEDIA_STEP(x_), \
.graphics = STEP_##x_, \
.media = STEP_##x_, \
.display = STEP_##x_
__diag_push();
__diag_ignore_all("-Woverride-init", "Allow field overrides in table");
/* Same GT stepping between tgl_uy_revids and tgl_revids don't mean the same HW */
static const struct xe_step_info tgl_revids[] = {
[0] = { COMMON_GT_MEDIA_STEP(A0), .display = STEP_B0 },
[1] = { COMMON_GT_MEDIA_STEP(B0), .display = STEP_D0 },
[0] = { COMMON_STEP(A0) },
[1] = { COMMON_STEP(B0) },
};
static const struct xe_step_info dg1_revids[] = {
@ -53,49 +47,49 @@ static const struct xe_step_info dg1_revids[] = {
};
static const struct xe_step_info adls_revids[] = {
[0x0] = { COMMON_GT_MEDIA_STEP(A0), .display = STEP_A0 },
[0x1] = { COMMON_GT_MEDIA_STEP(A0), .display = STEP_A2 },
[0x4] = { COMMON_GT_MEDIA_STEP(B0), .display = STEP_B0 },
[0x8] = { COMMON_GT_MEDIA_STEP(C0), .display = STEP_B0 },
[0xC] = { COMMON_GT_MEDIA_STEP(D0), .display = STEP_C0 },
[0x0] = { COMMON_STEP(A0) },
[0x1] = { COMMON_STEP(A0) },
[0x4] = { COMMON_STEP(B0) },
[0x8] = { COMMON_STEP(C0) },
[0xC] = { COMMON_STEP(D0) },
};
static const struct xe_step_info adls_rpls_revids[] = {
[0x4] = { COMMON_GT_MEDIA_STEP(D0), .display = STEP_D0 },
[0xC] = { COMMON_GT_MEDIA_STEP(D0), .display = STEP_C0 },
[0x4] = { COMMON_STEP(D0) },
[0xC] = { COMMON_STEP(D0) },
};
static const struct xe_step_info adlp_revids[] = {
[0x0] = { COMMON_GT_MEDIA_STEP(A0), .display = STEP_A0 },
[0x4] = { COMMON_GT_MEDIA_STEP(B0), .display = STEP_B0 },
[0x8] = { COMMON_GT_MEDIA_STEP(C0), .display = STEP_C0 },
[0xC] = { COMMON_GT_MEDIA_STEP(C0), .display = STEP_D0 },
[0x0] = { COMMON_STEP(A0) },
[0x4] = { COMMON_STEP(B0) },
[0x8] = { COMMON_STEP(C0) },
[0xC] = { COMMON_STEP(C0) },
};
static const struct xe_step_info adlp_rpl_revids[] = {
[0x4] = { COMMON_GT_MEDIA_STEP(C0), .display = STEP_E0 },
[0x4] = { COMMON_STEP(C0) },
};
static const struct xe_step_info adln_revids[] = {
[0x0] = { COMMON_GT_MEDIA_STEP(A0), .display = STEP_D0 },
[0x0] = { COMMON_STEP(A0) },
};
static const struct xe_step_info dg2_g10_revid_step_tbl[] = {
[0x0] = { COMMON_GT_MEDIA_STEP(A0), .display = STEP_A0 },
[0x1] = { COMMON_GT_MEDIA_STEP(A1), .display = STEP_A0 },
[0x4] = { COMMON_GT_MEDIA_STEP(B0), .display = STEP_B0 },
[0x8] = { COMMON_GT_MEDIA_STEP(C0), .display = STEP_C0 },
[0x0] = { COMMON_STEP(A0) },
[0x1] = { COMMON_STEP(A1) },
[0x4] = { COMMON_STEP(B0) },
[0x8] = { COMMON_STEP(C0) },
};
static const struct xe_step_info dg2_g11_revid_step_tbl[] = {
[0x0] = { COMMON_GT_MEDIA_STEP(A0), .display = STEP_B0 },
[0x4] = { COMMON_GT_MEDIA_STEP(B0), .display = STEP_C0 },
[0x5] = { COMMON_GT_MEDIA_STEP(B1), .display = STEP_C0 },
[0x0] = { COMMON_STEP(A0) },
[0x4] = { COMMON_STEP(B0) },
[0x5] = { COMMON_STEP(B1) },
};
static const struct xe_step_info dg2_g12_revid_step_tbl[] = {
[0x0] = { COMMON_GT_MEDIA_STEP(A0), .display = STEP_C0 },
[0x1] = { COMMON_GT_MEDIA_STEP(A1), .display = STEP_C0 },
[0x0] = { COMMON_STEP(A0) },
[0x1] = { COMMON_STEP(A1) },
};
static const struct xe_step_info pvc_revid_step_tbl[] = {
@ -195,7 +189,6 @@ struct xe_step_info xe_step_pre_gmdid_get(struct xe_device *xe)
} else {
drm_dbg(&xe->drm, "Using future steppings\n");
step.graphics = STEP_FUTURE;
step.display = STEP_FUTURE;
}
}

30
drivers/gpu/drm/xe/xe_step_types.h
View File

@ -11,12 +11,15 @@
struct xe_step_info {
u8 graphics;
u8 media;
u8 display;
u8 basedie;
};
#define STEP_ENUM_VAL(name) STEP_##name,
/*
* Always define four minor steppings 0-3 for each stepping to match GMD ID
* spacing of values. See xe_step_gmdid_get().
*/
#define STEP_NAME_LIST(func) \
func(A0) \
func(A1) \
@ -34,7 +37,30 @@ struct xe_step_info {
func(D1) \
func(D2) \
func(D3) \
func(E0)
func(E0) \
func(E1) \
func(E2) \
func(E3) \
func(F0) \
func(F1) \
func(F2) \
func(F3) \
func(G0) \
func(G1) \
func(G2) \
func(G3) \
func(H0) \
func(H1) \
func(H2) \
func(H3) \
func(I0) \
func(I1) \
func(I2) \
func(I3) \
func(J0) \
func(J1) \
func(J2) \
func(J3)
/*
* Symbolic steppings that do not match the hardware. These are valid both as gt

11
drivers/gpu/drm/xe/xe_vm.c
View File

@ -2878,7 +2878,16 @@ static int xe_vm_bind_ioctl_validate_bo(struct xe_device *xe, struct xe_bo *bo,
return -EINVAL;
}
if (bo->flags & XE_BO_FLAG_INTERNAL_64K) {
/*
* Some platforms require 64k VM_BIND alignment,
* specifically those with XE_VRAM_FLAGS_NEED64K.
*
* Other platforms may have BO's set to 64k physical placement,
* but can be mapped at 4k offsets anyway. This check is only
* there for the former case.
*/
if ((bo->flags & XE_BO_FLAG_INTERNAL_64K) &&
(xe->info.vram_flags & XE_VRAM_FLAGS_NEED64K)) {
if (XE_IOCTL_DBG(xe, obj_offset &
XE_64K_PAGE_MASK) ||
XE_IOCTL_DBG(xe, addr & XE_64K_PAGE_MASK) ||

13
include/drm/intel/i915_pciids.h
View File

@ -772,15 +772,18 @@
INTEL_ATS_M75_IDS(MACRO__, ## __VA_ARGS__)
/* MTL */
#define INTEL_MTL_IDS(MACRO__, ...) \
MACRO__(0x7D40, ## __VA_ARGS__), \
#define INTEL_ARL_IDS(MACRO__, ...) \
MACRO__(0x7D41, ## __VA_ARGS__), \
MACRO__(0x7D45, ## __VA_ARGS__), \
MACRO__(0x7D51, ## __VA_ARGS__), \
MACRO__(0x7D67, ## __VA_ARGS__), \
MACRO__(0x7DD1, ## __VA_ARGS__)
#define INTEL_MTL_IDS(MACRO__, ...) \
INTEL_ARL_IDS(MACRO__, ## __VA_ARGS__), \
MACRO__(0x7D40, ## __VA_ARGS__), \
MACRO__(0x7D45, ## __VA_ARGS__), \
MACRO__(0x7D55, ## __VA_ARGS__), \
MACRO__(0x7D60, ## __VA_ARGS__), \
MACRO__(0x7D67, ## __VA_ARGS__), \
MACRO__(0x7DD1, ## __VA_ARGS__), \
MACRO__(0x7DD5, ## __VA_ARGS__)
/* LNL */

25
include/uapi/drm/drm_fourcc.h
View File

@ -702,6 +702,31 @@ extern "C" {
*/
#define I915_FORMAT_MOD_4_TILED_MTL_RC_CCS_CC fourcc_mod_code(INTEL, 15)
/*
* Intel Color Control Surfaces (CCS) for graphics ver. 20 unified compression
* on integrated graphics
*
* The main surface is Tile 4 and at plane index 0. For semi-planar formats
* like NV12, the Y and UV planes are Tile 4 and are located at plane indices
* 0 and 1, respectively. The CCS for all planes are stored outside of the
* GEM object in a reserved memory area dedicated for the storage of the
* CCS data for all compressible GEM objects.
*/
#define I915_FORMAT_MOD_4_TILED_LNL_CCS fourcc_mod_code(INTEL, 16)
/*
* Intel Color Control Surfaces (CCS) for graphics ver. 20 unified compression
* on discrete graphics
*
* The main surface is Tile 4 and at plane index 0. For semi-planar formats
* like NV12, the Y and UV planes are Tile 4 and are located at plane indices
* 0 and 1, respectively. The CCS for all planes are stored outside of the
* GEM object in a reserved memory area dedicated for the storage of the
* CCS data for all compressible GEM objects. The GEM object must be stored in
* contiguous memory with a size aligned to 64KB
*/
#define I915_FORMAT_MOD_4_TILED_BMG_CCS fourcc_mod_code(INTEL, 17)
/*
* Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks
*