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pinctrl: actions: Add interrupt support for OWL S900 SoC
Add interrupt support for Actions Semi OWL S900 SoC. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This commit is contained in:
Manivannan Sadhasivam
Linus Walleij
parent
e3bc2ebd92
commit
6c5d0736e9
@ -5,6 +5,7 @@ config PINCTRL_OWL
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select PINCONF
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select GENERIC_PINCONF
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select GPIOLIB
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select GPIOLIB_IRQCHIP
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help
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Say Y here to enable Actions Semi OWL pinctrl driver
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@ -13,6 +13,7 @@
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#include <linux/err.h>
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#include <linux/gpio/driver.h>
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#include <linux/io.h>
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#include <linux/irq.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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@ -45,6 +46,9 @@ struct owl_pinctrl {
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struct clk *clk;
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const struct owl_pinctrl_soc_data *soc;
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void __iomem *base;
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struct irq_chip irq_chip;
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unsigned int num_irq;
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unsigned int *irq;
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};
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static void owl_update_bits(void __iomem *base, u32 mask, u32 val)
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@ -701,10 +705,213 @@ static int owl_gpio_direction_output(struct gpio_chip *chip,
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return 0;
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}
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static void irq_set_type(struct owl_pinctrl *pctrl, int gpio, unsigned int type)
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{
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const struct owl_gpio_port *port;
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void __iomem *gpio_base;
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unsigned long flags;
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unsigned int offset, value, irq_type = 0;
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switch (type) {
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case IRQ_TYPE_EDGE_BOTH:
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/*
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* Since the hardware doesn't support interrupts on both edges,
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* emulate it in the software by setting the single edge
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* interrupt and switching to the opposite edge while ACKing
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* the interrupt
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*/
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if (owl_gpio_get(&pctrl->chip, gpio))
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irq_type = OWL_GPIO_INT_EDGE_FALLING;
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else
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irq_type = OWL_GPIO_INT_EDGE_RISING;
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break;
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case IRQ_TYPE_EDGE_RISING:
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irq_type = OWL_GPIO_INT_EDGE_RISING;
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break;
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case IRQ_TYPE_EDGE_FALLING:
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irq_type = OWL_GPIO_INT_EDGE_FALLING;
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break;
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case IRQ_TYPE_LEVEL_HIGH:
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irq_type = OWL_GPIO_INT_LEVEL_HIGH;
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break;
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case IRQ_TYPE_LEVEL_LOW:
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irq_type = OWL_GPIO_INT_LEVEL_LOW;
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break;
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default:
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break;
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}
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port = owl_gpio_get_port(pctrl, &gpio);
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if (WARN_ON(port == NULL))
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return;
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gpio_base = pctrl->base + port->offset;
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raw_spin_lock_irqsave(&pctrl->lock, flags);
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offset = (gpio < 16) ? 4 : 0;
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value = readl_relaxed(gpio_base + port->intc_type + offset);
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value &= ~(OWL_GPIO_INT_MASK << ((gpio % 16) * 2));
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value |= irq_type << ((gpio % 16) * 2);
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writel_relaxed(value, gpio_base + port->intc_type + offset);
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raw_spin_unlock_irqrestore(&pctrl->lock, flags);
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}
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static void owl_gpio_irq_mask(struct irq_data *data)
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{
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struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
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struct owl_pinctrl *pctrl = gpiochip_get_data(gc);
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const struct owl_gpio_port *port;
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void __iomem *gpio_base;
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unsigned long flags;
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unsigned int gpio = data->hwirq;
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u32 val;
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port = owl_gpio_get_port(pctrl, &gpio);
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if (WARN_ON(port == NULL))
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return;
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gpio_base = pctrl->base + port->offset;
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raw_spin_lock_irqsave(&pctrl->lock, flags);
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owl_gpio_update_reg(gpio_base + port->intc_msk, gpio, false);
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/* disable port interrupt if no interrupt pending bit is active */
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val = readl_relaxed(gpio_base + port->intc_msk);
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if (val == 0)
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owl_gpio_update_reg(gpio_base + port->intc_ctl,
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OWL_GPIO_CTLR_ENABLE, false);
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raw_spin_unlock_irqrestore(&pctrl->lock, flags);
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}
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static void owl_gpio_irq_unmask(struct irq_data *data)
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{
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struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
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struct owl_pinctrl *pctrl = gpiochip_get_data(gc);
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const struct owl_gpio_port *port;
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void __iomem *gpio_base;
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unsigned long flags;
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unsigned int gpio = data->hwirq;
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u32 value;
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port = owl_gpio_get_port(pctrl, &gpio);
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if (WARN_ON(port == NULL))
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return;
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gpio_base = pctrl->base + port->offset;
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raw_spin_lock_irqsave(&pctrl->lock, flags);
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/* enable port interrupt */
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value = readl_relaxed(gpio_base + port->intc_ctl);
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value |= BIT(OWL_GPIO_CTLR_ENABLE) | BIT(OWL_GPIO_CTLR_SAMPLE_CLK_24M);
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writel_relaxed(value, gpio_base + port->intc_ctl);
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/* enable GPIO interrupt */
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owl_gpio_update_reg(gpio_base + port->intc_msk, gpio, true);
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raw_spin_unlock_irqrestore(&pctrl->lock, flags);
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}
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static void owl_gpio_irq_ack(struct irq_data *data)
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{
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struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
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struct owl_pinctrl *pctrl = gpiochip_get_data(gc);
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const struct owl_gpio_port *port;
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void __iomem *gpio_base;
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unsigned long flags;
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unsigned int gpio = data->hwirq;
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/*
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* Switch the interrupt edge to the opposite edge of the interrupt
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* which got triggered for the case of emulating both edges
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*/
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if (irqd_get_trigger_type(data) == IRQ_TYPE_EDGE_BOTH) {
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if (owl_gpio_get(gc, gpio))
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irq_set_type(pctrl, gpio, IRQ_TYPE_EDGE_FALLING);
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else
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irq_set_type(pctrl, gpio, IRQ_TYPE_EDGE_RISING);
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}
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port = owl_gpio_get_port(pctrl, &gpio);
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if (WARN_ON(port == NULL))
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return;
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gpio_base = pctrl->base + port->offset;
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raw_spin_lock_irqsave(&pctrl->lock, flags);
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owl_gpio_update_reg(gpio_base + port->intc_ctl,
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OWL_GPIO_CTLR_PENDING, true);
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raw_spin_unlock_irqrestore(&pctrl->lock, flags);
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}
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static int owl_gpio_irq_set_type(struct irq_data *data, unsigned int type)
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{
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struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
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struct owl_pinctrl *pctrl = gpiochip_get_data(gc);
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if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
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irq_set_handler_locked(data, handle_level_irq);
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else
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irq_set_handler_locked(data, handle_edge_irq);
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irq_set_type(pctrl, data->hwirq, type);
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return 0;
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}
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static void owl_gpio_irq_handler(struct irq_desc *desc)
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{
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struct owl_pinctrl *pctrl = irq_desc_get_handler_data(desc);
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struct irq_chip *chip = irq_desc_get_chip(desc);
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struct irq_domain *domain = pctrl->chip.irq.domain;
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unsigned int parent = irq_desc_get_irq(desc);
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const struct owl_gpio_port *port;
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void __iomem *base;
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unsigned int pin, irq, offset = 0, i;
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unsigned long pending_irq;
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chained_irq_enter(chip, desc);
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for (i = 0; i < pctrl->soc->nports; i++) {
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port = &pctrl->soc->ports[i];
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base = pctrl->base + port->offset;
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/* skip ports that are not associated with this irq */
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if (parent != pctrl->irq[i])
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goto skip;
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pending_irq = readl_relaxed(base + port->intc_pd);
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for_each_set_bit(pin, &pending_irq, port->pins) {
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irq = irq_find_mapping(domain, offset + pin);
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generic_handle_irq(irq);
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/* clear pending interrupt */
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owl_gpio_update_reg(base + port->intc_pd, pin, true);
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}
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skip:
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offset += port->pins;
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}
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chained_irq_exit(chip, desc);
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}
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static int owl_gpio_init(struct owl_pinctrl *pctrl)
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{
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struct gpio_chip *chip;
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int ret;
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struct gpio_irq_chip *gpio_irq;
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int ret, i, j, offset;
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chip = &pctrl->chip;
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chip->base = -1;
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@ -714,6 +921,35 @@ static int owl_gpio_init(struct owl_pinctrl *pctrl)
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chip->owner = THIS_MODULE;
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chip->of_node = pctrl->dev->of_node;
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pctrl->irq_chip.name = chip->of_node->name;
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pctrl->irq_chip.irq_ack = owl_gpio_irq_ack;
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pctrl->irq_chip.irq_mask = owl_gpio_irq_mask;
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pctrl->irq_chip.irq_unmask = owl_gpio_irq_unmask;
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pctrl->irq_chip.irq_set_type = owl_gpio_irq_set_type;
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gpio_irq = &chip->irq;
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gpio_irq->chip = &pctrl->irq_chip;
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gpio_irq->handler = handle_simple_irq;
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gpio_irq->default_type = IRQ_TYPE_NONE;
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gpio_irq->parent_handler = owl_gpio_irq_handler;
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gpio_irq->parent_handler_data = pctrl;
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gpio_irq->num_parents = pctrl->num_irq;
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gpio_irq->parents = pctrl->irq;
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gpio_irq->map = devm_kcalloc(pctrl->dev, chip->ngpio,
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sizeof(*gpio_irq->map), GFP_KERNEL);
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if (!gpio_irq->map)
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return -ENOMEM;
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for (i = 0, offset = 0; i < pctrl->soc->nports; i++) {
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const struct owl_gpio_port *port = &pctrl->soc->ports[i];
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for (j = 0; j < port->pins; j++)
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gpio_irq->map[offset + j] = gpio_irq->parents[i];
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offset += port->pins;
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}
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ret = gpiochip_add_data(&pctrl->chip, pctrl);
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if (ret) {
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dev_err(pctrl->dev, "failed to register gpiochip\n");
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@ -728,7 +964,7 @@ int owl_pinctrl_probe(struct platform_device *pdev,
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{
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struct resource *res;
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struct owl_pinctrl *pctrl;
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int ret;
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int ret, i;
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pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL);
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if (!pctrl)
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@ -772,14 +1008,41 @@ int owl_pinctrl_probe(struct platform_device *pdev,
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&owl_pinctrl_desc, pctrl);
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if (IS_ERR(pctrl->pctrldev)) {
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dev_err(&pdev->dev, "could not register Actions OWL pinmux driver\n");
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return PTR_ERR(pctrl->pctrldev);
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ret = PTR_ERR(pctrl->pctrldev);
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goto err_exit;
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}
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ret = platform_irq_count(pdev);
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if (ret < 0)
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goto err_exit;
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pctrl->num_irq = ret;
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pctrl->irq = devm_kcalloc(&pdev->dev, pctrl->num_irq,
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sizeof(*pctrl->irq), GFP_KERNEL);
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if (!pctrl->irq) {
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ret = -ENOMEM;
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goto err_exit;
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}
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for (i = 0; i < pctrl->num_irq ; i++) {
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pctrl->irq[i] = platform_get_irq(pdev, i);
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if (pctrl->irq[i] < 0) {
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ret = pctrl->irq[i];
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goto err_exit;
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}
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}
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ret = owl_gpio_init(pctrl);
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if (ret)
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return ret;
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goto err_exit;
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platform_set_drvdata(pdev, pctrl);
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return 0;
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err_exit:
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clk_disable_unprepare(pctrl->clk);
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return ret;
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}
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@ -29,6 +29,18 @@ enum owl_pinconf_drv {
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OWL_PINCONF_DRV_12MA,
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};
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/* GPIO CTRL Bit Definition */
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#define OWL_GPIO_CTLR_PENDING 0
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#define OWL_GPIO_CTLR_ENABLE 1
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#define OWL_GPIO_CTLR_SAMPLE_CLK_24M 2
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/* GPIO TYPE Bit Definition */
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#define OWL_GPIO_INT_LEVEL_HIGH 0
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#define OWL_GPIO_INT_LEVEL_LOW 1
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#define OWL_GPIO_INT_EDGE_RISING 2
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#define OWL_GPIO_INT_EDGE_FALLING 3
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#define OWL_GPIO_INT_MASK 3
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/**
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* struct owl_pullctl - Actions pad pull control register
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* @reg: offset to the pull control register
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@ -121,6 +133,10 @@ struct owl_pinmux_func {
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* @outen: offset of the output enable register.
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* @inen: offset of the input enable register.
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* @dat: offset of the data register.
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* @intc_ctl: offset of the interrupt control register.
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* @intc_pd: offset of the interrupt pending register.
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* @intc_msk: offset of the interrupt mask register.
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* @intc_type: offset of the interrupt type register.
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*/
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struct owl_gpio_port {
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unsigned int offset;
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@ -128,6 +144,10 @@ struct owl_gpio_port {
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unsigned int outen;
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unsigned int inen;
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unsigned int dat;
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unsigned int intc_ctl;
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unsigned int intc_pd;
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unsigned int intc_msk;
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unsigned int intc_type;
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};
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/**
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@ -140,7 +160,7 @@ struct owl_gpio_port {
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* @ngroups: number of entries in @groups.
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* @padinfo: array describing the pad info of this SoC.
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* @ngpios: number of pingroups the driver should expose as GPIOs.
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* @port: array describing all GPIO ports of this SoC.
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* @ports: array describing all GPIO ports of this SoC.
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* @nports: number of GPIO ports in this SoC.
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*/
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struct owl_pinctrl_soc_data {
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@ -1821,22 +1821,27 @@ static struct owl_padinfo s900_padinfo[NUM_PADS] = {
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[SGPIO3] = PAD_INFO_PULLCTL_ST(SGPIO3)
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};
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#define OWL_GPIO_PORT(port, base, count, _outen, _inen, _dat) \
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[OWL_GPIO_PORT_##port] = { \
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.offset = base, \
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.pins = count, \
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.outen = _outen, \
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.inen = _inen, \
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.dat = _dat, \
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#define OWL_GPIO_PORT(port, base, count, _outen, _inen, _dat, \
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_intc_ctl, _intc_pd, _intc_msk, _intc_type) \
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[OWL_GPIO_PORT_##port] = { \
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.offset = base, \
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.pins = count, \
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.outen = _outen, \
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.inen = _inen, \
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.dat = _dat, \
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.intc_ctl = _intc_ctl, \
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.intc_pd = _intc_pd, \
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.intc_msk = _intc_msk, \
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.intc_type = _intc_type, \
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}
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static const struct owl_gpio_port s900_gpio_ports[] = {
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OWL_GPIO_PORT(A, 0x0000, 32, 0x0, 0x4, 0x8),
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OWL_GPIO_PORT(B, 0x000C, 32, 0x0, 0x4, 0x8),
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OWL_GPIO_PORT(C, 0x0018, 12, 0x0, 0x4, 0x8),
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OWL_GPIO_PORT(D, 0x0024, 30, 0x0, 0x4, 0x8),
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OWL_GPIO_PORT(E, 0x0030, 32, 0x0, 0x4, 0x8),
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OWL_GPIO_PORT(F, 0x00F0, 8, 0x0, 0x4, 0x8)
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OWL_GPIO_PORT(A, 0x0000, 32, 0x0, 0x4, 0x8, 0x204, 0x208, 0x20C, 0x240),
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OWL_GPIO_PORT(B, 0x000C, 32, 0x0, 0x4, 0x8, 0x534, 0x204, 0x208, 0x23C),
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OWL_GPIO_PORT(C, 0x0018, 12, 0x0, 0x4, 0x8, 0x52C, 0x200, 0x204, 0x238),
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OWL_GPIO_PORT(D, 0x0024, 30, 0x0, 0x4, 0x8, 0x524, 0x1FC, 0x200, 0x234),
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OWL_GPIO_PORT(E, 0x0030, 32, 0x0, 0x4, 0x8, 0x51C, 0x1F8, 0x1FC, 0x230),
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OWL_GPIO_PORT(F, 0x00F0, 8, 0x0, 0x4, 0x8, 0x460, 0x140, 0x144, 0x178)
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};
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static struct owl_pinctrl_soc_data s900_pinctrl_data = {
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