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drm/nv50/pm: initial work towards proper memory reclocking, with timings
Signed-off-by: Ben Skeggs <bskeggs@redhat.com> Signed-off-by: Martin Peres <martin.peres@labri.fr>
This commit is contained in:
Ben Skeggs
parent
2d85bc8855
commit
6bdf68c9a4
@ -352,8 +352,13 @@ nv50_pm_clocks_get(struct drm_device *dev, struct nouveau_pm_level *perflvl)
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}
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struct nv50_pm_state {
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struct nouveau_pm_level *perflvl;
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struct hwsq_ucode mclk_hwsq;
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u32 mscript;
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u32 mmast;
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u32 mctrl;
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u32 mcoef;
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u32 emast;
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u32 nctrl;
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@ -415,36 +420,155 @@ clk_same(u32 a, u32 b)
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return ((a / 1000) == (b / 1000));
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}
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static void
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mclk_precharge(struct nouveau_mem_exec_func *exec)
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{
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struct nv50_pm_state *info = exec->priv;
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struct hwsq_ucode *hwsq = &info->mclk_hwsq;
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hwsq_wr32(hwsq, 0x1002d4, 0x00000001);
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}
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static void
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mclk_refresh(struct nouveau_mem_exec_func *exec)
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{
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struct nv50_pm_state *info = exec->priv;
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struct hwsq_ucode *hwsq = &info->mclk_hwsq;
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hwsq_wr32(hwsq, 0x1002d0, 0x00000001);
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}
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static void
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mclk_refresh_auto(struct nouveau_mem_exec_func *exec, bool enable)
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{
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struct nv50_pm_state *info = exec->priv;
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struct hwsq_ucode *hwsq = &info->mclk_hwsq;
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hwsq_wr32(hwsq, 0x100210, enable ? 0x80000000 : 0x00000000);
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}
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static void
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mclk_refresh_self(struct nouveau_mem_exec_func *exec, bool enable)
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{
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struct nv50_pm_state *info = exec->priv;
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struct hwsq_ucode *hwsq = &info->mclk_hwsq;
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hwsq_wr32(hwsq, 0x1002dc, enable ? 0x00000001 : 0x00000000);
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}
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static void
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mclk_wait(struct nouveau_mem_exec_func *exec, u32 nsec)
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{
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struct nv50_pm_state *info = exec->priv;
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struct hwsq_ucode *hwsq = &info->mclk_hwsq;
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if (nsec > 1000)
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hwsq_usec(hwsq, (nsec + 500) / 1000);
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}
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static u32
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mclk_mrg(struct nouveau_mem_exec_func *exec, int mr)
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{
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if (mr <= 1)
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return nv_rd32(exec->dev, 0x1002c0 + ((mr - 0) * 4));
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if (mr <= 3)
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return nv_rd32(exec->dev, 0x1002e0 + ((mr - 2) * 4));
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return 0;
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}
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static void
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mclk_mrs(struct nouveau_mem_exec_func *exec, int mr, u32 data)
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{
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struct drm_nouveau_private *dev_priv = exec->dev->dev_private;
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struct nv50_pm_state *info = exec->priv;
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struct hwsq_ucode *hwsq = &info->mclk_hwsq;
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if (mr <= 1) {
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if (dev_priv->vram_rank_B)
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hwsq_wr32(hwsq, 0x1002c8 + ((mr - 0) * 4), data);
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hwsq_wr32(hwsq, 0x1002c0 + ((mr - 0) * 4), data);
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} else
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if (mr <= 3) {
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if (dev_priv->vram_rank_B)
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hwsq_wr32(hwsq, 0x1002e8 + ((mr - 2) * 4), data);
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hwsq_wr32(hwsq, 0x1002e0 + ((mr - 2) * 4), data);
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}
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}
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static void
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mclk_clock_set(struct nouveau_mem_exec_func *exec)
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{
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struct nv50_pm_state *info = exec->priv;
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struct hwsq_ucode *hwsq = &info->mclk_hwsq;
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u32 ctrl = nv_rd32(exec->dev, 0x004008);
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info->mmast = nv_rd32(exec->dev, 0x00c040);
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info->mmast &= ~0xc0000000; /* get MCLK_2 from HREF */
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info->mmast |= 0x0000c000; /* use MCLK_2 as MPLL_BYPASS clock */
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hwsq_wr32(hwsq, 0xc040, info->mmast);
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hwsq_wr32(hwsq, 0x4008, ctrl | 0x00000200); /* bypass MPLL */
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if (info->mctrl & 0x80000000)
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hwsq_wr32(hwsq, 0x400c, info->mcoef);
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hwsq_wr32(hwsq, 0x4008, info->mctrl);
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}
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static void
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mclk_timing_set(struct nouveau_mem_exec_func *exec)
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{
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struct drm_device *dev = exec->dev;
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struct nv50_pm_state *info = exec->priv;
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struct nouveau_pm_level *perflvl = info->perflvl;
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struct hwsq_ucode *hwsq = &info->mclk_hwsq;
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int i;
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for (i = 0; i < 9; i++) {
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u32 reg = 0x100220 + (i * 4);
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u32 val = nv_rd32(dev, reg);
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if (val != perflvl->timing.reg[i])
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hwsq_wr32(hwsq, reg, perflvl->timing.reg[i]);
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}
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}
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static int
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calc_mclk(struct drm_device *dev, u32 freq, struct hwsq_ucode *hwsq)
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calc_mclk(struct drm_device *dev, struct nouveau_pm_level *perflvl,
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struct nv50_pm_state *info)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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struct nouveau_mem_exec_func exec = {
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.dev = dev,
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.precharge = mclk_precharge,
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.refresh = mclk_refresh,
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.refresh_auto = mclk_refresh_auto,
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.refresh_self = mclk_refresh_self,
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.wait = mclk_wait,
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.mrg = mclk_mrg,
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.mrs = mclk_mrs,
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.clock_set = mclk_clock_set,
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.timing_set = mclk_timing_set,
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.priv = info
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};
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struct hwsq_ucode *hwsq = &info->mclk_hwsq;
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struct pll_lims pll;
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u32 mast = nv_rd32(dev, 0x00c040);
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u32 ctrl = nv_rd32(dev, 0x004008);
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u32 coef = nv_rd32(dev, 0x00400c);
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u32 orig = ctrl;
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u32 crtc_mask = 0;
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int N, M, P;
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int ret, i;
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/* use pcie refclock if possible, otherwise use mpll */
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ctrl &= ~0x81ff0200;
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if (clk_same(freq, read_clk(dev, clk_src_href))) {
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ctrl |= 0x00000200 | (pll.log2p_bias << 19);
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info->mctrl = nv_rd32(dev, 0x004008);
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info->mctrl &= ~0x81ff0200;
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if (clk_same(perflvl->memory, read_clk(dev, clk_src_href))) {
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info->mctrl |= 0x00000200 | (pll.log2p_bias << 19);
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} else {
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ret = calc_pll(dev, 0x4008, &pll, freq, &N, &M, &P);
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ret = calc_pll(dev, 0x4008, &pll, perflvl->memory, &N, &M, &P);
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if (ret == 0)
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return -EINVAL;
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ctrl |= 0x80000000 | (P << 22) | (P << 16);
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ctrl |= pll.log2p_bias << 19;
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coef = (N << 8) | M;
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info->mctrl |= 0x80000000 | (P << 22) | (P << 16);
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info->mctrl |= pll.log2p_bias << 19;
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info->mcoef = (N << 8) | M;
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}
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mast &= ~0xc0000000; /* get MCLK_2 from HREF */
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mast |= 0x0000c000; /* use MCLK_2 as MPLL_BYPASS clock */
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/* determine active crtcs */
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for (i = 0; i < 2; i++) {
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if (nv_rd32(dev, NV50_PDISPLAY_CRTC_C(i, CLOCK)))
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@ -462,25 +586,10 @@ calc_mclk(struct drm_device *dev, u32 freq, struct hwsq_ucode *hwsq)
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hwsq_setf(hwsq, 0x10, 0); /* disable bus access */
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hwsq_op5f(hwsq, 0x00, 0x01); /* no idea :s */
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/* prepare memory controller */
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hwsq_wr32(hwsq, 0x1002d4, 0x00000001); /* precharge banks and idle */
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hwsq_wr32(hwsq, 0x1002d0, 0x00000001); /* force refresh */
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hwsq_wr32(hwsq, 0x100210, 0x00000000); /* stop the automatic refresh */
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hwsq_wr32(hwsq, 0x1002dc, 0x00000001); /* start self refresh mode */
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ret = nouveau_mem_exec(&exec, perflvl);
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if (ret)
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return ret;
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/* reclock memory */
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hwsq_wr32(hwsq, 0xc040, mast);
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hwsq_wr32(hwsq, 0x4008, orig | 0x00000200); /* bypass MPLL */
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hwsq_wr32(hwsq, 0x400c, coef);
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hwsq_wr32(hwsq, 0x4008, ctrl);
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/* restart memory controller */
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hwsq_wr32(hwsq, 0x1002d4, 0x00000001); /* precharge banks and idle */
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hwsq_wr32(hwsq, 0x1002dc, 0x00000000); /* stop self refresh mode */
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hwsq_wr32(hwsq, 0x100210, 0x80000000); /* restart automatic refresh */
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hwsq_usec(hwsq, 12); /* wait for the PLL to stabilize */
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hwsq_usec(hwsq, 48); /* may be unnecessary: causes flickering */
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hwsq_setf(hwsq, 0x10, 1); /* enable bus access */
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hwsq_op5f(hwsq, 0x00, 0x00); /* no idea, reverse of 0x00, 0x01? */
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if (dev_priv->chipset >= 0x92)
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@ -506,6 +615,17 @@ nv50_pm_clocks_pre(struct drm_device *dev, struct nouveau_pm_level *perflvl)
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info = kmalloc(sizeof(*info), GFP_KERNEL);
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if (!info)
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return ERR_PTR(-ENOMEM);
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info->perflvl = perflvl;
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/* memory: build hwsq ucode which we'll use to reclock memory.
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* use pcie refclock if possible, otherwise use mpll */
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info->mclk_hwsq.len = 0;
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if (perflvl->memory) {
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ret = calc_mclk(dev, perflvl, info);
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if (ret)
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goto error;
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info->mscript = perflvl->memscript;
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}
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/* core: for the moment at least, always use nvpll */
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clk = calc_pll(dev, 0x4028, &pll, perflvl->core, &N, &M, &P1);
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@ -536,18 +656,6 @@ nv50_pm_clocks_pre(struct drm_device *dev, struct nouveau_pm_level *perflvl)
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info->scoef = (N << 8) | M;
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}
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/* memory: build hwsq ucode which we'll use to reclock memory */
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info->mclk_hwsq.len = 0;
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if (perflvl->memory) {
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clk = calc_mclk(dev, perflvl->memory, &info->mclk_hwsq);
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if (clk < 0) {
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ret = clk;
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goto error;
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}
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info->mscript = perflvl->memscript;
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}
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/* vdec: avoid modifying xpll until we know exactly how the other
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* clock domains work, i suspect at least some of them can also be
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* tied to xpll...
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