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MIPS: bitops: Implement test_and_set_bit() in terms of _lock variant
The only difference between test_and_set_bit() & test_and_set_bit_lock() is memory ordering barrier semantics - the former provides a full barrier whilst the latter only provides acquire semantics. We can therefore implement test_and_set_bit() in terms of test_and_set_bit_lock() with the addition of the extra memory barrier. Do this in order to avoid duplicating logic. Signed-off-by: Paul Burton <paul.burton@mips.com> Cc: linux-mips@vger.kernel.org Cc: Huacai Chen <chenhc@lemote.com> Cc: Jiaxun Yang <jiaxun.yang@flygoat.com> Cc: linux-kernel@vger.kernel.org
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@ -31,8 +31,6 @@
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void __mips_set_bit(unsigned long nr, volatile unsigned long *addr);
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void __mips_clear_bit(unsigned long nr, volatile unsigned long *addr);
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void __mips_change_bit(unsigned long nr, volatile unsigned long *addr);
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int __mips_test_and_set_bit(unsigned long nr,
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volatile unsigned long *addr);
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int __mips_test_and_set_bit_lock(unsigned long nr,
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volatile unsigned long *addr);
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int __mips_test_and_clear_bit(unsigned long nr,
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@ -235,61 +233,6 @@ static inline void change_bit(unsigned long nr, volatile unsigned long *addr)
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} while (unlikely(!temp));
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}
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/*
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* test_and_set_bit - Set a bit and return its old value
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* @nr: Bit to set
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* @addr: Address to count from
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*
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* This operation is atomic and cannot be reordered.
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* It also implies a memory barrier.
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*/
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static inline int test_and_set_bit(unsigned long nr,
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volatile unsigned long *addr)
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{
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unsigned long *m = ((unsigned long *)addr) + (nr >> SZLONG_LOG);
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int bit = nr & SZLONG_MASK;
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unsigned long res, temp;
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smp_mb__before_llsc();
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if (!kernel_uses_llsc) {
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res = __mips_test_and_set_bit(nr, addr);
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} else if (R10000_LLSC_WAR) {
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__asm__ __volatile__(
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" .set push \n"
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" .set arch=r4000 \n"
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"1: " __LL "%0, %1 # test_and_set_bit \n"
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" or %2, %0, %3 \n"
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" " __SC "%2, %1 \n"
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" beqzl %2, 1b \n"
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" and %2, %0, %3 \n"
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" .set pop \n"
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: "=&r" (temp), "+" GCC_OFF_SMALL_ASM() (*m), "=&r" (res)
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: "r" (1UL << bit)
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: __LLSC_CLOBBER);
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} else {
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loongson_llsc_mb();
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do {
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__asm__ __volatile__(
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" .set push \n"
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" .set "MIPS_ISA_ARCH_LEVEL" \n"
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" " __LL "%0, %1 # test_and_set_bit \n"
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" or %2, %0, %3 \n"
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" " __SC "%2, %1 \n"
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" .set pop \n"
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: "=&r" (temp), "+" GCC_OFF_SMALL_ASM() (*m), "=&r" (res)
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: "r" (1UL << bit)
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: __LLSC_CLOBBER);
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} while (unlikely(!res));
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res = temp & (1UL << bit);
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}
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smp_llsc_mb();
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return res != 0;
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}
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/*
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* test_and_set_bit_lock - Set a bit and return its old value
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* @nr: Bit to set
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@ -321,6 +264,7 @@ static inline int test_and_set_bit_lock(unsigned long nr,
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: "r" (1UL << bit)
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: __LLSC_CLOBBER);
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} else {
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loongson_llsc_mb();
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do {
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__asm__ __volatile__(
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" .set push \n"
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@ -341,6 +285,22 @@ static inline int test_and_set_bit_lock(unsigned long nr,
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return res != 0;
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}
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/*
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* test_and_set_bit - Set a bit and return its old value
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* @nr: Bit to set
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* @addr: Address to count from
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*
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* This operation is atomic and cannot be reordered.
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* It also implies a memory barrier.
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*/
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static inline int test_and_set_bit(unsigned long nr,
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volatile unsigned long *addr)
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{
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smp_mb__before_llsc();
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return test_and_set_bit_lock(nr, addr);
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}
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/*
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* test_and_clear_bit - Clear a bit and return its old value
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* @nr: Bit to clear
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@ -77,32 +77,6 @@ void __mips_change_bit(unsigned long nr, volatile unsigned long *addr)
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EXPORT_SYMBOL(__mips_change_bit);
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/**
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* __mips_test_and_set_bit - Set a bit and return its old value. This is
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* called by test_and_set_bit() if it cannot find a faster solution.
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* @nr: Bit to set
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* @addr: Address to count from
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*/
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int __mips_test_and_set_bit(unsigned long nr,
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volatile unsigned long *addr)
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{
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unsigned long *a = (unsigned long *)addr;
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unsigned bit = nr & SZLONG_MASK;
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unsigned long mask;
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unsigned long flags;
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int res;
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a += nr >> SZLONG_LOG;
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mask = 1UL << bit;
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raw_local_irq_save(flags);
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res = (mask & *a) != 0;
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*a |= mask;
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raw_local_irq_restore(flags);
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return res;
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}
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EXPORT_SYMBOL(__mips_test_and_set_bit);
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/**
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* __mips_test_and_set_bit_lock - Set a bit and return its old value. This is
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* called by test_and_set_bit_lock() if it cannot find a faster solution.
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