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sparc32: Use PROM device probing for sun4m irq registers.
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
David S. Miller
parent
2e57572a50
commit
69c010b245
@ -272,17 +272,18 @@ smp4m_ticker:
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*/
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maybe_smp4m_msg:
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GET_PROCESSOR4M_ID(o3)
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set sun4m_interrupts, %l5
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ld [%l5], %o5
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sethi %hi(sun4m_irq_percpu), %l5
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sll %o3, 2, %o3
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or %l5, %lo(sun4m_irq_percpu), %o5
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sethi %hi(0x40000000), %o2
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sll %o3, 12, %o3
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ld [%o5 + %o3], %o1
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andcc %o1, %o2, %g0
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ld [%o1 + 0x00], %o3 ! sun4m_irq_percpu[cpu]->pending
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andcc %o3, %o2, %g0
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be,a smp4m_ticker
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cmp %l7, 14
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st %o2, [%o5 + 0x4]
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st %o2, [%o1 + 0x04] ! sun4m_irq_percpu[cpu]->clear=0x40000000
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WRITE_PAUSE
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ld [%o5], %g0
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ld [%o1 + 0x00], %g0 ! sun4m_irq_percpu[cpu]->pending
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WRITE_PAUSE
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or %l0, PSR_PIL, %l4
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wr %l4, 0x0, %psr
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@ -300,16 +301,16 @@ linux_trap_ipi15_sun4m:
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SAVE_ALL
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sethi %hi(0x80000000), %o2
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GET_PROCESSOR4M_ID(o0)
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set sun4m_interrupts, %l5
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ld [%l5], %o5
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sll %o0, 12, %o0
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add %o5, %o0, %o5
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ld [%o5], %o3
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sethi %hi(sun4m_irq_percpu), %l5
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or %l5, %lo(sun4m_irq_percpu), %o5
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sll %o0, 2, %o0
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ld [%o5 + %o0], %o5
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ld [%o5 + 0x00], %o3 ! sun4m_irq_percpu[cpu]->pending
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andcc %o3, %o2, %g0
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be 1f ! Must be an NMI async memory error
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st %o2, [%o5 + 4]
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st %o2, [%o5 + 0x04] ! sun4m_irq_percpu[cpu]->clear=0x80000000
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WRITE_PAUSE
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ld [%o5], %g0
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ld [%o5 + 0x00], %g0 ! sun4m_irq_percpu[cpu]->pending
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WRITE_PAUSE
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or %l0, PSR_PIL, %l4
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wr %l4, 0x0, %psr
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@ -323,12 +324,11 @@ linux_trap_ipi15_sun4m:
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1:
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/* NMI async memory error handling. */
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sethi %hi(0x80000000), %l4
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sethi %hi(0x4000), %o3
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sub %o5, %o0, %o5
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add %o5, %o3, %l5
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st %l4, [%l5 + 0xc]
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sethi %hi(sun4m_irq_global), %o5
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ld [%o5 + %lo(sun4m_irq_global)], %l5
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st %l4, [%l5 + 0x0c] ! sun4m_irq_global->mask_set=0x80000000
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WRITE_PAUSE
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ld [%l5], %g0
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ld [%l5 + 0x00], %g0 ! sun4m_irq_global->pending
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WRITE_PAUSE
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or %l0, PSR_PIL, %l4
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wr %l4, 0x0, %psr
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@ -337,9 +337,9 @@ linux_trap_ipi15_sun4m:
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WRITE_PAUSE
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call sun4m_nmi
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nop
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st %l4, [%l5 + 0x8]
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st %l4, [%l5 + 0x08] ! sun4m_irq_global->mask_clear=0x80000000
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WRITE_PAUSE
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ld [%l5], %g0
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ld [%l5 + 0x00], %g0 ! sun4m_irq_global->pending
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WRITE_PAUSE
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RESTORE_ALL
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@ -41,53 +41,25 @@
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#include "irq.h"
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/* On the sun4m, just like the timers, we have both per-cpu and master
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* interrupt registers.
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*/
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/* These registers are used for sending/receiving irqs from/to
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* different cpu's.
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*/
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struct sun4m_intreg_percpu {
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unsigned int tbt; /* Interrupts still pending for this cpu. */
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/* These next two registers are WRITE-ONLY and are only
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* "on bit" sensitive, "off bits" written have NO affect.
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*/
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unsigned int clear; /* Clear this cpus irqs here. */
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unsigned int set; /* Set this cpus irqs here. */
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unsigned char space[PAGE_SIZE - 12];
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struct sun4m_irq_percpu {
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u32 pending;
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u32 clear;
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u32 set;
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};
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/*
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* djhr
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* Actually the clear and set fields in this struct are misleading..
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* according to the SLAVIO manual (and the same applies for the SEC)
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* the clear field clears bits in the mask which will ENABLE that IRQ
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* the set field sets bits in the mask to DISABLE the IRQ.
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*
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* Also the undirected_xx address in the SLAVIO is defined as
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* RESERVED and write only..
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*
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* DAVEM_NOTE: The SLAVIO only specifies behavior on uniprocessor
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* sun4m machines, for MP the layout makes more sense.
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*/
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struct sun4m_intregs {
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struct sun4m_intreg_percpu cpu_intregs[SUN4M_NCPUS];
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unsigned int tbt; /* IRQ's that are still pending. */
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unsigned int irqs; /* Master IRQ bits. */
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/* Again, like the above, two these registers are WRITE-ONLY. */
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unsigned int clear; /* Clear master IRQ's by setting bits here. */
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unsigned int set; /* Set master IRQ's by setting bits here. */
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/* This register is both READ and WRITE. */
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unsigned int undirected_target; /* Which cpu gets undirected irqs. */
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struct sun4m_irq_global {
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u32 pending;
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u32 mask;
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u32 mask_clear;
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u32 mask_set;
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u32 interrupt_target;
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};
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/* Code in entry.S needs to get at these register mappings. */
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struct sun4m_irq_percpu __iomem *sun4m_irq_percpu[SUN4M_NCPUS];
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struct sun4m_irq_global __iomem *sun4m_irq_global;
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static unsigned long dummy;
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struct sun4m_intregs *sun4m_interrupts;
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unsigned long *irq_rcvreg = &dummy;
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/* Dave Redman (djhr@tadpole.co.uk)
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@ -182,9 +154,9 @@ static void sun4m_disable_irq(unsigned int irq_nr)
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mask = sun4m_get_irqmask(irq_nr);
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local_irq_save(flags);
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if (irq_nr > 15)
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sun4m_interrupts->set = mask;
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sbus_writel(mask, &sun4m_irq_global->mask_set);
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else
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sun4m_interrupts->cpu_intregs[cpu].set = mask;
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sbus_writel(mask, &sun4m_irq_percpu[cpu]->set);
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local_irq_restore(flags);
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}
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@ -201,13 +173,13 @@ static void sun4m_enable_irq(unsigned int irq_nr)
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mask = sun4m_get_irqmask(irq_nr);
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local_irq_save(flags);
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if (irq_nr > 15)
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sun4m_interrupts->clear = mask;
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sbus_writel(mask, &sun4m_irq_global->mask_clear);
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else
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sun4m_interrupts->cpu_intregs[cpu].clear = mask;
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sbus_writel(mask, &sun4m_irq_percpu[cpu]->clear);
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local_irq_restore(flags);
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} else {
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local_irq_save(flags);
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sun4m_interrupts->clear = SUN4M_INT_FLOPPY;
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sbus_writel(SUN4M_INT_FLOPPY, &sun4m_irq_global->mask_clear);
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local_irq_restore(flags);
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}
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}
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@ -236,34 +208,30 @@ static unsigned long cpu_pil_to_imask[16] = {
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*/
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static void sun4m_disable_pil_irq(unsigned int pil)
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{
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sun4m_interrupts->set = cpu_pil_to_imask[pil];
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sbus_writel(cpu_pil_to_imask[pil], &sun4m_irq_global->mask_set);
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}
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static void sun4m_enable_pil_irq(unsigned int pil)
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{
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sun4m_interrupts->clear = cpu_pil_to_imask[pil];
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sbus_writel(cpu_pil_to_imask[pil], &sun4m_irq_global->mask_clear);
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}
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#ifdef CONFIG_SMP
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static void sun4m_send_ipi(int cpu, int level)
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{
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unsigned long mask;
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mask = sun4m_get_irqmask(level);
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sun4m_interrupts->cpu_intregs[cpu].set = mask;
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unsigned long mask = sun4m_get_irqmask(level);
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sbus_writel(mask, &sun4m_irq_percpu[cpu]->set);
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}
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static void sun4m_clear_ipi(int cpu, int level)
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{
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unsigned long mask;
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mask = sun4m_get_irqmask(level);
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sun4m_interrupts->cpu_intregs[cpu].clear = mask;
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unsigned long mask = sun4m_get_irqmask(level);
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sbus_writel(mask, &sun4m_irq_percpu[cpu]->clear);
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}
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static void sun4m_set_udt(int cpu)
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{
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sun4m_interrupts->undirected_target = cpu;
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sbus_writel(cpu, &sun4m_irq_global->interrupt_target);
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}
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#endif
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@ -347,7 +315,7 @@ static void __init sun4m_init_timers(irq_handler_t counter_fn)
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for (i = 0; i < num_cpu_timers; i++)
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sbus_writel(0, &timers_percpu[i]->l14_limit);
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if (num_cpu_timers == 4)
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sbus_writel(SUN4M_INT_E14, &sun4m_interrupts->set);
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sbus_writel(SUN4M_INT_E14, &sun4m_irq_global->mask_set);
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#ifdef CONFIG_SMP
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{
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@ -372,62 +340,38 @@ static void __init sun4m_init_timers(irq_handler_t counter_fn)
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void __init sun4m_init_IRQ(void)
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{
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int ie_node,i;
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struct linux_prom_registers int_regs[PROMREG_MAX];
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int num_regs;
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struct resource r;
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int mid;
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struct device_node *dp = of_find_node_by_name(NULL, "interrupt");
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int len, i, mid, num_cpu_iregs;
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const u32 *addr;
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if (!dp) {
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printk(KERN_ERR "sun4m_init_IRQ: No 'interrupt' node.\n");
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return;
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}
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addr = of_get_property(dp, "address", &len);
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if (!addr) {
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printk(KERN_ERR "sun4m_init_IRQ: No 'address' prop.\n");
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return;
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}
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num_cpu_iregs = (len / sizeof(u32)) - 1;
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for (i = 0; i < num_cpu_iregs; i++) {
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sun4m_irq_percpu[i] = (void __iomem *)
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(unsigned long) addr[i];
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}
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sun4m_irq_global = (void __iomem *)
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(unsigned long) addr[num_cpu_iregs];
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local_irq_disable();
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if((ie_node = prom_searchsiblings(prom_getchild(prom_root_node), "obio")) == 0 ||
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(ie_node = prom_getchild (ie_node)) == 0 ||
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(ie_node = prom_searchsiblings (ie_node, "interrupt")) == 0) {
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prom_printf("Cannot find /obio/interrupt node\n");
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prom_halt();
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}
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num_regs = prom_getproperty(ie_node, "reg", (char *) int_regs,
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sizeof(int_regs));
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num_regs = (num_regs/sizeof(struct linux_prom_registers));
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/* Apply the obio ranges to these registers. */
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prom_apply_obio_ranges(int_regs, num_regs);
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int_regs[4].phys_addr = int_regs[num_regs-1].phys_addr;
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int_regs[4].reg_size = int_regs[num_regs-1].reg_size;
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int_regs[4].which_io = int_regs[num_regs-1].which_io;
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for(ie_node = 1; ie_node < 4; ie_node++) {
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int_regs[ie_node].phys_addr = int_regs[ie_node-1].phys_addr + PAGE_SIZE;
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int_regs[ie_node].reg_size = int_regs[ie_node-1].reg_size;
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int_regs[ie_node].which_io = int_regs[ie_node-1].which_io;
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}
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memset((char *)&r, 0, sizeof(struct resource));
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/* Map the interrupt registers for all possible cpus. */
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r.flags = int_regs[0].which_io;
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r.start = int_regs[0].phys_addr;
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sun4m_interrupts = (struct sun4m_intregs *) of_ioremap(&r, 0,
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PAGE_SIZE*SUN4M_NCPUS, "interrupts_percpu");
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/* Map the system interrupt control registers. */
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r.flags = int_regs[4].which_io;
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r.start = int_regs[4].phys_addr;
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of_ioremap(&r, 0, int_regs[4].reg_size, "interrupts_system");
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sun4m_interrupts->set = ~SUN4M_INT_MASKALL;
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sbus_writel(~SUN4M_INT_MASKALL, &sun4m_irq_global->mask_set);
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for (i = 0; !cpu_find_by_instance(i, NULL, &mid); i++)
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sun4m_interrupts->cpu_intregs[mid].clear = ~0x17fff;
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sbus_writel(~0x17fff, &sun4m_irq_percpu[mid]->clear);
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if (!cpu_find_by_instance(1, NULL, NULL)) {
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/* system wide interrupts go to cpu 0, this should always
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* be safe because it is guaranteed to be fitted or OBP doesn't
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* come up
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*
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* Not sure, but writing here on SLAVIO systems may puke
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* so I don't do it unless there is more than 1 cpu.
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*/
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irq_rcvreg = (unsigned long *)
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&sun4m_interrupts->undirected_target;
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sun4m_interrupts->undirected_target = 0;
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if (num_cpu_iregs == 4) {
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irq_rcvreg = (unsigned long *) &sun4m_irq_global->interrupt_target;
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sbus_writel(0, &sun4m_irq_global->interrupt_target);
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}
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BTFIXUPSET_CALL(enable_irq, sun4m_enable_irq, BTFIXUPCALL_NORM);
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BTFIXUPSET_CALL(disable_irq, sun4m_disable_irq, BTFIXUPCALL_NORM);
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@ -442,5 +386,6 @@ void __init sun4m_init_IRQ(void)
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BTFIXUPSET_CALL(clear_cpu_int, sun4m_clear_ipi, BTFIXUPCALL_NORM);
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BTFIXUPSET_CALL(set_irq_udt, sun4m_set_udt, BTFIXUPCALL_NORM);
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#endif
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/* Cannot enable interrupts until OBP ticker is disabled. */
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}
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