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lib/raid6: Add AVX512 optimized xor_syndrome functions
Optimize RAID6 xor_syndrome functions to take advantage of the 512-bit ZMM integer instructions introduced in AVX512. AVX512 optimized xor_syndrome functions, which is simply based on sse2.c written by hpa. The patch was tested and benchmarked before submission on a hardware that has AVX512 flags to support such instructions Cc: H. Peter Anvin <hpa@zytor.com> Cc: Jim Kukunas <james.t.kukunas@linux.intel.com> Cc: Fenghua Yu <fenghua.yu@intel.com> Cc: Megha Dey <megha.dey@linux.intel.com> Signed-off-by: Gayatri Kammela <gayatri.kammela@intel.com> Reviewed-by: Fenghua Yu <fenghua.yu@intel.com> Signed-off-by: Shaohua Li <shli@fb.com>
This commit is contained in:
Gayatri Kammela
Shaohua Li
parent
161db5d165
commit
694dda62d2
@ -103,9 +103,68 @@ static void raid6_avx5121_gen_syndrome(int disks, size_t bytes, void **ptrs)
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kernel_fpu_end();
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}
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static void raid6_avx5121_xor_syndrome(int disks, int start, int stop,
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size_t bytes, void **ptrs)
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{
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u8 **dptr = (u8 **)ptrs;
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u8 *p, *q;
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int d, z, z0;
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z0 = stop; /* P/Q right side optimization */
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p = dptr[disks-2]; /* XOR parity */
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q = dptr[disks-1]; /* RS syndrome */
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kernel_fpu_begin();
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asm volatile("vmovdqa64 %0,%%zmm0"
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: : "m" (raid6_avx512_constants.x1d[0]));
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for (d = 0 ; d < bytes ; d += 64) {
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asm volatile("vmovdqa64 %0,%%zmm4\n\t"
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"vmovdqa64 %1,%%zmm2\n\t"
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"vpxorq %%zmm4,%%zmm2,%%zmm2"
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:
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: "m" (dptr[z0][d]), "m" (p[d]));
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/* P/Q data pages */
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for (z = z0-1 ; z >= start ; z--) {
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asm volatile("vpxorq %%zmm5,%%zmm5,%%zmm5\n\t"
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"vpcmpgtb %%zmm4,%%zmm5,%%k1\n\t"
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"vpmovm2b %%k1,%%zmm5\n\t"
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"vpaddb %%zmm4,%%zmm4,%%zmm4\n\t"
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"vpandq %%zmm0,%%zmm5,%%zmm5\n\t"
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"vpxorq %%zmm5,%%zmm4,%%zmm4\n\t"
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"vmovdqa64 %0,%%zmm5\n\t"
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"vpxorq %%zmm5,%%zmm2,%%zmm2\n\t"
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"vpxorq %%zmm5,%%zmm4,%%zmm4"
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:
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: "m" (dptr[z][d]));
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}
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/* P/Q left side optimization */
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for (z = start-1 ; z >= 0 ; z--) {
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asm volatile("vpxorq %%zmm5,%%zmm5,%%zmm5\n\t"
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"vpcmpgtb %%zmm4,%%zmm5,%%k1\n\t"
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"vpmovm2b %%k1,%%zmm5\n\t"
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"vpaddb %%zmm4,%%zmm4,%%zmm4\n\t"
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"vpandq %%zmm0,%%zmm5,%%zmm5\n\t"
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"vpxorq %%zmm5,%%zmm4,%%zmm4"
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:
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: );
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}
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asm volatile("vpxorq %0,%%zmm4,%%zmm4\n\t"
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/* Don't use movntdq for r/w memory area < cache line */
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"vmovdqa64 %%zmm4,%0\n\t"
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"vmovdqa64 %%zmm2,%1"
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:
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: "m" (q[d]), "m" (p[d]));
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}
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asm volatile("sfence" : : : "memory");
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kernel_fpu_end();
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}
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const struct raid6_calls raid6_avx512x1 = {
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raid6_avx5121_gen_syndrome,
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NULL, /* XOR not yet implemented */
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raid6_avx5121_xor_syndrome,
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raid6_have_avx512,
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"avx512x1",
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1 /* Has cache hints */
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@ -176,9 +235,93 @@ static void raid6_avx5122_gen_syndrome(int disks, size_t bytes, void **ptrs)
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kernel_fpu_end();
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}
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static void raid6_avx5122_xor_syndrome(int disks, int start, int stop,
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size_t bytes, void **ptrs)
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{
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u8 **dptr = (u8 **)ptrs;
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u8 *p, *q;
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int d, z, z0;
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z0 = stop; /* P/Q right side optimization */
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p = dptr[disks-2]; /* XOR parity */
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q = dptr[disks-1]; /* RS syndrome */
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kernel_fpu_begin();
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asm volatile("vmovdqa64 %0,%%zmm0"
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: : "m" (raid6_avx512_constants.x1d[0]));
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for (d = 0 ; d < bytes ; d += 128) {
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asm volatile("vmovdqa64 %0,%%zmm4\n\t"
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"vmovdqa64 %1,%%zmm6\n\t"
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"vmovdqa64 %2,%%zmm2\n\t"
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"vmovdqa64 %3,%%zmm3\n\t"
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"vpxorq %%zmm4,%%zmm2,%%zmm2\n\t"
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"vpxorq %%zmm6,%%zmm3,%%zmm3"
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:
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: "m" (dptr[z0][d]), "m" (dptr[z0][d+64]),
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"m" (p[d]), "m" (p[d+64]));
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/* P/Q data pages */
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for (z = z0-1 ; z >= start ; z--) {
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asm volatile("vpxorq %%zmm5,%%zmm5,%%zmm5\n\t"
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"vpxorq %%zmm7,%%zmm7,%%zmm7\n\t"
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"vpcmpgtb %%zmm4,%%zmm5,%%k1\n\t"
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"vpcmpgtb %%zmm6,%%zmm7,%%k2\n\t"
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"vpmovm2b %%k1,%%zmm5\n\t"
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"vpmovm2b %%k2,%%zmm7\n\t"
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"vpaddb %%zmm4,%%zmm4,%%zmm4\n\t"
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"vpaddb %%zmm6,%%zmm6,%%zmm6\n\t"
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"vpandq %%zmm0,%%zmm5,%%zmm5\n\t"
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"vpandq %%zmm0,%%zmm7,%%zmm7\n\t"
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"vpxorq %%zmm5,%%zmm4,%%zmm4\n\t"
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"vpxorq %%zmm7,%%zmm6,%%zmm6\n\t"
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"vmovdqa64 %0,%%zmm5\n\t"
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"vmovdqa64 %1,%%zmm7\n\t"
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"vpxorq %%zmm5,%%zmm2,%%zmm2\n\t"
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"vpxorq %%zmm7,%%zmm3,%%zmm3\n\t"
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"vpxorq %%zmm5,%%zmm4,%%zmm4\n\t"
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"vpxorq %%zmm7,%%zmm6,%%zmm6"
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:
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: "m" (dptr[z][d]), "m" (dptr[z][d+64]));
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}
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/* P/Q left side optimization */
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for (z = start-1 ; z >= 0 ; z--) {
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asm volatile("vpxorq %%zmm5,%%zmm5,%%zmm5\n\t"
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"vpxorq %%zmm7,%%zmm7,%%zmm7\n\t"
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"vpcmpgtb %%zmm4,%%zmm5,%%k1\n\t"
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"vpcmpgtb %%zmm6,%%zmm7,%%k2\n\t"
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"vpmovm2b %%k1,%%zmm5\n\t"
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"vpmovm2b %%k2,%%zmm7\n\t"
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"vpaddb %%zmm4,%%zmm4,%%zmm4\n\t"
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"vpaddb %%zmm6,%%zmm6,%%zmm6\n\t"
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"vpandq %%zmm0,%%zmm5,%%zmm5\n\t"
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"vpandq %%zmm0,%%zmm7,%%zmm7\n\t"
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"vpxorq %%zmm5,%%zmm4,%%zmm4\n\t"
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"vpxorq %%zmm7,%%zmm6,%%zmm6"
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:
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: );
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}
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asm volatile("vpxorq %0,%%zmm4,%%zmm4\n\t"
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"vpxorq %1,%%zmm6,%%zmm6\n\t"
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/* Don't use movntdq for r/w
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* memory area < cache line
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*/
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"vmovdqa64 %%zmm4,%0\n\t"
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"vmovdqa64 %%zmm6,%1\n\t"
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"vmovdqa64 %%zmm2,%2\n\t"
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"vmovdqa64 %%zmm3,%3"
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:
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: "m" (q[d]), "m" (q[d+64]), "m" (p[d]),
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"m" (p[d+64]));
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}
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asm volatile("sfence" : : : "memory");
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kernel_fpu_end();
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}
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const struct raid6_calls raid6_avx512x2 = {
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raid6_avx5122_gen_syndrome,
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NULL, /* XOR not yet implemented */
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raid6_avx5122_xor_syndrome,
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raid6_have_avx512,
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"avx512x2",
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1 /* Has cache hints */
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@ -282,9 +425,141 @@ static void raid6_avx5124_gen_syndrome(int disks, size_t bytes, void **ptrs)
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kernel_fpu_end();
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}
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static void raid6_avx5124_xor_syndrome(int disks, int start, int stop,
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size_t bytes, void **ptrs)
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{
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u8 **dptr = (u8 **)ptrs;
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u8 *p, *q;
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int d, z, z0;
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z0 = stop; /* P/Q right side optimization */
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p = dptr[disks-2]; /* XOR parity */
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q = dptr[disks-1]; /* RS syndrome */
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kernel_fpu_begin();
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asm volatile("vmovdqa64 %0,%%zmm0"
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:: "m" (raid6_avx512_constants.x1d[0]));
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for (d = 0 ; d < bytes ; d += 256) {
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asm volatile("vmovdqa64 %0,%%zmm4\n\t"
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"vmovdqa64 %1,%%zmm6\n\t"
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"vmovdqa64 %2,%%zmm12\n\t"
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"vmovdqa64 %3,%%zmm14\n\t"
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"vmovdqa64 %4,%%zmm2\n\t"
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"vmovdqa64 %5,%%zmm3\n\t"
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"vmovdqa64 %6,%%zmm10\n\t"
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"vmovdqa64 %7,%%zmm11\n\t"
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"vpxorq %%zmm4,%%zmm2,%%zmm2\n\t"
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"vpxorq %%zmm6,%%zmm3,%%zmm3\n\t"
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"vpxorq %%zmm12,%%zmm10,%%zmm10\n\t"
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"vpxorq %%zmm14,%%zmm11,%%zmm11"
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:
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: "m" (dptr[z0][d]), "m" (dptr[z0][d+64]),
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"m" (dptr[z0][d+128]), "m" (dptr[z0][d+192]),
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"m" (p[d]), "m" (p[d+64]), "m" (p[d+128]),
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"m" (p[d+192]));
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/* P/Q data pages */
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for (z = z0-1 ; z >= start ; z--) {
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asm volatile("vpxorq %%zmm5,%%zmm5,%%zmm5\n\t"
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"vpxorq %%zmm7,%%zmm7,%%zmm7\n\t"
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"vpxorq %%zmm13,%%zmm13,%%zmm13\n\t"
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"vpxorq %%zmm15,%%zmm15,%%zmm15\n\t"
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"prefetchnta %0\n\t"
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"prefetchnta %2\n\t"
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"vpcmpgtb %%zmm4,%%zmm5,%%k1\n\t"
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"vpcmpgtb %%zmm6,%%zmm7,%%k2\n\t"
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"vpcmpgtb %%zmm12,%%zmm13,%%k3\n\t"
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"vpcmpgtb %%zmm14,%%zmm15,%%k4\n\t"
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"vpmovm2b %%k1,%%zmm5\n\t"
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"vpmovm2b %%k2,%%zmm7\n\t"
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"vpmovm2b %%k3,%%zmm13\n\t"
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"vpmovm2b %%k4,%%zmm15\n\t"
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"vpaddb %%zmm4,%%zmm4,%%zmm4\n\t"
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"vpaddb %%zmm6,%%zmm6,%%zmm6\n\t"
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"vpaddb %%zmm12,%%zmm12,%%zmm12\n\t"
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"vpaddb %%Zmm14,%%zmm14,%%zmm14\n\t"
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"vpandq %%zmm0,%%zmm5,%%zmm5\n\t"
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"vpandq %%zmm0,%%zmm7,%%zmm7\n\t"
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"vpandq %%zmm0,%%zmm13,%%zmm13\n\t"
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"vpandq %%zmm0,%%zmm15,%%zmm15\n\t"
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"vpxorq %%zmm5,%%zmm4,%%zmm4\n\t"
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"vpxorq %%zmm7,%%zmm6,%%zmm6\n\t"
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"vpxorq %%zmm13,%%zmm12,%%zmm12\n\t"
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"vpxorq %%zmm15,%%zmm14,%%zmm14\n\t"
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"vmovdqa64 %0,%%zmm5\n\t"
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"vmovdqa64 %1,%%zmm7\n\t"
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"vmovdqa64 %2,%%zmm13\n\t"
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"vmovdqa64 %3,%%zmm15\n\t"
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"vpxorq %%zmm5,%%zmm2,%%zmm2\n\t"
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"vpxorq %%zmm7,%%zmm3,%%zmm3\n\t"
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"vpxorq %%zmm13,%%zmm10,%%zmm10\n\t"
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"vpxorq %%zmm15,%%zmm11,%%zmm11\n\t"
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"vpxorq %%zmm5,%%zmm4,%%zmm4\n\t"
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"vpxorq %%zmm7,%%zmm6,%%zmm6\n\t"
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"vpxorq %%zmm13,%%zmm12,%%zmm12\n\t"
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"vpxorq %%zmm15,%%zmm14,%%zmm14"
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:
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: "m" (dptr[z][d]), "m" (dptr[z][d+64]),
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"m" (dptr[z][d+128]),
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"m" (dptr[z][d+192]));
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}
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asm volatile("prefetchnta %0\n\t"
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"prefetchnta %1\n\t"
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:
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: "m" (q[d]), "m" (q[d+128]));
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/* P/Q left side optimization */
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for (z = start-1 ; z >= 0 ; z--) {
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asm volatile("vpxorq %%zmm5,%%zmm5,%%zmm5\n\t"
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"vpxorq %%zmm7,%%zmm7,%%zmm7\n\t"
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"vpxorq %%zmm13,%%zmm13,%%zmm13\n\t"
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"vpxorq %%zmm15,%%zmm15,%%zmm15\n\t"
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"vpcmpgtb %%zmm4,%%zmm5,%%k1\n\t"
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"vpcmpgtb %%zmm6,%%zmm7,%%k2\n\t"
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"vpcmpgtb %%zmm12,%%zmm13,%%k3\n\t"
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"vpcmpgtb %%zmm14,%%zmm15,%%k4\n\t"
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"vpmovm2b %%k1,%%zmm5\n\t"
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"vpmovm2b %%k2,%%zmm7\n\t"
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"vpmovm2b %%k3,%%zmm13\n\t"
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"vpmovm2b %%k4,%%zmm15\n\t"
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"vpaddb %%zmm4,%%zmm4,%%zmm4\n\t"
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"vpaddb %%zmm6,%%zmm6,%%zmm6\n\t"
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"vpaddb %%zmm12,%%zmm12,%%zmm12\n\t"
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"vpaddb %%zmm14,%%zmm14,%%zmm14\n\t"
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"vpandq %%zmm0,%%zmm5,%%zmm5\n\t"
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"vpandq %%zmm0,%%zmm7,%%zmm7\n\t"
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"vpandq %%zmm0,%%zmm13,%%zmm13\n\t"
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"vpandq %%zmm0,%%zmm15,%%zmm15\n\t"
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"vpxorq %%zmm5,%%zmm4,%%zmm4\n\t"
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"vpxorq %%zmm7,%%zmm6,%%zmm6\n\t"
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"vpxorq %%zmm13,%%zmm12,%%zmm12\n\t"
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"vpxorq %%zmm15,%%zmm14,%%zmm14"
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:
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: );
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}
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asm volatile("vmovntdq %%zmm2,%0\n\t"
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"vmovntdq %%zmm3,%1\n\t"
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"vmovntdq %%zmm10,%2\n\t"
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"vmovntdq %%zmm11,%3\n\t"
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"vpxorq %4,%%zmm4,%%zmm4\n\t"
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"vpxorq %5,%%zmm6,%%zmm6\n\t"
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"vpxorq %6,%%zmm12,%%zmm12\n\t"
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"vpxorq %7,%%zmm14,%%zmm14\n\t"
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"vmovntdq %%zmm4,%4\n\t"
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"vmovntdq %%zmm6,%5\n\t"
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"vmovntdq %%zmm12,%6\n\t"
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"vmovntdq %%zmm14,%7"
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:
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: "m" (p[d]), "m" (p[d+64]), "m" (p[d+128]),
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"m" (p[d+192]), "m" (q[d]), "m" (q[d+64]),
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"m" (q[d+128]), "m" (q[d+192]));
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}
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asm volatile("sfence" : : : "memory");
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kernel_fpu_end();
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}
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const struct raid6_calls raid6_avx512x4 = {
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raid6_avx5124_gen_syndrome,
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NULL, /* XOR not yet implemented */
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raid6_avx5124_xor_syndrome,
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raid6_have_avx512,
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"avx512x4",
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1 /* Has cache hints */
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