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ARM: EXYNOS4: Add support new EXYNOS4212 SoC

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This patch adds Samsung EXYNOS4212 SoC support.
The EXYNOS4212 integrates a ARM Cortex A9 multi-core.

Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
This commit is contained in:
Kukjin Kim 2011-08-24 17:25:09 +09:00
parent 54122447bb
commit 684653842b
6 changed files with 32 additions and 5 deletions
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5
arch/arm/mach-exynos4/Kconfig
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@ -15,6 +15,11 @@ config CPU_EXYNOS4210
help
Enable EXYNOS4210 CPU support
config SOC_EXYNOS4212
bool
help
Enable EXYNOS4212 SoC support
config EXYNOS4_MCT
bool
default y

6
arch/arm/mach-exynos4/Makefile
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@ -12,8 +12,10 @@ obj- :=
# Core support for EXYNOS4 system
obj-$(CONFIG_CPU_EXYNOS4210) += cpu.o init.o clock.o irq-combiner.o
obj-$(CONFIG_CPU_EXYNOS4210) += setup-i2c0.o irq-eint.o dma.o pmu.o
obj-$(CONFIG_ARCH_EXYNOS4) += cpu.o init.o clock.o irq-combiner.o
obj-$(CONFIG_ARCH_EXYNOS4) += setup-i2c0.o irq-eint.o dma.o pmu.o
obj-$(CONFIG_CPU_EXYNOS4210) += clock-exynos4210.o
obj-$(CONFIG_SOC_EXYNOS4212) += clock-exynos4212.o
obj-$(CONFIG_PM) += pm.o sleep.o
obj-$(CONFIG_CPU_IDLE) += cpuidle.o

6
arch/arm/mach-exynos4/cpu.c
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@ -241,7 +241,11 @@ static int __init exynos4_l2x0_cache_init(void)
{
/* TAG, Data Latency Control: 2cycle */
__raw_writel(0x110, S5P_VA_L2CC + L2X0_TAG_LATENCY_CTRL);
__raw_writel(0x110, S5P_VA_L2CC + L2X0_DATA_LATENCY_CTRL);
if (soc_is_exynos4210())
__raw_writel(0x110, S5P_VA_L2CC + L2X0_DATA_LATENCY_CTRL);
else if (soc_is_exynos4212())
__raw_writel(0x120, S5P_VA_L2CC + L2X0_DATA_LATENCY_CTRL);
/* L2X0 Prefetch Control */
__raw_writel(0x30000007, S5P_VA_L2CC + L2X0_PREFETCH_CTRL);

9
arch/arm/plat-s5p/cpu.c
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@ -33,6 +33,7 @@ static const char name_s5p6450[] = "S5P6450";
static const char name_s5pc100[] = "S5PC100";
static const char name_s5pv210[] = "S5PV210/S5PC110";
static const char name_exynos4210[] = "EXYNOS4210";
static const char name_exynos4212[] = "EXYNOS4212";
static struct cpu_table cpu_ids[] __initdata = {
{
@ -75,6 +76,14 @@ static struct cpu_table cpu_ids[] __initdata = {
.init_uarts = exynos4_init_uarts,
.init = exynos4_init,
.name = name_exynos4210,
}, {
.idcode = EXYNOS4212_CPU_ID,
.idmask = EXYNOS4_CPU_MASK,
.map_io = exynos4_map_io,
.init_clocks = exynos4_init_clocks,
.init_uarts = exynos4_init_uarts,
.init = exynos4_init,
.name = name_exynos4212,
},
};

3
arch/arm/plat-s5p/include/plat/exynos4.h
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@ -16,8 +16,7 @@ extern void exynos4_common_init_uarts(struct s3c2410_uartcfg *cfg, int no);
extern void exynos4_register_clocks(void);
extern void exynos4_setup_clocks(void);
#ifdef CONFIG_CPU_EXYNOS4210
#ifdef CONFIG_ARCH_EXYNOS4
extern int exynos4_init(void);
extern void exynos4_init_irq(void);
extern void exynos4_map_io(void);

8
arch/arm/plat-samsung/include/plat/cpu.h
View File

@ -39,6 +39,7 @@ extern unsigned long samsung_cpu_id;
#define S5PV210_CPU_MASK 0xFFFFF000
#define EXYNOS4210_CPU_ID 0x43210000
#define EXYNOS4212_CPU_ID 0x43220000
#define EXYNOS4_CPU_MASK 0xFFFE0000
#define IS_SAMSUNG_CPU(name, id, mask) \
@ -54,6 +55,7 @@ IS_SAMSUNG_CPU(s5p6450, S5P6450_CPU_ID, S5P64XX_CPU_MASK)
IS_SAMSUNG_CPU(s5pc100, S5PC100_CPU_ID, S5PC100_CPU_MASK)
IS_SAMSUNG_CPU(s5pv210, S5PV210_CPU_ID, S5PV210_CPU_MASK)
IS_SAMSUNG_CPU(exynos4210, EXYNOS4210_CPU_ID, EXYNOS4_CPU_MASK)
IS_SAMSUNG_CPU(exynos4212, EXYNOS4212_CPU_ID, EXYNOS4_CPU_MASK)
#if defined(CONFIG_CPU_S3C2410) || defined(CONFIG_CPU_S3C2412) || \
defined(CONFIG_CPU_S3C2416) || defined(CONFIG_CPU_S3C2440) || \
@ -100,6 +102,12 @@ IS_SAMSUNG_CPU(exynos4210, EXYNOS4210_CPU_ID, EXYNOS4_CPU_MASK)
# define soc_is_exynos4210() 0
#endif
#if defined(CONFIG_SOC_EXYNOS4212)
# define soc_is_exynos4212() is_samsung_exynos4212()
#else
# define soc_is_exynos4212() 0
#endif
#define EXYNOS4210_REV_0 (0x0)
#define EXYNOS4210_REV_1_0 (0x10)
#define EXYNOS4210_REV_1_1 (0x11)