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ARM: mach-shmobile: sh73a0 DMA Engine support for SY-DMAC
Add SY-DMAC support via shdma.c to the sh73a0 SoC including slave ids, platform data and clock bindings. Signed-off-by: Magnus Damm <damm@opensource.se> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This commit is contained in:
Magnus Damm
Paul Mundt
parent
d026e00e58
commit
681e1b3eeb
@ -266,7 +266,8 @@ enum { MSTP001,
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MSTP129, MSTP128, MSTP127, MSTP126, MSTP125, MSTP118, MSTP116, MSTP100,
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MSTP219,
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MSTP207, MSTP206, MSTP204, MSTP203, MSTP202, MSTP201, MSTP200,
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MSTP331, MSTP329, MSTP325, MSTP323, MSTP314, MSTP313, MSTP312, MSTP311,
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MSTP331, MSTP329, MSTP325, MSTP323, MSTP318,
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MSTP314, MSTP313, MSTP312, MSTP311,
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MSTP411, MSTP410, MSTP403,
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MSTP_NR };
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@ -295,6 +296,7 @@ static struct clk mstp_clks[MSTP_NR] = {
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[MSTP329] = MSTP(&r_clk, SMSTPCR3, 29, 0), /* CMT10 */
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[MSTP325] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR3, 25, 0), /* IrDA */
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[MSTP323] = MSTP(&div4_clks[DIV4_HP], SMSTPCR3, 23, 0), /* IIC1 */
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[MSTP318] = MSTP(&div4_clks[DIV4_HP], SMSTPCR3, 18, 0), /* SY-DMAC */
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[MSTP314] = MSTP(&div6_clks[DIV6_SDHI0], SMSTPCR3, 14, 0), /* SDHI0 */
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[MSTP313] = MSTP(&div6_clks[DIV6_SDHI1], SMSTPCR3, 13, 0), /* SDHI1 */
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[MSTP312] = MSTP(&div4_clks[DIV4_HP], SMSTPCR3, 12, 0), /* MMCIF0 */
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@ -347,6 +349,7 @@ static struct clk_lookup lookups[] = {
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CLKDEV_DEV_ID("sh_cmt.10", &mstp_clks[MSTP329]), /* CMT10 */
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CLKDEV_DEV_ID("sh_irda.0", &mstp_clks[MSTP325]), /* IrDA */
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CLKDEV_DEV_ID("i2c-sh_mobile.1", &mstp_clks[MSTP323]), /* I2C1 */
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CLKDEV_DEV_ID("sh-dma-engine.0", &mstp_clks[MSTP318]), /* SY-DMAC */
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CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[MSTP314]), /* SDHI0 */
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CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP313]), /* SDHI1 */
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CLKDEV_DEV_ID("sh_mmcif.0", &mstp_clks[MSTP312]), /* MMCIF0 */
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@ -463,5 +463,34 @@ enum {
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GPIO_FN_FSIAIBT_PU,
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GPIO_FN_FSIAISLD_PU,
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};
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/* DMA slave IDs */
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enum {
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SHDMA_SLAVE_SCIF0_TX,
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SHDMA_SLAVE_SCIF0_RX,
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SHDMA_SLAVE_SCIF1_TX,
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SHDMA_SLAVE_SCIF1_RX,
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SHDMA_SLAVE_SCIF2_TX,
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SHDMA_SLAVE_SCIF2_RX,
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SHDMA_SLAVE_SCIF3_TX,
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SHDMA_SLAVE_SCIF3_RX,
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SHDMA_SLAVE_SCIF4_TX,
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SHDMA_SLAVE_SCIF4_RX,
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SHDMA_SLAVE_SCIF5_TX,
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SHDMA_SLAVE_SCIF5_RX,
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SHDMA_SLAVE_SCIF6_TX,
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SHDMA_SLAVE_SCIF6_RX,
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SHDMA_SLAVE_SCIF7_TX,
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SHDMA_SLAVE_SCIF7_RX,
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SHDMA_SLAVE_SCIF8_TX,
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SHDMA_SLAVE_SCIF8_RX,
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SHDMA_SLAVE_SDHI0_TX,
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SHDMA_SLAVE_SDHI0_RX,
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SHDMA_SLAVE_SDHI1_TX,
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SHDMA_SLAVE_SDHI1_RX,
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SHDMA_SLAVE_SDHI2_TX,
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SHDMA_SLAVE_SDHI2_RX,
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SHDMA_SLAVE_MMCIF_TX,
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SHDMA_SLAVE_MMCIF_RX,
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};
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#endif /* __ASM_SH73A0_H__ */
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@ -27,9 +27,11 @@
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#include <linux/input.h>
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#include <linux/io.h>
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#include <linux/serial_sci.h>
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#include <linux/sh_dma.h>
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#include <linux/sh_intc.h>
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#include <linux/sh_timer.h>
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#include <mach/hardware.h>
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#include <mach/sh73a0.h>
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#include <asm/mach-types.h>
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#include <asm/mach/arch.h>
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@ -392,6 +394,242 @@ static struct platform_device i2c4_device = {
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.num_resources = ARRAY_SIZE(i2c4_resources),
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};
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/* Transmit sizes and respective CHCR register values */
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enum {
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XMIT_SZ_8BIT = 0,
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XMIT_SZ_16BIT = 1,
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XMIT_SZ_32BIT = 2,
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XMIT_SZ_64BIT = 7,
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XMIT_SZ_128BIT = 3,
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XMIT_SZ_256BIT = 4,
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XMIT_SZ_512BIT = 5,
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};
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/* log2(size / 8) - used to calculate number of transfers */
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#define TS_SHIFT { \
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[XMIT_SZ_8BIT] = 0, \
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[XMIT_SZ_16BIT] = 1, \
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[XMIT_SZ_32BIT] = 2, \
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[XMIT_SZ_64BIT] = 3, \
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[XMIT_SZ_128BIT] = 4, \
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[XMIT_SZ_256BIT] = 5, \
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[XMIT_SZ_512BIT] = 6, \
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}
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#define TS_INDEX2VAL(i) ((((i) & 3) << 3) | (((i) & 0xc) << (20 - 2)))
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#define CHCR_TX(xmit_sz) (DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL((xmit_sz)))
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#define CHCR_RX(xmit_sz) (DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL((xmit_sz)))
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static const struct sh_dmae_slave_config sh73a0_dmae_slaves[] = {
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{
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.slave_id = SHDMA_SLAVE_SCIF0_TX,
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.addr = 0xe6c40020,
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.chcr = CHCR_TX(XMIT_SZ_8BIT),
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.mid_rid = 0x21,
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}, {
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.slave_id = SHDMA_SLAVE_SCIF0_RX,
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.addr = 0xe6c40024,
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.chcr = CHCR_RX(XMIT_SZ_8BIT),
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.mid_rid = 0x22,
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}, {
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.slave_id = SHDMA_SLAVE_SCIF1_TX,
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.addr = 0xe6c50020,
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.chcr = CHCR_TX(XMIT_SZ_8BIT),
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.mid_rid = 0x25,
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}, {
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.slave_id = SHDMA_SLAVE_SCIF1_RX,
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.addr = 0xe6c50024,
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.chcr = CHCR_RX(XMIT_SZ_8BIT),
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.mid_rid = 0x26,
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}, {
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.slave_id = SHDMA_SLAVE_SCIF2_TX,
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.addr = 0xe6c60020,
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.chcr = CHCR_TX(XMIT_SZ_8BIT),
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.mid_rid = 0x29,
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}, {
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.slave_id = SHDMA_SLAVE_SCIF2_RX,
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.addr = 0xe6c60024,
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.chcr = CHCR_RX(XMIT_SZ_8BIT),
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.mid_rid = 0x2a,
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}, {
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.slave_id = SHDMA_SLAVE_SCIF3_TX,
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.addr = 0xe6c70020,
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.chcr = CHCR_TX(XMIT_SZ_8BIT),
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.mid_rid = 0x2d,
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}, {
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.slave_id = SHDMA_SLAVE_SCIF3_RX,
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.addr = 0xe6c70024,
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.chcr = CHCR_RX(XMIT_SZ_8BIT),
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.mid_rid = 0x2e,
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}, {
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.slave_id = SHDMA_SLAVE_SCIF4_TX,
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.addr = 0xe6c80020,
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.chcr = CHCR_TX(XMIT_SZ_8BIT),
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.mid_rid = 0x39,
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}, {
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.slave_id = SHDMA_SLAVE_SCIF4_RX,
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.addr = 0xe6c80024,
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.chcr = CHCR_RX(XMIT_SZ_8BIT),
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.mid_rid = 0x3a,
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}, {
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.slave_id = SHDMA_SLAVE_SCIF5_TX,
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.addr = 0xe6cb0020,
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.chcr = CHCR_TX(XMIT_SZ_8BIT),
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.mid_rid = 0x35,
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}, {
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.slave_id = SHDMA_SLAVE_SCIF5_RX,
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.addr = 0xe6cb0024,
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.chcr = CHCR_RX(XMIT_SZ_8BIT),
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.mid_rid = 0x36,
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}, {
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.slave_id = SHDMA_SLAVE_SCIF6_TX,
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.addr = 0xe6cc0020,
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.chcr = CHCR_TX(XMIT_SZ_8BIT),
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.mid_rid = 0x1d,
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}, {
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.slave_id = SHDMA_SLAVE_SCIF6_RX,
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.addr = 0xe6cc0024,
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.chcr = CHCR_RX(XMIT_SZ_8BIT),
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.mid_rid = 0x1e,
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}, {
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.slave_id = SHDMA_SLAVE_SCIF7_TX,
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.addr = 0xe6cd0020,
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.chcr = CHCR_TX(XMIT_SZ_8BIT),
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.mid_rid = 0x19,
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}, {
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.slave_id = SHDMA_SLAVE_SCIF7_RX,
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.addr = 0xe6cd0024,
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.chcr = CHCR_RX(XMIT_SZ_8BIT),
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.mid_rid = 0x1a,
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}, {
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.slave_id = SHDMA_SLAVE_SCIF8_TX,
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.addr = 0xe6c30040,
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.chcr = CHCR_TX(XMIT_SZ_8BIT),
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.mid_rid = 0x3d,
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}, {
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.slave_id = SHDMA_SLAVE_SCIF8_RX,
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.addr = 0xe6c30060,
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.chcr = CHCR_RX(XMIT_SZ_8BIT),
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.mid_rid = 0x3e,
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}, {
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.slave_id = SHDMA_SLAVE_SDHI0_TX,
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.addr = 0xee100030,
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.chcr = CHCR_TX(XMIT_SZ_16BIT),
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.mid_rid = 0xc1,
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}, {
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.slave_id = SHDMA_SLAVE_SDHI0_RX,
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.addr = 0xee100030,
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.chcr = CHCR_RX(XMIT_SZ_16BIT),
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.mid_rid = 0xc2,
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}, {
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.slave_id = SHDMA_SLAVE_SDHI1_TX,
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.addr = 0xee120030,
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.chcr = CHCR_TX(XMIT_SZ_16BIT),
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.mid_rid = 0xc9,
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}, {
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.slave_id = SHDMA_SLAVE_SDHI1_RX,
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.addr = 0xee120030,
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.chcr = CHCR_RX(XMIT_SZ_16BIT),
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.mid_rid = 0xca,
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}, {
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.slave_id = SHDMA_SLAVE_SDHI2_TX,
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.addr = 0xee140030,
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.chcr = CHCR_TX(XMIT_SZ_16BIT),
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.mid_rid = 0xcd,
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}, {
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.slave_id = SHDMA_SLAVE_SDHI2_RX,
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.addr = 0xee140030,
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.chcr = CHCR_RX(XMIT_SZ_16BIT),
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.mid_rid = 0xce,
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}, {
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.slave_id = SHDMA_SLAVE_MMCIF_TX,
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.addr = 0xe6bd0034,
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.chcr = CHCR_TX(XMIT_SZ_32BIT),
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.mid_rid = 0xd1,
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}, {
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.slave_id = SHDMA_SLAVE_MMCIF_RX,
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.addr = 0xe6bd0034,
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.chcr = CHCR_RX(XMIT_SZ_32BIT),
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.mid_rid = 0xd2,
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},
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};
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#define DMAE_CHANNEL(_offset) \
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{ \
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.offset = _offset - 0x20, \
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.dmars = _offset - 0x20 + 0x40, \
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}
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static const struct sh_dmae_channel sh73a0_dmae_channels[] = {
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DMAE_CHANNEL(0x8000),
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DMAE_CHANNEL(0x8080),
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DMAE_CHANNEL(0x8100),
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DMAE_CHANNEL(0x8180),
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DMAE_CHANNEL(0x8200),
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DMAE_CHANNEL(0x8280),
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DMAE_CHANNEL(0x8300),
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DMAE_CHANNEL(0x8380),
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DMAE_CHANNEL(0x8400),
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DMAE_CHANNEL(0x8480),
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DMAE_CHANNEL(0x8500),
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DMAE_CHANNEL(0x8580),
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DMAE_CHANNEL(0x8600),
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DMAE_CHANNEL(0x8680),
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DMAE_CHANNEL(0x8700),
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DMAE_CHANNEL(0x8780),
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DMAE_CHANNEL(0x8800),
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DMAE_CHANNEL(0x8880),
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DMAE_CHANNEL(0x8900),
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DMAE_CHANNEL(0x8980),
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};
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static const unsigned int ts_shift[] = TS_SHIFT;
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static struct sh_dmae_pdata sh73a0_dmae_platform_data = {
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.slave = sh73a0_dmae_slaves,
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.slave_num = ARRAY_SIZE(sh73a0_dmae_slaves),
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.channel = sh73a0_dmae_channels,
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.channel_num = ARRAY_SIZE(sh73a0_dmae_channels),
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.ts_low_shift = 3,
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.ts_low_mask = 0x18,
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.ts_high_shift = (20 - 2), /* 2 bits for shifted low TS */
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.ts_high_mask = 0x00300000,
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.ts_shift = ts_shift,
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.ts_shift_num = ARRAY_SIZE(ts_shift),
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.dmaor_init = DMAOR_DME,
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};
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static struct resource sh73a0_dmae_resources[] = {
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{
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/* Registers including DMAOR and channels including DMARSx */
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.start = 0xfe000020,
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.end = 0xfe008a00 - 1,
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.flags = IORESOURCE_MEM,
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},
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{
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/* DMA error IRQ */
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.start = gic_spi(129),
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.end = gic_spi(129),
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.flags = IORESOURCE_IRQ,
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},
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{
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/* IRQ for channels 0-19 */
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.start = gic_spi(109),
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.end = gic_spi(128),
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct platform_device dma0_device = {
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.name = "sh-dma-engine",
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.id = 0,
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.resource = sh73a0_dmae_resources,
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.num_resources = ARRAY_SIZE(sh73a0_dmae_resources),
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.dev = {
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.platform_data = &sh73a0_dmae_platform_data,
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},
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};
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static struct platform_device *sh73a0_early_devices[] __initdata = {
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&scif0_device,
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&scif1_device,
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@ -413,10 +651,16 @@ static struct platform_device *sh73a0_late_devices[] __initdata = {
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&i2c2_device,
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&i2c3_device,
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&i2c4_device,
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&dma0_device,
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};
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#define SRCR2 0xe61580b0
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void __init sh73a0_add_standard_devices(void)
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{
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/* Clear software reset bit on SY-DMAC module */
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__raw_writel(__raw_readl(SRCR2) & ~(1 << 18), SRCR2);
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platform_add_devices(sh73a0_early_devices,
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ARRAY_SIZE(sh73a0_early_devices));
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platform_add_devices(sh73a0_late_devices,
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