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phy: qcom: qmp-pcie: refactor clock register code
The PCIe Gen4x2 PHY found in the SM8[456]50 SoCs have a second clock, in order to expose it, split the current clock registering in two parts: - CCF clock registering - DT clock registering Keep the of_clk_add_hw_provider/devm_add_action_or_reset to keep compatibility with the legacy subnode bindings. Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20240322-topic-sm8x50-upstream-pcie-1-phy-aux-clk-v2-2-3ec0a966d52f@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
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@ -3664,7 +3664,7 @@ static int phy_pipe_clk_register(struct qmp_pcie *qmp, struct device_node *np)
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struct clk_init_data init = { };
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int ret;
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ret = of_property_read_string(np, "clock-output-names", &init.name);
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ret = of_property_read_string_index(np, "clock-output-names", 0, &init.name);
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if (ret) {
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dev_err(qmp->dev, "%pOFn: No clock-output-names\n", np);
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return ret;
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@ -3683,11 +3683,18 @@ static int phy_pipe_clk_register(struct qmp_pcie *qmp, struct device_node *np)
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fixed->hw.init = &init;
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ret = devm_clk_hw_register(qmp->dev, &fixed->hw);
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return devm_clk_hw_register(qmp->dev, &fixed->hw);
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}
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static int qmp_pcie_register_clocks(struct qmp_pcie *qmp, struct device_node *np)
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{
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int ret;
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ret = phy_pipe_clk_register(qmp, np);
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if (ret)
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return ret;
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ret = of_clk_add_hw_provider(np, of_clk_hw_simple_get, &fixed->hw);
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ret = of_clk_add_hw_provider(np, of_clk_hw_simple_get, &qmp->pipe_clk_fixed.hw);
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if (ret)
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return ret;
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@ -3899,7 +3906,7 @@ static int qmp_pcie_probe(struct platform_device *pdev)
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if (ret)
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goto err_node_put;
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ret = phy_pipe_clk_register(qmp, np);
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ret = qmp_pcie_register_clocks(qmp, np);
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if (ret)
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goto err_node_put;
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