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[MIPS] rbtx4938: misc cleanups
* Do not use non-standard I/O accessors, such as reg_rd08, etc. * Kill unnecessary wbflush() * Kill tx4938_mips.h * Kill unnecessary includes Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Atsushi Nemoto
Ralf Baechle
parent
1bd0962e3d
commit
66140c8e9f
@ -31,9 +31,7 @@
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* Support for TX4938 in 2.6 - Hiroshi DOYU <Hiroshi_DOYU@montavista.co.jp>
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*/
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#include <asm/mipsregs.h>
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#include <asm/system.h>
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#include <asm/tx4938/tx4938_mips.h>
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#include <linux/types>
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extern u8 txx9_sio_kdbg_rd(void);
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extern int txx9_sio_kdbg_wr( u8 ch );
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@ -13,13 +13,8 @@
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*/
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#include <linux/init.h>
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#include <linux/mm.h>
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#include <linux/sched.h>
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#include <linux/bootmem.h>
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#include <asm/addrspace.h>
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#include <asm/bootinfo.h>
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#include <asm/tx4938/tx4938.h>
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#include <linux/types.h>
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#include <linux/io.h>
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static unsigned int __init
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tx4938_process_sdccr(u64 * addr)
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@ -35,7 +30,7 @@ tx4938_process_sdccr(u64 * addr)
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unsigned int bc = 4;
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unsigned int msize = 0;
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val = (*((vu64 *) (addr)));
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val = ____raw_readq((void __iomem *)addr);
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/* MVMCP -- need #defs for these bits masks */
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sdccr_ce = ((val & (1 << 10)) >> 10);
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@ -67,24 +67,7 @@ IRQ Device
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63 RBTX4938-IOC/07 SWINT
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*/
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/types.h>
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#include <linux/mm.h>
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#include <linux/swap.h>
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#include <linux/ioport.h>
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#include <linux/sched.h>
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#include <linux/interrupt.h>
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#include <linux/pci.h>
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#include <linux/timex.h>
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#include <asm/bootinfo.h>
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#include <asm/page.h>
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#include <asm/io.h>
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#include <asm/irq.h>
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#include <asm/processor.h>
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#include <asm/reboot.h>
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#include <asm/time.h>
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#include <asm/wbflush.h>
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#include <linux/bootmem.h>
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#include <asm/tx4938/rbtx4938.h>
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static void toshiba_rbtx4938_irq_ioc_enable(unsigned int irq);
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@ -99,21 +82,16 @@ static struct irq_chip toshiba_rbtx4938_irq_ioc_type = {
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.unmask = toshiba_rbtx4938_irq_ioc_enable,
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};
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#define TOSHIBA_RBTX4938_IOC_INTR_ENAB 0xb7f02000
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#define TOSHIBA_RBTX4938_IOC_INTR_STAT 0xb7f0200a
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int
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toshiba_rbtx4938_irq_nested(int sw_irq)
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{
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u8 level3;
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level3 = reg_rd08(TOSHIBA_RBTX4938_IOC_INTR_STAT) & 0xff;
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if (level3) {
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level3 = readb(rbtx4938_imstat_addr);
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if (level3)
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/* must use fls so onboard ATA has priority */
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sw_irq = TOSHIBA_RBTX4938_IRQ_IOC_BEG + fls(level3) - 1;
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}
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wbflush();
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return sw_irq;
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}
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@ -144,25 +122,23 @@ toshiba_rbtx4938_irq_ioc_init(void)
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static void
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toshiba_rbtx4938_irq_ioc_enable(unsigned int irq)
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{
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volatile unsigned char v;
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unsigned char v;
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v = TX4938_RD08(TOSHIBA_RBTX4938_IOC_INTR_ENAB);
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v = readb(rbtx4938_imask_addr);
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v |= (1 << (irq - TOSHIBA_RBTX4938_IRQ_IOC_BEG));
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TX4938_WR08(TOSHIBA_RBTX4938_IOC_INTR_ENAB, v);
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writeb(v, rbtx4938_imask_addr);
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mmiowb();
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TX4938_RD08(TOSHIBA_RBTX4938_IOC_INTR_ENAB);
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}
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static void
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toshiba_rbtx4938_irq_ioc_disable(unsigned int irq)
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{
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volatile unsigned char v;
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unsigned char v;
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v = TX4938_RD08(TOSHIBA_RBTX4938_IOC_INTR_ENAB);
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v = readb(rbtx4938_imask_addr);
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v &= ~(1 << (irq - TOSHIBA_RBTX4938_IRQ_IOC_BEG));
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TX4938_WR08(TOSHIBA_RBTX4938_IOC_INTR_ENAB, v);
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writeb(v, rbtx4938_imask_addr);
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mmiowb();
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TX4938_RD08(TOSHIBA_RBTX4938_IOC_INTR_ENAB);
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}
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void __init arch_init_irq(void)
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@ -174,14 +150,12 @@ void __init arch_init_irq(void)
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/* all IRC interrupt mode are Low Active. */
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/* mask all IOC interrupts */
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*rbtx4938_imask_ptr = 0;
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writeb(0, rbtx4938_imask_addr);
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/* clear SoftInt interrupts */
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*rbtx4938_softint_ptr = 0;
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writeb(0, rbtx4938_softint_addr);
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tx4938_irq_init();
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toshiba_rbtx4938_irq_ioc_init();
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/* Onboard 10M Ether: High Active */
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set_irq_type(RBTX4938_IRQ_ETHER, IRQF_TRIGGER_HIGH);
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wbflush();
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}
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@ -23,7 +23,6 @@
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#include <linux/clk.h>
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#include <linux/gpio.h>
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#include <asm/wbflush.h>
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#include <asm/reboot.h>
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#include <asm/time.h>
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#include <asm/txx9tmr.h>
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@ -91,12 +90,11 @@ void rbtx4938_machine_restart(char *command)
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local_irq_disable();
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printk("Rebooting...");
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*rbtx4938_softresetlock_ptr = 1;
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*rbtx4938_sfvol_ptr = 1;
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*rbtx4938_softreset_ptr = 1;
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wbflush();
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while(1);
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writeb(1, rbtx4938_softresetlock_addr);
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writeb(1, rbtx4938_sfvol_addr);
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writeb(1, rbtx4938_softreset_addr);
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while(1)
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;
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}
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void __init
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@ -488,7 +486,7 @@ static int __init tx4938_pcibios_init(void)
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}
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/* Reset PCI Bus */
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*rbtx4938_pcireset_ptr = 0;
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writeb(0, rbtx4938_pcireset_addr);
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/* Reset PCIC */
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tx4938_ccfgptr->clkctr |= TX4938_CLKCTR_PCIRST;
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if (txboard_pci66_mode > 0)
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@ -496,8 +494,8 @@ static int __init tx4938_pcibios_init(void)
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mdelay(10);
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/* clear PCIC reset */
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tx4938_ccfgptr->clkctr &= ~TX4938_CLKCTR_PCIRST;
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*rbtx4938_pcireset_ptr = 1;
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wbflush();
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writeb(1, rbtx4938_pcireset_addr);
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mmiowb();
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tx4938_report_pcic_status1(tx4938_pcicptr);
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tx4938_report_pciclk();
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@ -505,15 +503,15 @@ static int __init tx4938_pcibios_init(void)
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if (txboard_pci66_mode == 0 &&
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txboard_pci66_check(&tx4938_pci_controller[0], 0, 0)) {
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/* Reset PCI Bus */
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*rbtx4938_pcireset_ptr = 0;
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writeb(0, rbtx4938_pcireset_addr);
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/* Reset PCIC */
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tx4938_ccfgptr->clkctr |= TX4938_CLKCTR_PCIRST;
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tx4938_pciclk66_setup();
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mdelay(10);
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/* clear PCIC reset */
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tx4938_ccfgptr->clkctr &= ~TX4938_CLKCTR_PCIRST;
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*rbtx4938_pcireset_ptr = 1;
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wbflush();
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writeb(1, rbtx4938_pcireset_addr);
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mmiowb();
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/* Reinitialize PCIC */
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tx4938_report_pciclk();
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tx4938_pcic_setup(tx4938_pcicptr, &tx4938_pci_controller[0], io_base[0], extarb);
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@ -774,8 +772,9 @@ void __init tx4938_board_setup(void)
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txx9_tmr_init(TX4938_TMR_REG(i) & 0xfffffffffULL);
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/* enable DMA */
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TX4938_WR64(0xff1fb150, TX4938_DMA_MCR_MSTEN);
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TX4938_WR64(0xff1fb950, TX4938_DMA_MCR_MSTEN);
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for (i = 0; i < 2; i++)
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____raw_writeq(TX4938_DMA_MCR_MSTEN,
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(void __iomem *)(TX4938_DMA_REG(i) + 0x50));
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/* PIO */
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__raw_writel(0, &tx4938_pioptr->maskcpu);
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@ -861,10 +860,6 @@ void __init plat_mem_setup(void)
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if (txx9_master_clock == 0)
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txx9_master_clock = 25000000; /* 25MHz */
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tx4938_board_setup();
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/* setup serial stuff */
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TX4938_WR(0xff1ff314, 0x00000000); /* h/w flow control off */
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TX4938_WR(0xff1ff414, 0x00000000); /* h/w flow control off */
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#ifndef CONFIG_PCI
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set_io_port_base(RBTX4938_ETHER_BASE);
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#endif
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@ -930,16 +925,16 @@ void __init plat_mem_setup(void)
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pcfg = tx4938_ccfgptr->pcfg; /* updated */
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/* fixup piosel */
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if ((pcfg & (TX4938_PCFG_ATA_SEL | TX4938_PCFG_NDF_SEL)) ==
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TX4938_PCFG_ATA_SEL) {
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*rbtx4938_piosel_ptr = (*rbtx4938_piosel_ptr & 0x03) | 0x04;
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}
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TX4938_PCFG_ATA_SEL)
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writeb((readb(rbtx4938_piosel_addr) & 0x03) | 0x04,
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rbtx4938_piosel_addr);
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else if ((pcfg & (TX4938_PCFG_ATA_SEL | TX4938_PCFG_NDF_SEL)) ==
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TX4938_PCFG_NDF_SEL) {
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*rbtx4938_piosel_ptr = (*rbtx4938_piosel_ptr & 0x03) | 0x08;
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}
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else {
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*rbtx4938_piosel_ptr &= ~(0x08 | 0x04);
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}
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TX4938_PCFG_NDF_SEL)
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writeb((readb(rbtx4938_piosel_addr) & 0x03) | 0x08,
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rbtx4938_piosel_addr);
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else
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writeb(readb(rbtx4938_piosel_addr) & ~(0x08 | 0x04),
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rbtx4938_piosel_addr);
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rbtx4938_fpga_resource.name = "FPGA Registers";
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rbtx4938_fpga_resource.start = CPHYSADDR(RBTX4938_FPGA_REG_ADDR);
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@ -948,17 +943,14 @@ void __init plat_mem_setup(void)
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if (request_resource(&iomem_resource, &rbtx4938_fpga_resource))
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printk("request resource for fpga failed\n");
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/* disable all OnBoard I/O interrupts */
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*rbtx4938_imask_ptr = 0;
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_machine_restart = rbtx4938_machine_restart;
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_machine_halt = rbtx4938_machine_halt;
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pm_power_off = rbtx4938_machine_power_off;
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*rbtx4938_led_ptr = 0xff;
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printk("RBTX4938 --- FPGA(Rev %02x)", *rbtx4938_fpga_rev_ptr);
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printk(" DIPSW:%02x,%02x\n",
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*rbtx4938_dipsw_ptr, *rbtx4938_bdipsw_ptr);
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writeb(0xff, rbtx4938_led_addr);
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printk(KERN_INFO "RBTX4938 --- FPGA(Rev %02x) DIPSW:%02x,%02x\n",
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readb(rbtx4938_fpga_rev_addr),
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readb(rbtx4938_dipsw_addr), readb(rbtx4938_bdipsw_addr));
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}
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static int __init rbtx4938_ne_init(void)
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@ -1000,12 +992,12 @@ static void rbtx4938_spi_gpio_set(struct gpio_chip *chip, unsigned int offset,
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u8 val;
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unsigned long flags;
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spin_lock_irqsave(&rbtx4938_spi_gpio_lock, flags);
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val = *rbtx4938_spics_ptr;
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val = readb(rbtx4938_spics_addr);
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if (value)
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val |= 1 << offset;
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else
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val &= ~(1 << offset);
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*rbtx4938_spics_ptr = val;
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writeb(val, rbtx4938_spics_addr);
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mmiowb();
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spin_unlock_irqrestore(&rbtx4938_spi_gpio_lock, flags);
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}
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@ -67,44 +67,26 @@
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#define RBTX4938_INTF_MODEM (1 << RBTX4938_INTB_MODEM)
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#define RBTX4938_INTF_SWINT (1 << RBTX4938_INTB_SWINT)
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#define rbtx4938_fpga_rev_ptr \
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((volatile unsigned char *)RBTX4938_FPGA_REV_ADDR)
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#define rbtx4938_led_ptr \
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((volatile unsigned char *)RBTX4938_LED_ADDR)
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#define rbtx4938_dipsw_ptr \
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((volatile unsigned char *)RBTX4938_DIPSW_ADDR)
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#define rbtx4938_bdipsw_ptr \
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((volatile unsigned char *)RBTX4938_BDIPSW_ADDR)
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#define rbtx4938_imask_ptr \
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((volatile unsigned char *)RBTX4938_IMASK_ADDR)
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#define rbtx4938_imask2_ptr \
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((volatile unsigned char *)RBTX4938_IMASK2_ADDR)
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#define rbtx4938_intpol_ptr \
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((volatile unsigned char *)RBTX4938_INTPOL_ADDR)
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#define rbtx4938_istat_ptr \
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((volatile unsigned char *)RBTX4938_ISTAT_ADDR)
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#define rbtx4938_istat2_ptr \
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((volatile unsigned char *)RBTX4938_ISTAT2_ADDR)
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#define rbtx4938_imstat_ptr \
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((volatile unsigned char *)RBTX4938_IMSTAT_ADDR)
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#define rbtx4938_imstat2_ptr \
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((volatile unsigned char *)RBTX4938_IMSTAT2_ADDR)
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#define rbtx4938_softint_ptr \
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((volatile unsigned char *)RBTX4938_SOFTINT_ADDR)
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#define rbtx4938_piosel_ptr \
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((volatile unsigned char *)RBTX4938_PIOSEL_ADDR)
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#define rbtx4938_spics_ptr \
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((volatile unsigned char *)RBTX4938_SPICS_ADDR)
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#define rbtx4938_sfpwr_ptr \
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((volatile unsigned char *)RBTX4938_SFPWR_ADDR)
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#define rbtx4938_sfvol_ptr \
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((volatile unsigned char *)RBTX4938_SFVOL_ADDR)
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#define rbtx4938_softreset_ptr \
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((volatile unsigned char *)RBTX4938_SOFTRESET_ADDR)
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#define rbtx4938_softresetlock_ptr \
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((volatile unsigned char *)RBTX4938_SOFTRESETLOCK_ADDR)
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#define rbtx4938_pcireset_ptr \
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((volatile unsigned char *)RBTX4938_PCIRESET_ADDR)
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#define rbtx4938_fpga_rev_addr ((__u8 __iomem *)RBTX4938_FPGA_REV_ADDR)
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#define rbtx4938_led_addr ((__u8 __iomem *)RBTX4938_LED_ADDR)
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#define rbtx4938_dipsw_addr ((__u8 __iomem *)RBTX4938_DIPSW_ADDR)
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#define rbtx4938_bdipsw_addr ((__u8 __iomem *)RBTX4938_BDIPSW_ADDR)
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#define rbtx4938_imask_addr ((__u8 __iomem *)RBTX4938_IMASK_ADDR)
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#define rbtx4938_imask2_addr ((__u8 __iomem *)RBTX4938_IMASK2_ADDR)
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#define rbtx4938_intpol_addr ((__u8 __iomem *)RBTX4938_INTPOL_ADDR)
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#define rbtx4938_istat_addr ((__u8 __iomem *)RBTX4938_ISTAT_ADDR)
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#define rbtx4938_istat2_addr ((__u8 __iomem *)RBTX4938_ISTAT2_ADDR)
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#define rbtx4938_imstat_addr ((__u8 __iomem *)RBTX4938_IMSTAT_ADDR)
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#define rbtx4938_imstat2_addr ((__u8 __iomem *)RBTX4938_IMSTAT2_ADDR)
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#define rbtx4938_softint_addr ((__u8 __iomem *)RBTX4938_SOFTINT_ADDR)
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#define rbtx4938_piosel_addr ((__u8 __iomem *)RBTX4938_PIOSEL_ADDR)
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#define rbtx4938_spics_addr ((__u8 __iomem *)RBTX4938_SPICS_ADDR)
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#define rbtx4938_sfpwr_addr ((__u8 __iomem *)RBTX4938_SFPWR_ADDR)
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#define rbtx4938_sfvol_addr ((__u8 __iomem *)RBTX4938_SFVOL_ADDR)
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#define rbtx4938_softreset_addr ((__u8 __iomem *)RBTX4938_SOFTRESET_ADDR)
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#define rbtx4938_softresetlock_addr \
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((__u8 __iomem *)RBTX4938_SOFTRESETLOCK_ADDR)
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#define rbtx4938_pcireset_addr ((__u8 __iomem *)RBTX4938_PCIRESET_ADDR)
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/*
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* IRQ mappings
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@ -13,8 +13,6 @@
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#ifndef __ASM_TX_BOARDS_TX4938_H
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#define __ASM_TX_BOARDS_TX4938_H
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#include <asm/tx4938/tx4938_mips.h>
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#define tx4938_read_nfmc(addr) (*(volatile unsigned int *)(addr))
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#define tx4938_write_nfmc(b, addr) (*(volatile unsigned int *)(addr)) = (b)
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@ -54,28 +52,6 @@
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#define TX4938_ACLC_REG (TX4938_REG_BASE + 0xf700)
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#define TX4938_SPI_REG (TX4938_REG_BASE + 0xf800)
|
||||
|
||||
#ifndef _LANGUAGE_ASSEMBLY
|
||||
#include <asm/byteorder.h>
|
||||
|
||||
#define TX4938_MKA(x) ((u32)( ((u32)(TX4938_REG_BASE)) | ((u32)(x)) ))
|
||||
|
||||
#define TX4938_RD08( reg ) (*(vu08*)(reg))
|
||||
#define TX4938_WR08( reg, val ) ((*(vu08*)(reg))=(val))
|
||||
|
||||
#define TX4938_RD16( reg ) (*(vu16*)(reg))
|
||||
#define TX4938_WR16( reg, val ) ((*(vu16*)(reg))=(val))
|
||||
|
||||
#define TX4938_RD32( reg ) (*(vu32*)(reg))
|
||||
#define TX4938_WR32( reg, val ) ((*(vu32*)(reg))=(val))
|
||||
|
||||
#define TX4938_RD64( reg ) (*(vu64*)(reg))
|
||||
#define TX4938_WR64( reg, val ) ((*(vu64*)(reg))=(val))
|
||||
|
||||
#define TX4938_RD( reg ) TX4938_RD32( reg )
|
||||
#define TX4938_WR( reg, val ) TX4938_WR32( reg, val )
|
||||
|
||||
#endif /* !__ASSEMBLY__ */
|
||||
|
||||
#ifdef __ASSEMBLY__
|
||||
#define _CONST64(c) c
|
||||
#else
|
||||
|
||||
@ -1,54 +0,0 @@
|
||||
/*
|
||||
* linux/include/asm-mips/tx4938/tx4938_mips.h
|
||||
* Generic bitmask definitions
|
||||
*
|
||||
* 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the
|
||||
* terms of the GNU General Public License version 2. This program is
|
||||
* licensed "as is" without any warranty of any kind, whether express
|
||||
* or implied.
|
||||
*
|
||||
* Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com)
|
||||
*/
|
||||
|
||||
#ifndef TX4938_TX4938_MIPS_H
|
||||
#define TX4938_TX4938_MIPS_H
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
#define reg_rd08(r) ((u8 )(*((vu8 *)(r))))
|
||||
#define reg_rd16(r) ((u16)(*((vu16*)(r))))
|
||||
#define reg_rd32(r) ((u32)(*((vu32*)(r))))
|
||||
#define reg_rd64(r) ((u64)(*((vu64*)(r))))
|
||||
|
||||
#define reg_wr08(r, v) ((*((vu8 *)(r)))=((u8 )(v)))
|
||||
#define reg_wr16(r, v) ((*((vu16*)(r)))=((u16)(v)))
|
||||
#define reg_wr32(r, v) ((*((vu32*)(r)))=((u32)(v)))
|
||||
#define reg_wr64(r, v) ((*((vu64*)(r)))=((u64)(v)))
|
||||
|
||||
typedef volatile __signed char vs8;
|
||||
typedef volatile unsigned char vu8;
|
||||
|
||||
typedef volatile __signed short vs16;
|
||||
typedef volatile unsigned short vu16;
|
||||
|
||||
typedef volatile __signed int vs32;
|
||||
typedef volatile unsigned int vu32;
|
||||
|
||||
typedef s8 s08;
|
||||
typedef vs8 vs08;
|
||||
|
||||
typedef u8 u08;
|
||||
typedef vu8 vu08;
|
||||
|
||||
#if (_MIPS_SZLONG == 64)
|
||||
|
||||
typedef volatile __signed__ long vs64;
|
||||
typedef volatile unsigned long vu64;
|
||||
|
||||
#else
|
||||
|
||||
typedef volatile __signed__ long long vs64;
|
||||
typedef volatile unsigned long long vu64;
|
||||
|
||||
#endif
|
||||
#endif
|
||||
#endif
|
||||
Loading…
Reference in New Issue
Block a user