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Merge branch 'topic/xilinx' into for-linus

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This commit is contained in:
Vinod Koul 2018-12-31 19:32:32 +05:30
commit 660611827c
2 changed files with 25 additions and 21 deletions
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44
drivers/dma/xilinx/xilinx_dma.c
View File

@ -190,6 +190,8 @@
/* AXI CDMA Specific Masks */ /* AXI CDMA Specific Masks */
#define XILINX_CDMA_CR_SGMODE BIT(3) #define XILINX_CDMA_CR_SGMODE BIT(3)
#define xilinx_prep_dma_addr_t(addr) \
((dma_addr_t)((u64)addr##_##msb << 32 | (addr)))
/** /**
* struct xilinx_vdma_desc_hw - Hardware Descriptor * struct xilinx_vdma_desc_hw - Hardware Descriptor
* @next_desc: Next Descriptor Pointer @0x00 * @next_desc: Next Descriptor Pointer @0x00
@ -887,6 +889,24 @@ static int xilinx_dma_alloc_chan_resources(struct dma_chan *dchan)
chan->id); chan->id);
return -ENOMEM; return -ENOMEM;
} }
/*
* For cyclic DMA mode we need to program the tail Descriptor
* register with a value which is not a part of the BD chain
* so allocating a desc segment during channel allocation for
* programming tail descriptor.
*/
chan->cyclic_seg_v = dma_zalloc_coherent(chan->dev,
sizeof(*chan->cyclic_seg_v),
&chan->cyclic_seg_p, GFP_KERNEL);
if (!chan->cyclic_seg_v) {
dev_err(chan->dev,
"unable to allocate desc segment for cyclic DMA\n");
dma_free_coherent(chan->dev, sizeof(*chan->seg_v) *
XILINX_DMA_NUM_DESCS, chan->seg_v,
chan->seg_p);
return -ENOMEM;
}
chan->cyclic_seg_v->phys = chan->cyclic_seg_p;
for (i = 0; i < XILINX_DMA_NUM_DESCS; i++) { for (i = 0; i < XILINX_DMA_NUM_DESCS; i++) {
chan->seg_v[i].hw.next_desc = chan->seg_v[i].hw.next_desc =
@ -922,24 +942,6 @@ static int xilinx_dma_alloc_chan_resources(struct dma_chan *dchan)
return -ENOMEM; return -ENOMEM;
} }
if (chan->xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA) {
/*
* For cyclic DMA mode we need to program the tail Descriptor
* register with a value which is not a part of the BD chain
* so allocating a desc segment during channel allocation for
* programming tail descriptor.
*/
chan->cyclic_seg_v = dma_zalloc_coherent(chan->dev,
sizeof(*chan->cyclic_seg_v),
&chan->cyclic_seg_p, GFP_KERNEL);
if (!chan->cyclic_seg_v) {
dev_err(chan->dev,
"unable to allocate desc segment for cyclic DMA\n");
return -ENOMEM;
}
chan->cyclic_seg_v->phys = chan->cyclic_seg_p;
}
dma_cookie_init(dchan); dma_cookie_init(dchan);
if (chan->xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA) { if (chan->xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA) {
@ -1245,8 +1247,10 @@ static void xilinx_cdma_start_transfer(struct xilinx_dma_chan *chan)
hw = &segment->hw; hw = &segment->hw;
xilinx_write(chan, XILINX_CDMA_REG_SRCADDR, hw->src_addr); xilinx_write(chan, XILINX_CDMA_REG_SRCADDR,
xilinx_write(chan, XILINX_CDMA_REG_DSTADDR, hw->dest_addr); xilinx_prep_dma_addr_t(hw->src_addr));
xilinx_write(chan, XILINX_CDMA_REG_DSTADDR,
xilinx_prep_dma_addr_t(hw->dest_addr));
/* Start the transfer */ /* Start the transfer */
dma_ctrl_write(chan, XILINX_DMA_REG_BTT, dma_ctrl_write(chan, XILINX_DMA_REG_BTT,

2
drivers/dma/xilinx/zynqmp_dma.c
View File

@ -163,7 +163,7 @@ struct zynqmp_dma_desc_ll {
u32 ctrl; u32 ctrl;
u64 nxtdscraddr; u64 nxtdscraddr;
u64 rsvd; u64 rsvd;
}; __aligned(64) };
/** /**
* struct zynqmp_dma_desc_sw - Per Transaction structure * struct zynqmp_dma_desc_sw - Per Transaction structure