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Merge branch 'topic/xilinx' into for-linus
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commit
660611827c
@ -190,6 +190,8 @@
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/* AXI CDMA Specific Masks */
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#define XILINX_CDMA_CR_SGMODE BIT(3)
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#define xilinx_prep_dma_addr_t(addr) \
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((dma_addr_t)((u64)addr##_##msb << 32 | (addr)))
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/**
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* struct xilinx_vdma_desc_hw - Hardware Descriptor
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* @next_desc: Next Descriptor Pointer @0x00
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@ -887,6 +889,24 @@ static int xilinx_dma_alloc_chan_resources(struct dma_chan *dchan)
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chan->id);
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return -ENOMEM;
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}
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/*
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* For cyclic DMA mode we need to program the tail Descriptor
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* register with a value which is not a part of the BD chain
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* so allocating a desc segment during channel allocation for
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* programming tail descriptor.
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*/
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chan->cyclic_seg_v = dma_zalloc_coherent(chan->dev,
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sizeof(*chan->cyclic_seg_v),
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&chan->cyclic_seg_p, GFP_KERNEL);
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if (!chan->cyclic_seg_v) {
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dev_err(chan->dev,
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"unable to allocate desc segment for cyclic DMA\n");
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dma_free_coherent(chan->dev, sizeof(*chan->seg_v) *
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XILINX_DMA_NUM_DESCS, chan->seg_v,
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chan->seg_p);
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return -ENOMEM;
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}
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chan->cyclic_seg_v->phys = chan->cyclic_seg_p;
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for (i = 0; i < XILINX_DMA_NUM_DESCS; i++) {
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chan->seg_v[i].hw.next_desc =
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@ -922,24 +942,6 @@ static int xilinx_dma_alloc_chan_resources(struct dma_chan *dchan)
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return -ENOMEM;
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}
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if (chan->xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA) {
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/*
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* For cyclic DMA mode we need to program the tail Descriptor
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* register with a value which is not a part of the BD chain
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* so allocating a desc segment during channel allocation for
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* programming tail descriptor.
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*/
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chan->cyclic_seg_v = dma_zalloc_coherent(chan->dev,
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sizeof(*chan->cyclic_seg_v),
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&chan->cyclic_seg_p, GFP_KERNEL);
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if (!chan->cyclic_seg_v) {
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dev_err(chan->dev,
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"unable to allocate desc segment for cyclic DMA\n");
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return -ENOMEM;
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}
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chan->cyclic_seg_v->phys = chan->cyclic_seg_p;
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}
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dma_cookie_init(dchan);
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if (chan->xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA) {
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@ -1245,8 +1247,10 @@ static void xilinx_cdma_start_transfer(struct xilinx_dma_chan *chan)
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hw = &segment->hw;
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xilinx_write(chan, XILINX_CDMA_REG_SRCADDR, hw->src_addr);
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xilinx_write(chan, XILINX_CDMA_REG_DSTADDR, hw->dest_addr);
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xilinx_write(chan, XILINX_CDMA_REG_SRCADDR,
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xilinx_prep_dma_addr_t(hw->src_addr));
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xilinx_write(chan, XILINX_CDMA_REG_DSTADDR,
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xilinx_prep_dma_addr_t(hw->dest_addr));
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/* Start the transfer */
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dma_ctrl_write(chan, XILINX_DMA_REG_BTT,
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@ -163,7 +163,7 @@ struct zynqmp_dma_desc_ll {
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u32 ctrl;
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u64 nxtdscraddr;
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u64 rsvd;
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}; __aligned(64)
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};
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/**
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* struct zynqmp_dma_desc_sw - Per Transaction structure
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