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spi: fsl_spi: Convert to transfer_one
Let the core handle all the chipselect bakery and replace transfer_one_message() by transfer_one() and prepare_message(). At the time being, there is fsl_spi_cs_control() to handle chipselects. That function handles both GPIO and non-GPIO chipselects. The GPIO chipselects will now be handled by the core directly, so only handle non-GPIO chipselects and hook it to ->set_cs Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu> Link: https://lore.kernel.org/r/753266abafe81722d86c3ddb8bac8ef1cb00fe8c.1660829841.git.christophe.leroy@csgroup.eu Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Christophe Leroy
Mark Brown
parent
83e5335bf5
commit
64ca1a034f
@ -111,32 +111,6 @@ static void fsl_spi_change_mode(struct spi_device *spi)
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local_irq_restore(flags);
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}
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static void fsl_spi_chipselect(struct spi_device *spi, int value)
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{
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struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master);
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struct fsl_spi_platform_data *pdata;
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struct spi_mpc8xxx_cs *cs = spi->controller_state;
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pdata = spi->dev.parent->parent->platform_data;
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if (value == BITBANG_CS_INACTIVE) {
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if (pdata->cs_control)
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pdata->cs_control(spi, false);
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}
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if (value == BITBANG_CS_ACTIVE) {
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mpc8xxx_spi->rx_shift = cs->rx_shift;
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mpc8xxx_spi->tx_shift = cs->tx_shift;
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mpc8xxx_spi->get_rx = cs->get_rx;
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mpc8xxx_spi->get_tx = cs->get_tx;
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fsl_spi_change_mode(spi);
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if (pdata->cs_control)
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pdata->cs_control(spi, true);
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}
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}
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static void fsl_spi_qe_cpu_set_shifts(u32 *rx_shift, u32 *tx_shift,
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int bits_per_word, int msb_first)
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{
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@ -354,15 +328,11 @@ static int fsl_spi_bufs(struct spi_device *spi, struct spi_transfer *t,
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return mpc8xxx_spi->count;
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}
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static int fsl_spi_do_one_msg(struct spi_master *master,
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struct spi_message *m)
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static int fsl_spi_prepare_message(struct spi_controller *ctlr,
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struct spi_message *m)
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{
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struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(master);
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struct spi_device *spi = m->spi;
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struct spi_transfer *t, *first;
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unsigned int cs_change;
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const int nsecs = 50;
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int status, last_bpw;
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struct mpc8xxx_spi *mpc8xxx_spi = spi_controller_get_devdata(ctlr);
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struct spi_transfer *t;
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/*
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* In CPU mode, optimize large byte transfers to use larger
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@ -378,64 +348,32 @@ static int fsl_spi_do_one_msg(struct spi_master *master,
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t->bits_per_word = 16;
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}
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}
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/* Don't allow changes if CS is active */
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cs_change = 1;
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list_for_each_entry(t, &m->transfers, transfer_list) {
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if (cs_change)
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first = t;
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cs_change = t->cs_change;
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if (first->speed_hz != t->speed_hz) {
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dev_err(&spi->dev,
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"speed_hz cannot change while CS is active\n");
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return -EINVAL;
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}
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}
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last_bpw = -1;
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cs_change = 1;
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status = -EINVAL;
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list_for_each_entry(t, &m->transfers, transfer_list) {
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if (cs_change || last_bpw != t->bits_per_word)
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status = fsl_spi_setup_transfer(spi, t);
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if (status < 0)
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break;
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last_bpw = t->bits_per_word;
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if (cs_change) {
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fsl_spi_chipselect(spi, BITBANG_CS_ACTIVE);
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ndelay(nsecs);
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}
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cs_change = t->cs_change;
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if (t->len)
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status = fsl_spi_bufs(spi, t, m->is_dma_mapped);
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if (status) {
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status = -EMSGSIZE;
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break;
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}
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m->actual_length += t->len;
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spi_transfer_delay_exec(t);
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if (cs_change) {
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ndelay(nsecs);
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fsl_spi_chipselect(spi, BITBANG_CS_INACTIVE);
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ndelay(nsecs);
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}
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}
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m->status = status;
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if (status || !cs_change) {
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ndelay(nsecs);
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fsl_spi_chipselect(spi, BITBANG_CS_INACTIVE);
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}
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fsl_spi_setup_transfer(spi, NULL);
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spi_finalize_current_message(master);
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return 0;
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}
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static int fsl_spi_transfer_one(struct spi_controller *controller,
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struct spi_device *spi,
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struct spi_transfer *t)
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{
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int status;
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status = fsl_spi_setup_transfer(spi, t);
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if (status < 0)
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return status;
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if (t->len)
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status = fsl_spi_bufs(spi, t, !!t->tx_dma || !!t->rx_dma);
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if (status > 0)
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return -EMSGSIZE;
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return status;
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}
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static int fsl_spi_unprepare_message(struct spi_controller *controller,
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struct spi_message *msg)
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{
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return fsl_spi_setup_transfer(msg->spi, NULL);
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}
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static int fsl_spi_setup(struct spi_device *spi)
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{
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struct mpc8xxx_spi *mpc8xxx_spi;
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@ -482,9 +420,6 @@ static int fsl_spi_setup(struct spi_device *spi)
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return retval;
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}
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/* Initialize chipselect - might be active for SPI_CS_HIGH mode */
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fsl_spi_chipselect(spi, BITBANG_CS_INACTIVE);
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return 0;
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}
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@ -557,9 +492,7 @@ static void fsl_spi_grlib_cs_control(struct spi_device *spi, bool on)
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u32 slvsel;
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u16 cs = spi->chip_select;
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if (spi->cs_gpiod) {
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gpiod_set_value(spi->cs_gpiod, on);
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} else if (cs < mpc8xxx_spi->native_chipselects) {
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if (cs < mpc8xxx_spi->native_chipselects) {
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slvsel = mpc8xxx_spi_read_reg(®_base->slvsel);
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slvsel = on ? (slvsel | (1 << cs)) : (slvsel & ~(1 << cs));
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mpc8xxx_spi_write_reg(®_base->slvsel, slvsel);
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@ -568,7 +501,6 @@ static void fsl_spi_grlib_cs_control(struct spi_device *spi, bool on)
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static void fsl_spi_grlib_probe(struct device *dev)
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{
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struct fsl_spi_platform_data *pdata = dev_get_platdata(dev);
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struct spi_master *master = dev_get_drvdata(dev);
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struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(master);
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struct fsl_spi_reg __iomem *reg_base = mpc8xxx_spi->reg_base;
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@ -588,7 +520,18 @@ static void fsl_spi_grlib_probe(struct device *dev)
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mpc8xxx_spi_write_reg(®_base->slvsel, 0xffffffff);
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}
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master->num_chipselect = mpc8xxx_spi->native_chipselects;
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pdata->cs_control = fsl_spi_grlib_cs_control;
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master->set_cs = fsl_spi_grlib_cs_control;
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}
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static void fsl_spi_cs_control(struct spi_device *spi, bool on)
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{
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struct device *dev = spi->dev.parent->parent;
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struct fsl_spi_platform_data *pdata = dev_get_platdata(dev);
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struct mpc8xxx_spi_probe_info *pinfo = to_of_pinfo(pdata);
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if (WARN_ON_ONCE(!pinfo->immr_spi_cs))
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return;
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iowrite32be(on ? 0 : SPI_BOOT_SEL_BIT, pinfo->immr_spi_cs);
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}
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static struct spi_master *fsl_spi_probe(struct device *dev,
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@ -613,8 +556,11 @@ static struct spi_master *fsl_spi_probe(struct device *dev,
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master->setup = fsl_spi_setup;
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master->cleanup = fsl_spi_cleanup;
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master->transfer_one_message = fsl_spi_do_one_msg;
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master->prepare_message = fsl_spi_prepare_message;
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master->transfer_one = fsl_spi_transfer_one;
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master->unprepare_message = fsl_spi_unprepare_message;
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master->use_gpio_descriptors = true;
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master->set_cs = fsl_spi_cs_control;
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mpc8xxx_spi = spi_master_get_devdata(master);
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mpc8xxx_spi->max_bits_per_word = 32;
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@ -688,21 +634,6 @@ err:
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return ERR_PTR(ret);
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}
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static void fsl_spi_cs_control(struct spi_device *spi, bool on)
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{
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if (spi->cs_gpiod) {
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gpiod_set_value(spi->cs_gpiod, on);
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} else {
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struct device *dev = spi->dev.parent->parent;
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struct fsl_spi_platform_data *pdata = dev_get_platdata(dev);
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struct mpc8xxx_spi_probe_info *pinfo = to_of_pinfo(pdata);
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if (WARN_ON_ONCE(!pinfo->immr_spi_cs))
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return;
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iowrite32be(on ? 0 : SPI_BOOT_SEL_BIT, pinfo->immr_spi_cs);
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}
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}
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static int of_fsl_spi_probe(struct platform_device *ofdev)
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{
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struct device *dev = &ofdev->dev;
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@ -744,12 +675,10 @@ static int of_fsl_spi_probe(struct platform_device *ofdev)
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ret = gpiod_count(dev, "cs");
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if (ret < 0)
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ret = 0;
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if (ret == 0 && !spisel_boot) {
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if (ret == 0 && !spisel_boot)
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pdata->max_chipselect = 1;
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} else {
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else
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pdata->max_chipselect = ret + spisel_boot;
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pdata->cs_control = fsl_spi_cs_control;
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}
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}
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ret = of_address_to_resource(np, 0, &mem);
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