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video: mmpdisp: add spi port in display controller
Add spi port support in mmp display controller. This port is from display controller and for panel usage. This driver implemented and registered as a spi master. Signed-off-by: Zhou Zhu <zzhu3@marvell.com> Acked-by: Haojian Zhuang <haojian.zhuang@gmail.com> Cc: Lisa Du <cldu@marvell.com> Cc: Guoqing Li <ligq@marvell.com> Cc: Florian Tobias Schandinat <FlorianSchandinat@gmx.de> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
This commit is contained in:
Zhou Zhu
Linus Torvalds
parent
3c76f15fd5
commit
641b4b1b6a
@ -9,4 +9,12 @@ config MMP_DISP_CONTROLLER
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this controller is used on Marvell PXA910,
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MMP2, MMP3, PXA988 chips
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config MMP_DISP_SPI
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bool "mmp display controller spi port"
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depends on MMP_DISP_CONTROLLER && SPI_MASTER
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default y
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help
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Marvell MMP display hw controller spi port support
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will register as a spi master for panel usage
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endif
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@ -1 +1,2 @@
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obj-$(CONFIG_MMP_DISP_CONTROLLER) += mmp_ctrl.o
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obj-$(CONFIG_MMP_DISP_SPI) += mmp_spi.o
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@ -535,6 +535,12 @@ static int mmphw_probe(struct platform_device *pdev)
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}
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}
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#ifdef CONFIG_MMP_DISP_SPI
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ret = lcd_spi_register(ctrl);
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if (ret < 0)
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goto failed_path_init;
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#endif
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dev_info(ctrl->dev, "device init done\n");
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return 0;
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@ -1967,4 +1967,8 @@ static inline struct lcd_regs *path_regs(struct mmp_path *path)
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return NULL;
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}
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}
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#ifdef CONFIG_MMP_DISP_SPI
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extern int lcd_spi_register(struct mmphw_ctrl *ctrl);
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#endif
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#endif /* _MMP_CTRL_H_ */
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180
drivers/video/mmp/hw/mmp_spi.c
Normal file
180
drivers/video/mmp/hw/mmp_spi.c
Normal file
@ -0,0 +1,180 @@
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/*
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* linux/drivers/video/mmp/hw/mmp_spi.c
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* using the spi in LCD controler for commands send
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*
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* Copyright (C) 2012 Marvell Technology Group Ltd.
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* Authors: Guoqing Li <ligq@marvell.com>
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* Lisa Du <cldu@marvell.com>
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* Zhou Zhu <zzhu3@marvell.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*
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*/
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#include <linux/errno.h>
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#include <linux/delay.h>
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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/spi/spi.h>
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#include "mmp_ctrl.h"
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/**
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* spi_write - write command to the SPI port
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* @data: can be 8/16/32-bit, MSB justified data to write.
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* @len: data length.
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*
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* Wait bus transfer complete IRQ.
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* The caller is expected to perform the necessary locking.
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*
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* Returns:
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* %-ETIMEDOUT timeout occurred
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* 0 success
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*/
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static inline int lcd_spi_write(struct spi_device *spi, u32 data)
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{
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int timeout = 100000, isr, ret = 0;
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u32 tmp;
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void *reg_base =
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*(void **)spi_master_get_devdata(spi->master);
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/* clear ISR */
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writel_relaxed(~SPI_IRQ_MASK, reg_base + SPU_IRQ_ISR);
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switch (spi->bits_per_word) {
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case 8:
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writel_relaxed((u8)data, reg_base + LCD_SPU_SPI_TXDATA);
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break;
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case 16:
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writel_relaxed((u16)data, reg_base + LCD_SPU_SPI_TXDATA);
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break;
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case 32:
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writel_relaxed((u32)data, reg_base + LCD_SPU_SPI_TXDATA);
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break;
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default:
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dev_err(&spi->dev, "Wrong spi bit length\n");
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}
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/* SPI start to send command */
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tmp = readl_relaxed(reg_base + LCD_SPU_SPI_CTRL);
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tmp &= ~CFG_SPI_START_MASK;
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tmp |= CFG_SPI_START(1);
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writel(tmp, reg_base + LCD_SPU_SPI_CTRL);
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isr = readl_relaxed(reg_base + SPU_IRQ_ISR);
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while (!(isr & SPI_IRQ_ENA_MASK)) {
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udelay(100);
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isr = readl_relaxed(reg_base + SPU_IRQ_ISR);
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if (!--timeout) {
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ret = -ETIMEDOUT;
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dev_err(&spi->dev, "spi cmd send time out\n");
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break;
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}
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}
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tmp = readl_relaxed(reg_base + LCD_SPU_SPI_CTRL);
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tmp &= ~CFG_SPI_START_MASK;
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tmp |= CFG_SPI_START(0);
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writel_relaxed(tmp, reg_base + LCD_SPU_SPI_CTRL);
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writel_relaxed(~SPI_IRQ_MASK, reg_base + SPU_IRQ_ISR);
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return ret;
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}
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static int lcd_spi_setup(struct spi_device *spi)
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{
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void *reg_base =
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*(void **)spi_master_get_devdata(spi->master);
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u32 tmp;
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tmp = CFG_SCLKCNT(16) |
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CFG_TXBITS(spi->bits_per_word) |
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CFG_SPI_SEL(1) | CFG_SPI_ENA(1) |
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CFG_SPI_3W4WB(1);
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writel(tmp, reg_base + LCD_SPU_SPI_CTRL);
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/*
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* After set mode it need a time to pull up the spi singals,
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* or it would cause the wrong waveform when send spi command,
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* especially on pxa910h
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*/
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tmp = readl_relaxed(reg_base + SPU_IOPAD_CONTROL);
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if ((tmp & CFG_IOPADMODE_MASK) != IOPAD_DUMB18SPI)
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writel_relaxed(IOPAD_DUMB18SPI |
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(tmp & ~CFG_IOPADMODE_MASK),
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reg_base + SPU_IOPAD_CONTROL);
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udelay(20);
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return 0;
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}
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static int lcd_spi_one_transfer(struct spi_device *spi, struct spi_message *m)
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{
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struct spi_transfer *t;
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int i;
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list_for_each_entry(t, &m->transfers, transfer_list) {
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switch (spi->bits_per_word) {
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case 8:
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for (i = 0; i < t->len; i++)
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lcd_spi_write(spi, ((u8 *)t->tx_buf)[i]);
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break;
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case 16:
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for (i = 0; i < t->len/2; i++)
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lcd_spi_write(spi, ((u16 *)t->tx_buf)[i]);
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break;
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case 32:
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for (i = 0; i < t->len/4; i++)
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lcd_spi_write(spi, ((u32 *)t->tx_buf)[i]);
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break;
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default:
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dev_err(&spi->dev, "Wrong spi bit length\n");
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}
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}
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m->status = 0;
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if (m->complete)
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m->complete(m->context);
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return 0;
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}
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int lcd_spi_register(struct mmphw_ctrl *ctrl)
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{
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struct spi_master *master;
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void **p_regbase;
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int err;
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master = spi_alloc_master(ctrl->dev, sizeof(void *));
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if (!master) {
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dev_err(ctrl->dev, "unable to allocate SPI master\n");
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return -ENOMEM;
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}
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p_regbase = spi_master_get_devdata(master);
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*p_regbase = ctrl->reg_base;
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/* set bus num to 5 to avoid conflict with other spi hosts */
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master->bus_num = 5;
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master->num_chipselect = 1;
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master->setup = lcd_spi_setup;
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master->transfer = lcd_spi_one_transfer;
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err = spi_register_master(master);
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if (err < 0) {
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dev_err(ctrl->dev, "unable to register SPI master\n");
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spi_master_put(master);
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return err;
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}
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dev_info(&master->dev, "registered\n");
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return 0;
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}
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