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Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/net into net

Browse Source 
Pull in 'net' to take in the bug fixes that didn't make it into
3.8-final.

Also, deal with the semantic conflict of the change made to
net/ipv6/xfrm6_policy.c   A missing rt6->n neighbour release
was added to 'net', but in 'net-next' we no longer cache the
neighbour entries in the ipv6 routes so that change is not
appropriate there.

Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
David S. Miller 2013-02-18 23:32:49 -05:00
commit 6338a53a2b
60 changed files with 753 additions and 627 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
Documentation/x86/boot.txt
View File

@ -390,6 +390,7 @@ Protocol: 2.00+
F Special (0xFF = undefined)
10 Reserved
11 Minimal Linux Bootloader <http://sebastian-plotz.blogspot.de>
12 OVMF UEFI virtualization stack
Please contact <hpa@zytor.com> if you need a bootloader ID
value assigned.

2
MAINTAINERS
View File

@ -7524,7 +7524,7 @@ S: Maintained
F: drivers/media/tuners/tea5767.*
TEAM DRIVER
M: Jiri Pirko <jpirko@redhat.com>
M: Jiri Pirko <jiri@resnulli.us>
L: netdev@vger.kernel.org
S: Supported
F: drivers/net/team/

8
arch/arm/include/asm/smp_scu.h
View File

@ -7,8 +7,14 @@
#ifndef __ASSEMBLER__
unsigned int scu_get_core_count(void __iomem *);
void scu_enable(void __iomem *);
int scu_power_mode(void __iomem *, unsigned int);
#ifdef CONFIG_SMP
void scu_enable(void __iomem *scu_base);
#else
static inline void scu_enable(void __iomem *scu_base) {}
#endif
#endif
#endif

2
arch/arm/kernel/smp_scu.c
View File

@ -75,7 +75,7 @@ void scu_enable(void __iomem *scu_base)
int scu_power_mode(void __iomem *scu_base, unsigned int mode)
{
unsigned int val;
int cpu = cpu_logical_map(smp_processor_id());
int cpu = MPIDR_AFFINITY_LEVEL(cpu_logical_map(smp_processor_id()), 0);
if (mode > 3 || mode == 1 || cpu > 3)
return -EINVAL;

3
arch/arm/mach-highbank/highbank.c
View File

@ -28,6 +28,7 @@
#include <asm/arch_timer.h>
#include <asm/cacheflush.h>
#include <asm/cputype.h>
#include <asm/smp_plat.h>
#include <asm/smp_twd.h>
#include <asm/hardware/arm_timer.h>
@ -59,7 +60,7 @@ static void __init highbank_scu_map_io(void)
void highbank_set_cpu_jump(int cpu, void *jump_addr)
{
cpu = cpu_logical_map(cpu);
cpu = MPIDR_AFFINITY_LEVEL(cpu_logical_map(cpu), 0);
writel(virt_to_phys(jump_addr), HB_JUMP_TABLE_VIRT(cpu));
__cpuc_flush_dcache_area(HB_JUMP_TABLE_VIRT(cpu), 16);
outer_clean_range(HB_JUMP_TABLE_PHYS(cpu),

4
arch/arm/mach-highbank/sysregs.h
View File

@ -37,7 +37,7 @@ extern void __iomem *sregs_base;
static inline void highbank_set_core_pwr(void)
{
int cpu = cpu_logical_map(smp_processor_id());
int cpu = MPIDR_AFFINITY_LEVEL(cpu_logical_map(smp_processor_id()), 0);
if (scu_base_addr)
scu_power_mode(scu_base_addr, SCU_PM_POWEROFF);
else
@ -46,7 +46,7 @@ static inline void highbank_set_core_pwr(void)
static inline void highbank_clear_core_pwr(void)
{
int cpu = cpu_logical_map(smp_processor_id());
int cpu = MPIDR_AFFINITY_LEVEL(cpu_logical_map(smp_processor_id()), 0);
if (scu_base_addr)
scu_power_mode(scu_base_addr, SCU_PM_NORMAL);
else

15
arch/arm/net/bpf_jit_32.c
View File

@ -341,10 +341,17 @@ static void emit_load_be16(u8 cond, u8 r_res, u8 r_addr, struct jit_ctx *ctx)
static inline void emit_swap16(u8 r_dst, u8 r_src, struct jit_ctx *ctx)
{
emit(ARM_LSL_R(ARM_R1, r_src, 8), ctx);
emit(ARM_ORR_S(r_dst, ARM_R1, r_src, SRTYPE_LSL, 8), ctx);
emit(ARM_LSL_I(r_dst, r_dst, 8), ctx);
emit(ARM_LSL_R(r_dst, r_dst, 8), ctx);
/* r_dst = (r_src << 8) | (r_src >> 8) */
emit(ARM_LSL_I(ARM_R1, r_src, 8), ctx);
emit(ARM_ORR_S(r_dst, ARM_R1, r_src, SRTYPE_LSR, 8), ctx);
/*
* we need to mask out the bits set in r_dst[23:16] due to
* the first shift instruction.
*
* note that 0x8ff is the encoded immediate 0x00ff0000.
*/
emit(ARM_BIC_I(r_dst, r_dst, 0x8ff), ctx);
}
#else /* ARMv6+ */

1
arch/m68k/include/asm/processor.h
View File

@ -130,7 +130,6 @@ extern int handle_kernel_fault(struct pt_regs *regs);
#define start_thread(_regs, _pc, _usp) \
do { \
(_regs)->pc = (_pc); \
((struct switch_stack *)(_regs))[-1].a6 = 0; \
setframeformat(_regs); \
if (current->mm) \
(_regs)->d5 = current->mm->start_data; \

3
arch/s390/kernel/time.c
View File

@ -120,6 +120,9 @@ static int s390_next_ktime(ktime_t expires,
nsecs = ktime_to_ns(ktime_add(timespec_to_ktime(ts), expires));
do_div(nsecs, 125);
S390_lowcore.clock_comparator = sched_clock_base_cc + (nsecs << 9);
/* Program the maximum value if we have an overflow (== year 2042) */
if (unlikely(S390_lowcore.clock_comparator < sched_clock_base_cc))
S390_lowcore.clock_comparator = -1ULL;
set_clock_comparator(S390_lowcore.clock_comparator);
return 0;
}

2
arch/tile/Kconfig
View File

@ -140,6 +140,8 @@ config ARCH_DEFCONFIG
source "init/Kconfig"
source "kernel/Kconfig.freezer"
menu "Tilera-specific configuration"
config NR_CPUS

6
arch/tile/include/asm/io.h
View File

@ -250,7 +250,9 @@ static inline void writeq(u64 val, unsigned long addr)
#define iowrite32 writel
#define iowrite64 writeq
static inline void memset_io(void *dst, int val, size_t len)
#if CHIP_HAS_MMIO() || defined(CONFIG_PCI)
static inline void memset_io(volatile void *dst, int val, size_t len)
{
int x;
BUG_ON((unsigned long)dst & 0x3);
@ -277,6 +279,8 @@ static inline void memcpy_toio(volatile void __iomem *dst, const void *src,
writel(*(u32 *)(src + x), dst + x);
}
#endif
/*
* The Tile architecture does not support IOPORT, even with PCI.
* Unfortunately we can't yet simply not declare these methods,

32
arch/tile/include/asm/irqflags.h
View File

@ -18,32 +18,20 @@
#include <arch/interrupts.h>
#include <arch/chip.h>
#if !defined(__tilegx__) && defined(__ASSEMBLY__)
/*
* The set of interrupts we want to allow when interrupts are nominally
* disabled. The remainder are effectively "NMI" interrupts from
* the point of view of the generic Linux code. Note that synchronous
* interrupts (aka "non-queued") are not blocked by the mask in any case.
*/
#if CHIP_HAS_AUX_PERF_COUNTERS()
#define LINUX_MASKABLE_INTERRUPTS_HI \
(~(INT_MASK_HI(INT_PERF_COUNT) | INT_MASK_HI(INT_AUX_PERF_COUNT)))
#else
#define LINUX_MASKABLE_INTERRUPTS_HI \
(~(INT_MASK_HI(INT_PERF_COUNT)))
#endif
#else
#if CHIP_HAS_AUX_PERF_COUNTERS()
#define LINUX_MASKABLE_INTERRUPTS \
(~(INT_MASK(INT_PERF_COUNT) | INT_MASK(INT_AUX_PERF_COUNT)))
#else
#define LINUX_MASKABLE_INTERRUPTS \
(~(INT_MASK(INT_PERF_COUNT)))
#endif
(~((_AC(1,ULL) << INT_PERF_COUNT) | (_AC(1,ULL) << INT_AUX_PERF_COUNT)))
#if CHIP_HAS_SPLIT_INTR_MASK()
/* The same macro, but for the two 32-bit SPRs separately. */
#define LINUX_MASKABLE_INTERRUPTS_LO (-1)
#define LINUX_MASKABLE_INTERRUPTS_HI \
(~((1 << (INT_PERF_COUNT - 32)) | (1 << (INT_AUX_PERF_COUNT - 32))))
#endif
#ifndef __ASSEMBLY__
@ -126,7 +114,7 @@
* to know our current state.
*/
DECLARE_PER_CPU(unsigned long long, interrupts_enabled_mask);
#define INITIAL_INTERRUPTS_ENABLED INT_MASK(INT_MEM_ERROR)
#define INITIAL_INTERRUPTS_ENABLED (1ULL << INT_MEM_ERROR)
/* Disable interrupts. */
#define arch_local_irq_disable() \
@ -165,7 +153,7 @@ DECLARE_PER_CPU(unsigned long long, interrupts_enabled_mask);
/* Prevent the given interrupt from being enabled next time we enable irqs. */
#define arch_local_irq_mask(interrupt) \
(__get_cpu_var(interrupts_enabled_mask) &= ~INT_MASK(interrupt))
(__get_cpu_var(interrupts_enabled_mask) &= ~(1ULL << (interrupt)))
/* Prevent the given interrupt from being enabled immediately. */
#define arch_local_irq_mask_now(interrupt) do { \
@ -175,7 +163,7 @@ DECLARE_PER_CPU(unsigned long long, interrupts_enabled_mask);
/* Allow the given interrupt to be enabled next time we enable irqs. */
#define arch_local_irq_unmask(interrupt) \
(__get_cpu_var(interrupts_enabled_mask) |= INT_MASK(interrupt))
(__get_cpu_var(interrupts_enabled_mask) |= (1ULL << (interrupt)))
/* Allow the given interrupt to be enabled immediately, if !irqs_disabled. */
#define arch_local_irq_unmask_now(interrupt) do { \
@ -250,7 +238,7 @@ DECLARE_PER_CPU(unsigned long long, interrupts_enabled_mask);
/* Disable interrupts. */
#define IRQ_DISABLE(tmp0, tmp1) \
{ \
movei tmp0, -1; \
movei tmp0, LINUX_MASKABLE_INTERRUPTS_LO; \
moveli tmp1, lo16(LINUX_MASKABLE_INTERRUPTS_HI) \
}; \
{ \

394
arch/tile/include/uapi/arch/interrupts_32.h
View File

@ -15,6 +15,7 @@
#ifndef __ARCH_INTERRUPTS_H__
#define __ARCH_INTERRUPTS_H__
#ifndef __KERNEL__
/** Mask for an interrupt. */
/* Note: must handle breaking interrupts into high and low words manually. */
#define INT_MASK_LO(intno) (1 << (intno))
@ -23,6 +24,7 @@
#ifndef __ASSEMBLER__
#define INT_MASK(intno) (1ULL << (intno))
#endif
#endif
/** Where a given interrupt executes */
@ -92,216 +94,216 @@
#ifndef __ASSEMBLER__
#define QUEUED_INTERRUPTS ( \
INT_MASK(INT_MEM_ERROR) | \
INT_MASK(INT_DMATLB_MISS) | \
INT_MASK(INT_DMATLB_ACCESS) | \
INT_MASK(INT_SNITLB_MISS) | \
INT_MASK(INT_SN_NOTIFY) | \
INT_MASK(INT_SN_FIREWALL) | \
INT_MASK(INT_IDN_FIREWALL) | \
INT_MASK(INT_UDN_FIREWALL) | \
INT_MASK(INT_TILE_TIMER) | \
INT_MASK(INT_IDN_TIMER) | \
INT_MASK(INT_UDN_TIMER) | \
INT_MASK(INT_DMA_NOTIFY) | \
INT_MASK(INT_IDN_CA) | \
INT_MASK(INT_UDN_CA) | \
INT_MASK(INT_IDN_AVAIL) | \
INT_MASK(INT_UDN_AVAIL) | \
INT_MASK(INT_PERF_COUNT) | \
INT_MASK(INT_INTCTRL_3) | \
INT_MASK(INT_INTCTRL_2) | \
INT_MASK(INT_INTCTRL_1) | \
INT_MASK(INT_INTCTRL_0) | \
INT_MASK(INT_BOOT_ACCESS) | \
INT_MASK(INT_WORLD_ACCESS) | \
INT_MASK(INT_I_ASID) | \
INT_MASK(INT_D_ASID) | \
INT_MASK(INT_DMA_ASID) | \
INT_MASK(INT_SNI_ASID) | \
INT_MASK(INT_DMA_CPL) | \
INT_MASK(INT_SN_CPL) | \
INT_MASK(INT_DOUBLE_FAULT) | \
INT_MASK(INT_AUX_PERF_COUNT) | \
(1ULL << INT_MEM_ERROR) | \
(1ULL << INT_DMATLB_MISS) | \
(1ULL << INT_DMATLB_ACCESS) | \
(1ULL << INT_SNITLB_MISS) | \
(1ULL << INT_SN_NOTIFY) | \
(1ULL << INT_SN_FIREWALL) | \
(1ULL << INT_IDN_FIREWALL) | \
(1ULL << INT_UDN_FIREWALL) | \
(1ULL << INT_TILE_TIMER) | \
(1ULL << INT_IDN_TIMER) | \
(1ULL << INT_UDN_TIMER) | \
(1ULL << INT_DMA_NOTIFY) | \
(1ULL << INT_IDN_CA) | \
(1ULL << INT_UDN_CA) | \
(1ULL << INT_IDN_AVAIL) | \
(1ULL << INT_UDN_AVAIL) | \
(1ULL << INT_PERF_COUNT) | \
(1ULL << INT_INTCTRL_3) | \
(1ULL << INT_INTCTRL_2) | \
(1ULL << INT_INTCTRL_1) | \
(1ULL << INT_INTCTRL_0) | \
(1ULL << INT_BOOT_ACCESS) | \
(1ULL << INT_WORLD_ACCESS) | \
(1ULL << INT_I_ASID) | \
(1ULL << INT_D_ASID) | \
(1ULL << INT_DMA_ASID) | \
(1ULL << INT_SNI_ASID) | \
(1ULL << INT_DMA_CPL) | \
(1ULL << INT_SN_CPL) | \
(1ULL << INT_DOUBLE_FAULT) | \
(1ULL << INT_AUX_PERF_COUNT) | \
0)
#define NONQUEUED_INTERRUPTS ( \
INT_MASK(INT_ITLB_MISS) | \
INT_MASK(INT_ILL) | \
INT_MASK(INT_GPV) | \
INT_MASK(INT_SN_ACCESS) | \
INT_MASK(INT_IDN_ACCESS) | \
INT_MASK(INT_UDN_ACCESS) | \
INT_MASK(INT_IDN_REFILL) | \
INT_MASK(INT_UDN_REFILL) | \
INT_MASK(INT_IDN_COMPLETE) | \
INT_MASK(INT_UDN_COMPLETE) | \
INT_MASK(INT_SWINT_3) | \
INT_MASK(INT_SWINT_2) | \
INT_MASK(INT_SWINT_1) | \
INT_MASK(INT_SWINT_0) | \
INT_MASK(INT_UNALIGN_DATA) | \
INT_MASK(INT_DTLB_MISS) | \
INT_MASK(INT_DTLB_ACCESS) | \
INT_MASK(INT_SN_STATIC_ACCESS) | \
(1ULL << INT_ITLB_MISS) | \
(1ULL << INT_ILL) | \
(1ULL << INT_GPV) | \
(1ULL << INT_SN_ACCESS) | \
(1ULL << INT_IDN_ACCESS) | \
(1ULL << INT_UDN_ACCESS) | \
(1ULL << INT_IDN_REFILL) | \
(1ULL << INT_UDN_REFILL) | \
(1ULL << INT_IDN_COMPLETE) | \
(1ULL << INT_UDN_COMPLETE) | \
(1ULL << INT_SWINT_3) | \
(1ULL << INT_SWINT_2) | \
(1ULL << INT_SWINT_1) | \
(1ULL << INT_SWINT_0) | \
(1ULL << INT_UNALIGN_DATA) | \
(1ULL << INT_DTLB_MISS) | \
(1ULL << INT_DTLB_ACCESS) | \
(1ULL << INT_SN_STATIC_ACCESS) | \
0)
#define CRITICAL_MASKED_INTERRUPTS ( \
INT_MASK(INT_MEM_ERROR) | \
INT_MASK(INT_DMATLB_MISS) | \
INT_MASK(INT_DMATLB_ACCESS) | \
INT_MASK(INT_SNITLB_MISS) | \
INT_MASK(INT_SN_NOTIFY) | \
INT_MASK(INT_SN_FIREWALL) | \
INT_MASK(INT_IDN_FIREWALL) | \
INT_MASK(INT_UDN_FIREWALL) | \
INT_MASK(INT_TILE_TIMER) | \
INT_MASK(INT_IDN_TIMER) | \
INT_MASK(INT_UDN_TIMER) | \
INT_MASK(INT_DMA_NOTIFY) | \
INT_MASK(INT_IDN_CA) | \
INT_MASK(INT_UDN_CA) | \
INT_MASK(INT_IDN_AVAIL) | \
INT_MASK(INT_UDN_AVAIL) | \
INT_MASK(INT_PERF_COUNT) | \
INT_MASK(INT_INTCTRL_3) | \
INT_MASK(INT_INTCTRL_2) | \
INT_MASK(INT_INTCTRL_1) | \
INT_MASK(INT_INTCTRL_0) | \
INT_MASK(INT_AUX_PERF_COUNT) | \
(1ULL << INT_MEM_ERROR) | \
(1ULL << INT_DMATLB_MISS) | \
(1ULL << INT_DMATLB_ACCESS) | \
(1ULL << INT_SNITLB_MISS) | \
(1ULL << INT_SN_NOTIFY) | \
(1ULL << INT_SN_FIREWALL) | \
(1ULL << INT_IDN_FIREWALL) | \
(1ULL << INT_UDN_FIREWALL) | \
(1ULL << INT_TILE_TIMER) | \
(1ULL << INT_IDN_TIMER) | \
(1ULL << INT_UDN_TIMER) | \
(1ULL << INT_DMA_NOTIFY) | \
(1ULL << INT_IDN_CA) | \
(1ULL << INT_UDN_CA) | \
(1ULL << INT_IDN_AVAIL) | \
(1ULL << INT_UDN_AVAIL) | \
(1ULL << INT_PERF_COUNT) | \
(1ULL << INT_INTCTRL_3) | \
(1ULL << INT_INTCTRL_2) | \
(1ULL << INT_INTCTRL_1) | \
(1ULL << INT_INTCTRL_0) | \
(1ULL << INT_AUX_PERF_COUNT) | \
0)
#define CRITICAL_UNMASKED_INTERRUPTS ( \
INT_MASK(INT_ITLB_MISS) | \
INT_MASK(INT_ILL) | \
INT_MASK(INT_GPV) | \
INT_MASK(INT_SN_ACCESS) | \
INT_MASK(INT_IDN_ACCESS) | \
INT_MASK(INT_UDN_ACCESS) | \
INT_MASK(INT_IDN_REFILL) | \
INT_MASK(INT_UDN_REFILL) | \
INT_MASK(INT_IDN_COMPLETE) | \
INT_MASK(INT_UDN_COMPLETE) | \
INT_MASK(INT_SWINT_3) | \
INT_MASK(INT_SWINT_2) | \
INT_MASK(INT_SWINT_1) | \
INT_MASK(INT_SWINT_0) | \
INT_MASK(INT_UNALIGN_DATA) | \
INT_MASK(INT_DTLB_MISS) | \
INT_MASK(INT_DTLB_ACCESS) | \
INT_MASK(INT_BOOT_ACCESS) | \
INT_MASK(INT_WORLD_ACCESS) | \
INT_MASK(INT_I_ASID) | \
INT_MASK(INT_D_ASID) | \
INT_MASK(INT_DMA_ASID) | \
INT_MASK(INT_SNI_ASID) | \
INT_MASK(INT_DMA_CPL) | \
INT_MASK(INT_SN_CPL) | \
INT_MASK(INT_DOUBLE_FAULT) | \
INT_MASK(INT_SN_STATIC_ACCESS) | \
(1ULL << INT_ITLB_MISS) | \
(1ULL << INT_ILL) | \
(1ULL << INT_GPV) | \
(1ULL << INT_SN_ACCESS) | \
(1ULL << INT_IDN_ACCESS) | \
(1ULL << INT_UDN_ACCESS) | \
(1ULL << INT_IDN_REFILL) | \
(1ULL << INT_UDN_REFILL) | \
(1ULL << INT_IDN_COMPLETE) | \
(1ULL << INT_UDN_COMPLETE) | \
(1ULL << INT_SWINT_3) | \
(1ULL << INT_SWINT_2) | \
(1ULL << INT_SWINT_1) | \
(1ULL << INT_SWINT_0) | \
(1ULL << INT_UNALIGN_DATA) | \
(1ULL << INT_DTLB_MISS) | \
(1ULL << INT_DTLB_ACCESS) | \
(1ULL << INT_BOOT_ACCESS) | \
(1ULL << INT_WORLD_ACCESS) | \
(1ULL << INT_I_ASID) | \
(1ULL << INT_D_ASID) | \
(1ULL << INT_DMA_ASID) | \
(1ULL << INT_SNI_ASID) | \
(1ULL << INT_DMA_CPL) | \
(1ULL << INT_SN_CPL) | \
(1ULL << INT_DOUBLE_FAULT) | \
(1ULL << INT_SN_STATIC_ACCESS) | \
0)
#define MASKABLE_INTERRUPTS ( \
INT_MASK(INT_MEM_ERROR) | \
INT_MASK(INT_IDN_REFILL) | \
INT_MASK(INT_UDN_REFILL) | \
INT_MASK(INT_IDN_COMPLETE) | \
INT_MASK(INT_UDN_COMPLETE) | \
INT_MASK(INT_DMATLB_MISS) | \
INT_MASK(INT_DMATLB_ACCESS) | \
INT_MASK(INT_SNITLB_MISS) | \
INT_MASK(INT_SN_NOTIFY) | \
INT_MASK(INT_SN_FIREWALL) | \
INT_MASK(INT_IDN_FIREWALL) | \
INT_MASK(INT_UDN_FIREWALL) | \
INT_MASK(INT_TILE_TIMER) | \
INT_MASK(INT_IDN_TIMER) | \
INT_MASK(INT_UDN_TIMER) | \
INT_MASK(INT_DMA_NOTIFY) | \
INT_MASK(INT_IDN_CA) | \
INT_MASK(INT_UDN_CA) | \
INT_MASK(INT_IDN_AVAIL) | \
INT_MASK(INT_UDN_AVAIL) | \
INT_MASK(INT_PERF_COUNT) | \
INT_MASK(INT_INTCTRL_3) | \
INT_MASK(INT_INTCTRL_2) | \
INT_MASK(INT_INTCTRL_1) | \
INT_MASK(INT_INTCTRL_0) | \
INT_MASK(INT_AUX_PERF_COUNT) | \
(1ULL << INT_MEM_ERROR) | \
(1ULL << INT_IDN_REFILL) | \
(1ULL << INT_UDN_REFILL) | \
(1ULL << INT_IDN_COMPLETE) | \
(1ULL << INT_UDN_COMPLETE) | \
(1ULL << INT_DMATLB_MISS) | \
(1ULL << INT_DMATLB_ACCESS) | \
(1ULL << INT_SNITLB_MISS) | \
(1ULL << INT_SN_NOTIFY) | \
(1ULL << INT_SN_FIREWALL) | \
(1ULL << INT_IDN_FIREWALL) | \
(1ULL << INT_UDN_FIREWALL) | \
(1ULL << INT_TILE_TIMER) | \
(1ULL << INT_IDN_TIMER) | \
(1ULL << INT_UDN_TIMER) | \
(1ULL << INT_DMA_NOTIFY) | \
(1ULL << INT_IDN_CA) | \
(1ULL << INT_UDN_CA) | \
(1ULL << INT_IDN_AVAIL) | \
(1ULL << INT_UDN_AVAIL) | \
(1ULL << INT_PERF_COUNT) | \
(1ULL << INT_INTCTRL_3) | \
(1ULL << INT_INTCTRL_2) | \
(1ULL << INT_INTCTRL_1) | \
(1ULL << INT_INTCTRL_0) | \
(1ULL << INT_AUX_PERF_COUNT) | \
0)
#define UNMASKABLE_INTERRUPTS ( \
INT_MASK(INT_ITLB_MISS) | \
INT_MASK(INT_ILL) | \
INT_MASK(INT_GPV) | \
INT_MASK(INT_SN_ACCESS) | \
INT_MASK(INT_IDN_ACCESS) | \
INT_MASK(INT_UDN_ACCESS) | \
INT_MASK(INT_SWINT_3) | \
INT_MASK(INT_SWINT_2) | \
INT_MASK(INT_SWINT_1) | \
INT_MASK(INT_SWINT_0) | \
INT_MASK(INT_UNALIGN_DATA) | \
INT_MASK(INT_DTLB_MISS) | \
INT_MASK(INT_DTLB_ACCESS) | \
INT_MASK(INT_BOOT_ACCESS) | \
INT_MASK(INT_WORLD_ACCESS) | \
INT_MASK(INT_I_ASID) | \
INT_MASK(INT_D_ASID) | \
INT_MASK(INT_DMA_ASID) | \
INT_MASK(INT_SNI_ASID) | \
INT_MASK(INT_DMA_CPL) | \
INT_MASK(INT_SN_CPL) | \
INT_MASK(INT_DOUBLE_FAULT) | \
INT_MASK(INT_SN_STATIC_ACCESS) | \
(1ULL << INT_ITLB_MISS) | \
(1ULL << INT_ILL) | \
(1ULL << INT_GPV) | \
(1ULL << INT_SN_ACCESS) | \
(1ULL << INT_IDN_ACCESS) | \
(1ULL << INT_UDN_ACCESS) | \
(1ULL << INT_SWINT_3) | \
(1ULL << INT_SWINT_2) | \
(1ULL << INT_SWINT_1) | \
(1ULL << INT_SWINT_0) | \
(1ULL << INT_UNALIGN_DATA) | \
(1ULL << INT_DTLB_MISS) | \
(1ULL << INT_DTLB_ACCESS) | \
(1ULL << INT_BOOT_ACCESS) | \
(1ULL << INT_WORLD_ACCESS) | \
(1ULL << INT_I_ASID) | \
(1ULL << INT_D_ASID) | \
(1ULL << INT_DMA_ASID) | \
(1ULL << INT_SNI_ASID) | \
(1ULL << INT_DMA_CPL) | \
(1ULL << INT_SN_CPL) | \
(1ULL << INT_DOUBLE_FAULT) | \
(1ULL << INT_SN_STATIC_ACCESS) | \
0)
#define SYNC_INTERRUPTS ( \
INT_MASK(INT_ITLB_MISS) | \
INT_MASK(INT_ILL) | \
INT_MASK(INT_GPV) | \
INT_MASK(INT_SN_ACCESS) | \
INT_MASK(INT_IDN_ACCESS) | \
INT_MASK(INT_UDN_ACCESS) | \
INT_MASK(INT_IDN_REFILL) | \
INT_MASK(INT_UDN_REFILL) | \
INT_MASK(INT_IDN_COMPLETE) | \
INT_MASK(INT_UDN_COMPLETE) | \
INT_MASK(INT_SWINT_3) | \
INT_MASK(INT_SWINT_2) | \
INT_MASK(INT_SWINT_1) | \
INT_MASK(INT_SWINT_0) | \
INT_MASK(INT_UNALIGN_DATA) | \
INT_MASK(INT_DTLB_MISS) | \
INT_MASK(INT_DTLB_ACCESS) | \
INT_MASK(INT_SN_STATIC_ACCESS) | \
(1ULL << INT_ITLB_MISS) | \
(1ULL << INT_ILL) | \
(1ULL << INT_GPV) | \
(1ULL << INT_SN_ACCESS) | \
(1ULL << INT_IDN_ACCESS) | \
(1ULL << INT_UDN_ACCESS) | \
(1ULL << INT_IDN_REFILL) | \
(1ULL << INT_UDN_REFILL) | \
(1ULL << INT_IDN_COMPLETE) | \
(1ULL << INT_UDN_COMPLETE) | \
(1ULL << INT_SWINT_3) | \
(1ULL << INT_SWINT_2) | \
(1ULL << INT_SWINT_1) | \
(1ULL << INT_SWINT_0) | \
(1ULL << INT_UNALIGN_DATA) | \
(1ULL << INT_DTLB_MISS) | \
(1ULL << INT_DTLB_ACCESS) | \
(1ULL << INT_SN_STATIC_ACCESS) | \
0)
#define NON_SYNC_INTERRUPTS ( \
INT_MASK(INT_MEM_ERROR) | \
INT_MASK(INT_DMATLB_MISS) | \
INT_MASK(INT_DMATLB_ACCESS) | \
INT_MASK(INT_SNITLB_MISS) | \
INT_MASK(INT_SN_NOTIFY) | \
INT_MASK(INT_SN_FIREWALL) | \
INT_MASK(INT_IDN_FIREWALL) | \
INT_MASK(INT_UDN_FIREWALL) | \
INT_MASK(INT_TILE_TIMER) | \
INT_MASK(INT_IDN_TIMER) | \
INT_MASK(INT_UDN_TIMER) | \
INT_MASK(INT_DMA_NOTIFY) | \
INT_MASK(INT_IDN_CA) | \
INT_MASK(INT_UDN_CA) | \
INT_MASK(INT_IDN_AVAIL) | \
INT_MASK(INT_UDN_AVAIL) | \
INT_MASK(INT_PERF_COUNT) | \
INT_MASK(INT_INTCTRL_3) | \
INT_MASK(INT_INTCTRL_2) | \
INT_MASK(INT_INTCTRL_1) | \
INT_MASK(INT_INTCTRL_0) | \
INT_MASK(INT_BOOT_ACCESS) | \
INT_MASK(INT_WORLD_ACCESS) | \
INT_MASK(INT_I_ASID) | \
INT_MASK(INT_D_ASID) | \
INT_MASK(INT_DMA_ASID) | \
INT_MASK(INT_SNI_ASID) | \
INT_MASK(INT_DMA_CPL) | \
INT_MASK(INT_SN_CPL) | \
INT_MASK(INT_DOUBLE_FAULT) | \
INT_MASK(INT_AUX_PERF_COUNT) | \
(1ULL << INT_MEM_ERROR) | \
(1ULL << INT_DMATLB_MISS) | \
(1ULL << INT_DMATLB_ACCESS) | \
(1ULL << INT_SNITLB_MISS) | \
(1ULL << INT_SN_NOTIFY) | \
(1ULL << INT_SN_FIREWALL) | \
(1ULL << INT_IDN_FIREWALL) | \
(1ULL << INT_UDN_FIREWALL) | \
(1ULL << INT_TILE_TIMER) | \
(1ULL << INT_IDN_TIMER) | \
(1ULL << INT_UDN_TIMER) | \
(1ULL << INT_DMA_NOTIFY) | \
(1ULL << INT_IDN_CA) | \
(1ULL << INT_UDN_CA) | \
(1ULL << INT_IDN_AVAIL) | \
(1ULL << INT_UDN_AVAIL) | \
(1ULL << INT_PERF_COUNT) | \
(1ULL << INT_INTCTRL_3) | \
(1ULL << INT_INTCTRL_2) | \
(1ULL << INT_INTCTRL_1) | \
(1ULL << INT_INTCTRL_0) | \
(1ULL << INT_BOOT_ACCESS) | \
(1ULL << INT_WORLD_ACCESS) | \
(1ULL << INT_I_ASID) | \
(1ULL << INT_D_ASID) | \
(1ULL << INT_DMA_ASID) | \
(1ULL << INT_SNI_ASID) | \
(1ULL << INT_DMA_CPL) | \
(1ULL << INT_SN_CPL) | \
(1ULL << INT_DOUBLE_FAULT) | \
(1ULL << INT_AUX_PERF_COUNT) | \
0)
#endif /* !__ASSEMBLER__ */
#endif /* !__ARCH_INTERRUPTS_H__ */

346
arch/tile/include/uapi/arch/interrupts_64.h
View File

@ -15,6 +15,7 @@
#ifndef __ARCH_INTERRUPTS_H__
#define __ARCH_INTERRUPTS_H__
#ifndef __KERNEL__
/** Mask for an interrupt. */
#ifdef __ASSEMBLER__
/* Note: must handle breaking interrupts into high and low words manually. */
@ -22,6 +23,7 @@
#else
#define INT_MASK(intno) (1ULL << (intno))
#endif
#endif
/** Where a given interrupt executes */
@ -85,192 +87,192 @@
#ifndef __ASSEMBLER__
#define QUEUED_INTERRUPTS ( \
INT_MASK(INT_MEM_ERROR) | \
INT_MASK(INT_IDN_COMPLETE) | \
INT_MASK(INT_UDN_COMPLETE) | \
INT_MASK(INT_IDN_FIREWALL) | \
INT_MASK(INT_UDN_FIREWALL) | \
INT_MASK(INT_TILE_TIMER) | \
INT_MASK(INT_AUX_TILE_TIMER) | \
INT_MASK(INT_IDN_TIMER) | \
INT_MASK(INT_UDN_TIMER) | \
INT_MASK(INT_IDN_AVAIL) | \
INT_MASK(INT_UDN_AVAIL) | \
INT_MASK(INT_IPI_3) | \
INT_MASK(INT_IPI_2) | \
INT_MASK(INT_IPI_1) | \
INT_MASK(INT_IPI_0) | \
INT_MASK(INT_PERF_COUNT) | \
INT_MASK(INT_AUX_PERF_COUNT) | \
INT_MASK(INT_INTCTRL_3) | \
INT_MASK(INT_INTCTRL_2) | \
INT_MASK(INT_INTCTRL_1) | \
INT_MASK(INT_INTCTRL_0) | \
INT_MASK(INT_BOOT_ACCESS) | \
INT_MASK(INT_WORLD_ACCESS) | \
INT_MASK(INT_I_ASID) | \
INT_MASK(INT_D_ASID) | \
INT_MASK(INT_DOUBLE_FAULT) | \
(1ULL << INT_MEM_ERROR) | \
(1ULL << INT_IDN_COMPLETE) | \
(1ULL << INT_UDN_COMPLETE) | \
(1ULL << INT_IDN_FIREWALL) | \
(1ULL << INT_UDN_FIREWALL) | \
(1ULL << INT_TILE_TIMER) | \
(1ULL << INT_AUX_TILE_TIMER) | \
(1ULL << INT_IDN_TIMER) | \
(1ULL << INT_UDN_TIMER) | \
(1ULL << INT_IDN_AVAIL) | \
(1ULL << INT_UDN_AVAIL) | \
(1ULL << INT_IPI_3) | \
(1ULL << INT_IPI_2) | \
(1ULL << INT_IPI_1) | \
(1ULL << INT_IPI_0) | \
(1ULL << INT_PERF_COUNT) | \
(1ULL << INT_AUX_PERF_COUNT) | \
(1ULL << INT_INTCTRL_3) | \
(1ULL << INT_INTCTRL_2) | \
(1ULL << INT_INTCTRL_1) | \
(1ULL << INT_INTCTRL_0) | \
(1ULL << INT_BOOT_ACCESS) | \
(1ULL << INT_WORLD_ACCESS) | \
(1ULL << INT_I_ASID) | \
(1ULL << INT_D_ASID) | \
(1ULL << INT_DOUBLE_FAULT) | \
0)
#define NONQUEUED_INTERRUPTS ( \
INT_MASK(INT_SINGLE_STEP_3) | \
INT_MASK(INT_SINGLE_STEP_2) | \
INT_MASK(INT_SINGLE_STEP_1) | \
INT_MASK(INT_SINGLE_STEP_0) | \
INT_MASK(INT_ITLB_MISS) | \
INT_MASK(INT_ILL) | \
INT_MASK(INT_GPV) | \
INT_MASK(INT_IDN_ACCESS) | \
INT_MASK(INT_UDN_ACCESS) | \
INT_MASK(INT_SWINT_3) | \
INT_MASK(INT_SWINT_2) | \
INT_MASK(INT_SWINT_1) | \
INT_MASK(INT_SWINT_0) | \
INT_MASK(INT_ILL_TRANS) | \
INT_MASK(INT_UNALIGN_DATA) | \
INT_MASK(INT_DTLB_MISS) | \
INT_MASK(INT_DTLB_ACCESS) | \
(1ULL << INT_SINGLE_STEP_3) | \
(1ULL << INT_SINGLE_STEP_2) | \
(1ULL << INT_SINGLE_STEP_1) | \
(1ULL << INT_SINGLE_STEP_0) | \
(1ULL << INT_ITLB_MISS) | \
(1ULL << INT_ILL) | \
(1ULL << INT_GPV) | \
(1ULL << INT_IDN_ACCESS) | \
(1ULL << INT_UDN_ACCESS) | \
(1ULL << INT_SWINT_3) | \
(1ULL << INT_SWINT_2) | \
(1ULL << INT_SWINT_1) | \
(1ULL << INT_SWINT_0) | \
(1ULL << INT_ILL_TRANS) | \
(1ULL << INT_UNALIGN_DATA) | \
(1ULL << INT_DTLB_MISS) | \
(1ULL << INT_DTLB_ACCESS) | \
0)
#define CRITICAL_MASKED_INTERRUPTS ( \
INT_MASK(INT_MEM_ERROR) | \
INT_MASK(INT_SINGLE_STEP_3) | \
INT_MASK(INT_SINGLE_STEP_2) | \
INT_MASK(INT_SINGLE_STEP_1) | \
INT_MASK(INT_SINGLE_STEP_0) | \
INT_MASK(INT_IDN_COMPLETE) | \
INT_MASK(INT_UDN_COMPLETE) | \
INT_MASK(INT_IDN_FIREWALL) | \
INT_MASK(INT_UDN_FIREWALL) | \
INT_MASK(INT_TILE_TIMER) | \
INT_MASK(INT_AUX_TILE_TIMER) | \
INT_MASK(INT_IDN_TIMER) | \
INT_MASK(INT_UDN_TIMER) | \
INT_MASK(INT_IDN_AVAIL) | \
INT_MASK(INT_UDN_AVAIL) | \
INT_MASK(INT_IPI_3) | \
INT_MASK(INT_IPI_2) | \
INT_MASK(INT_IPI_1) | \
INT_MASK(INT_IPI_0) | \
INT_MASK(INT_PERF_COUNT) | \
INT_MASK(INT_AUX_PERF_COUNT) | \
INT_MASK(INT_INTCTRL_3) | \
INT_MASK(INT_INTCTRL_2) | \
INT_MASK(INT_INTCTRL_1) | \
INT_MASK(INT_INTCTRL_0) | \
(1ULL << INT_MEM_ERROR) | \
(1ULL << INT_SINGLE_STEP_3) | \
(1ULL << INT_SINGLE_STEP_2) | \
(1ULL << INT_SINGLE_STEP_1) | \
(1ULL << INT_SINGLE_STEP_0) | \
(1ULL << INT_IDN_COMPLETE) | \
(1ULL << INT_UDN_COMPLETE) | \
(1ULL << INT_IDN_FIREWALL) | \
(1ULL << INT_UDN_FIREWALL) | \
(1ULL << INT_TILE_TIMER) | \
(1ULL << INT_AUX_TILE_TIMER) | \
(1ULL << INT_IDN_TIMER) | \
(1ULL << INT_UDN_TIMER) | \
(1ULL << INT_IDN_AVAIL) | \
(1ULL << INT_UDN_AVAIL) | \
(1ULL << INT_IPI_3) | \
(1ULL << INT_IPI_2) | \
(1ULL << INT_IPI_1) | \
(1ULL << INT_IPI_0) | \
(1ULL << INT_PERF_COUNT) | \
(1ULL << INT_AUX_PERF_COUNT) | \
(1ULL << INT_INTCTRL_3) | \
(1ULL << INT_INTCTRL_2) | \
(1ULL << INT_INTCTRL_1) | \
(1ULL << INT_INTCTRL_0) | \
0)
#define CRITICAL_UNMASKED_INTERRUPTS ( \
INT_MASK(INT_ITLB_MISS) | \
INT_MASK(INT_ILL) | \
INT_MASK(INT_GPV) | \
INT_MASK(INT_IDN_ACCESS) | \
INT_MASK(INT_UDN_ACCESS) | \
INT_MASK(INT_SWINT_3) | \
INT_MASK(INT_SWINT_2) | \
INT_MASK(INT_SWINT_1) | \
INT_MASK(INT_SWINT_0) | \
INT_MASK(INT_ILL_TRANS) | \
INT_MASK(INT_UNALIGN_DATA) | \
INT_MASK(INT_DTLB_MISS) | \
INT_MASK(INT_DTLB_ACCESS) | \
INT_MASK(INT_BOOT_ACCESS) | \
INT_MASK(INT_WORLD_ACCESS) | \
INT_MASK(INT_I_ASID) | \
INT_MASK(INT_D_ASID) | \
INT_MASK(INT_DOUBLE_FAULT) | \
(1ULL << INT_ITLB_MISS) | \
(1ULL << INT_ILL) | \
(1ULL << INT_GPV) | \
(1ULL << INT_IDN_ACCESS) | \
(1ULL << INT_UDN_ACCESS) | \
(1ULL << INT_SWINT_3) | \
(1ULL << INT_SWINT_2) | \
(1ULL << INT_SWINT_1) | \
(1ULL << INT_SWINT_0) | \
(1ULL << INT_ILL_TRANS) | \
(1ULL << INT_UNALIGN_DATA) | \
(1ULL << INT_DTLB_MISS) | \
(1ULL << INT_DTLB_ACCESS) | \
(1ULL << INT_BOOT_ACCESS) | \
(1ULL << INT_WORLD_ACCESS) | \
(1ULL << INT_I_ASID) | \
(1ULL << INT_D_ASID) | \
(1ULL << INT_DOUBLE_FAULT) | \
0)
#define MASKABLE_INTERRUPTS ( \
INT_MASK(INT_MEM_ERROR) | \
INT_MASK(INT_SINGLE_STEP_3) | \
INT_MASK(INT_SINGLE_STEP_2) | \
INT_MASK(INT_SINGLE_STEP_1) | \
INT_MASK(INT_SINGLE_STEP_0) | \
INT_MASK(INT_IDN_COMPLETE) | \
INT_MASK(INT_UDN_COMPLETE) | \
INT_MASK(INT_IDN_FIREWALL) | \
INT_MASK(INT_UDN_FIREWALL) | \
INT_MASK(INT_TILE_TIMER) | \
INT_MASK(INT_AUX_TILE_TIMER) | \
INT_MASK(INT_IDN_TIMER) | \
INT_MASK(INT_UDN_TIMER) | \
INT_MASK(INT_IDN_AVAIL) | \
INT_MASK(INT_UDN_AVAIL) | \
INT_MASK(INT_IPI_3) | \
INT_MASK(INT_IPI_2) | \
INT_MASK(INT_IPI_1) | \
INT_MASK(INT_IPI_0) | \
INT_MASK(INT_PERF_COUNT) | \
INT_MASK(INT_AUX_PERF_COUNT) | \
INT_MASK(INT_INTCTRL_3) | \
INT_MASK(INT_INTCTRL_2) | \
INT_MASK(INT_INTCTRL_1) | \
INT_MASK(INT_INTCTRL_0) | \
(1ULL << INT_MEM_ERROR) | \
(1ULL << INT_SINGLE_STEP_3) | \
(1ULL << INT_SINGLE_STEP_2) | \
(1ULL << INT_SINGLE_STEP_1) | \
(1ULL << INT_SINGLE_STEP_0) | \
(1ULL << INT_IDN_COMPLETE) | \
(1ULL << INT_UDN_COMPLETE) | \
(1ULL << INT_IDN_FIREWALL) | \
(1ULL << INT_UDN_FIREWALL) | \
(1ULL << INT_TILE_TIMER) | \
(1ULL << INT_AUX_TILE_TIMER) | \
(1ULL << INT_IDN_TIMER) | \
(1ULL << INT_UDN_TIMER) | \
(1ULL << INT_IDN_AVAIL) | \
(1ULL << INT_UDN_AVAIL) | \
(1ULL << INT_IPI_3) | \
(1ULL << INT_IPI_2) | \
(1ULL << INT_IPI_1) | \
(1ULL << INT_IPI_0) | \
(1ULL << INT_PERF_COUNT) | \
(1ULL << INT_AUX_PERF_COUNT) | \
(1ULL << INT_INTCTRL_3) | \
(1ULL << INT_INTCTRL_2) | \
(1ULL << INT_INTCTRL_1) | \
(1ULL << INT_INTCTRL_0) | \
0)
#define UNMASKABLE_INTERRUPTS ( \
INT_MASK(INT_ITLB_MISS) | \
INT_MASK(INT_ILL) | \
INT_MASK(INT_GPV) | \
INT_MASK(INT_IDN_ACCESS) | \
INT_MASK(INT_UDN_ACCESS) | \
INT_MASK(INT_SWINT_3) | \
INT_MASK(INT_SWINT_2) | \
INT_MASK(INT_SWINT_1) | \
INT_MASK(INT_SWINT_0) | \
INT_MASK(INT_ILL_TRANS) | \
INT_MASK(INT_UNALIGN_DATA) | \
INT_MASK(INT_DTLB_MISS) | \
INT_MASK(INT_DTLB_ACCESS) | \
INT_MASK(INT_BOOT_ACCESS) | \
INT_MASK(INT_WORLD_ACCESS) | \
INT_MASK(INT_I_ASID) | \
INT_MASK(INT_D_ASID) | \
INT_MASK(INT_DOUBLE_FAULT) | \
(1ULL << INT_ITLB_MISS) | \
(1ULL << INT_ILL) | \
(1ULL << INT_GPV) | \
(1ULL << INT_IDN_ACCESS) | \
(1ULL << INT_UDN_ACCESS) | \
(1ULL << INT_SWINT_3) | \
(1ULL << INT_SWINT_2) | \
(1ULL << INT_SWINT_1) | \
(1ULL << INT_SWINT_0) | \
(1ULL << INT_ILL_TRANS) | \
(1ULL << INT_UNALIGN_DATA) | \
(1ULL << INT_DTLB_MISS) | \
(1ULL << INT_DTLB_ACCESS) | \
(1ULL << INT_BOOT_ACCESS) | \
(1ULL << INT_WORLD_ACCESS) | \
(1ULL << INT_I_ASID) | \
(1ULL << INT_D_ASID) | \
(1ULL << INT_DOUBLE_FAULT) | \
0)
#define SYNC_INTERRUPTS ( \
INT_MASK(INT_SINGLE_STEP_3) | \
INT_MASK(INT_SINGLE_STEP_2) | \
INT_MASK(INT_SINGLE_STEP_1) | \
INT_MASK(INT_SINGLE_STEP_0) | \
INT_MASK(INT_IDN_COMPLETE) | \
INT_MASK(INT_UDN_COMPLETE) | \
INT_MASK(INT_ITLB_MISS) | \
INT_MASK(INT_ILL) | \
INT_MASK(INT_GPV) | \
INT_MASK(INT_IDN_ACCESS) | \
INT_MASK(INT_UDN_ACCESS) | \
INT_MASK(INT_SWINT_3) | \
INT_MASK(INT_SWINT_2) | \
INT_MASK(INT_SWINT_1) | \
INT_MASK(INT_SWINT_0) | \
INT_MASK(INT_ILL_TRANS) | \
INT_MASK(INT_UNALIGN_DATA) | \
INT_MASK(INT_DTLB_MISS) | \
INT_MASK(INT_DTLB_ACCESS) | \
(1ULL << INT_SINGLE_STEP_3) | \
(1ULL << INT_SINGLE_STEP_2) | \
(1ULL << INT_SINGLE_STEP_1) | \
(1ULL << INT_SINGLE_STEP_0) | \
(1ULL << INT_IDN_COMPLETE) | \
(1ULL << INT_UDN_COMPLETE) | \
(1ULL << INT_ITLB_MISS) | \
(1ULL << INT_ILL) | \
(1ULL << INT_GPV) | \
(1ULL << INT_IDN_ACCESS) | \
(1ULL << INT_UDN_ACCESS) | \
(1ULL << INT_SWINT_3) | \
(1ULL << INT_SWINT_2) | \
(1ULL << INT_SWINT_1) | \
(1ULL << INT_SWINT_0) | \
(1ULL << INT_ILL_TRANS) | \
(1ULL << INT_UNALIGN_DATA) | \
(1ULL << INT_DTLB_MISS) | \
(1ULL << INT_DTLB_ACCESS) | \
0)
#define NON_SYNC_INTERRUPTS ( \
INT_MASK(INT_MEM_ERROR) | \
INT_MASK(INT_IDN_FIREWALL) | \
INT_MASK(INT_UDN_FIREWALL) | \
INT_MASK(INT_TILE_TIMER) | \
INT_MASK(INT_AUX_TILE_TIMER) | \
INT_MASK(INT_IDN_TIMER) | \
INT_MASK(INT_UDN_TIMER) | \
INT_MASK(INT_IDN_AVAIL) | \
INT_MASK(INT_UDN_AVAIL) | \
INT_MASK(INT_IPI_3) | \
INT_MASK(INT_IPI_2) | \
INT_MASK(INT_IPI_1) | \
INT_MASK(INT_IPI_0) | \
INT_MASK(INT_PERF_COUNT) | \
INT_MASK(INT_AUX_PERF_COUNT) | \
INT_MASK(INT_INTCTRL_3) | \
INT_MASK(INT_INTCTRL_2) | \
INT_MASK(INT_INTCTRL_1) | \
INT_MASK(INT_INTCTRL_0) | \
INT_MASK(INT_BOOT_ACCESS) | \
INT_MASK(INT_WORLD_ACCESS) | \
INT_MASK(INT_I_ASID) | \
INT_MASK(INT_D_ASID) | \
INT_MASK(INT_DOUBLE_FAULT) | \
(1ULL << INT_MEM_ERROR) | \
(1ULL << INT_IDN_FIREWALL) | \
(1ULL << INT_UDN_FIREWALL) | \
(1ULL << INT_TILE_TIMER) | \
(1ULL << INT_AUX_TILE_TIMER) | \
(1ULL << INT_IDN_TIMER) | \
(1ULL << INT_UDN_TIMER) | \
(1ULL << INT_IDN_AVAIL) | \
(1ULL << INT_UDN_AVAIL) | \
(1ULL << INT_IPI_3) | \
(1ULL << INT_IPI_2) | \
(1ULL << INT_IPI_1) | \
(1ULL << INT_IPI_0) | \
(1ULL << INT_PERF_COUNT) | \
(1ULL << INT_AUX_PERF_COUNT) | \
(1ULL << INT_INTCTRL_3) | \
(1ULL << INT_INTCTRL_2) | \
(1ULL << INT_INTCTRL_1) | \
(1ULL << INT_INTCTRL_0) | \
(1ULL << INT_BOOT_ACCESS) | \
(1ULL << INT_WORLD_ACCESS) | \
(1ULL << INT_I_ASID) | \
(1ULL << INT_D_ASID) | \
(1ULL << INT_DOUBLE_FAULT) | \
0)
#endif /* !__ASSEMBLER__ */
#endif /* !__ARCH_INTERRUPTS_H__ */

4
arch/tile/kernel/intvec_64.S
View File

@ -1035,7 +1035,9 @@ handle_syscall:
/* Ensure that the syscall number is within the legal range. */
{
moveli r20, hw2(sys_call_table)
#ifdef CONFIG_COMPAT
blbs r30, .Lcompat_syscall
#endif
}
{
cmpltu r21, TREG_SYSCALL_NR_NAME, r21
@ -1093,6 +1095,7 @@ handle_syscall:
j .Lresume_userspace /* jump into middle of interrupt_return */
}
#ifdef CONFIG_COMPAT
.Lcompat_syscall:
/*
* Load the base of the compat syscall table in r20, and
@ -1117,6 +1120,7 @@ handle_syscall:
{ move r15, r4; addxi r4, r4, 0 }
{ move r16, r5; addxi r5, r5, 0 }
j .Lload_syscall_pointer
#endif
.Linvalid_syscall:
/* Report an invalid syscall back to the user program */

2
arch/tile/kernel/process.c
View File

@ -159,7 +159,7 @@ static void save_arch_state(struct thread_struct *t);
int copy_thread(unsigned long clone_flags, unsigned long sp,
unsigned long arg, struct task_struct *p)
{
struct pt_regs *childregs = task_pt_regs(p), *regs = current_pt_regs();
struct pt_regs *childregs = task_pt_regs(p);
unsigned long ksp;
unsigned long *callee_regs;

2
arch/tile/kernel/reboot.c
View File

@ -16,6 +16,7 @@
#include <linux/reboot.h>
#include <linux/smp.h>
#include <linux/pm.h>
#include <linux/export.h>
#include <asm/page.h>
#include <asm/setup.h>
#include <hv/hypervisor.h>
@ -49,3 +50,4 @@ void machine_restart(char *cmd)
/* No interesting distinction to be made here. */
void (*pm_power_off)(void) = NULL;
EXPORT_SYMBOL(pm_power_off);

5
arch/tile/kernel/setup.c
View File

@ -31,6 +31,7 @@
#include <linux/timex.h>
#include <linux/hugetlb.h>
#include <linux/start_kernel.h>
#include <linux/screen_info.h>
#include <asm/setup.h>
#include <asm/sections.h>
#include <asm/cacheflush.h>
@ -49,6 +50,10 @@ static inline int ABS(int x) { return x >= 0 ? x : -x; }
/* Chip information */
char chip_model[64] __write_once;
#ifdef CONFIG_VT
struct screen_info screen_info;
#endif
struct pglist_data node_data[MAX_NUMNODES] __read_mostly;
EXPORT_SYMBOL(node_data);

3
arch/tile/kernel/stack.c
View File

@ -112,7 +112,7 @@ static struct pt_regs *valid_fault_handler(struct KBacktraceIterator* kbt)
p->pc, p->sp, p->ex1);
p = NULL;
}
if (!kbt->profile || (INT_MASK(p->faultnum) & QUEUED_INTERRUPTS) == 0)
if (!kbt->profile || ((1ULL << p->faultnum) & QUEUED_INTERRUPTS) == 0)
return p;
return NULL;
}
@ -484,6 +484,7 @@ void save_stack_trace(struct stack_trace *trace)
{
save_stack_trace_tsk(NULL, trace);
}
EXPORT_SYMBOL_GPL(save_stack_trace);
#endif

2
arch/tile/lib/cacheflush.c
View File

@ -12,6 +12,7 @@
* more details.
*/
#include <linux/export.h>
#include <asm/page.h>
#include <asm/cacheflush.h>
#include <arch/icache.h>
@ -165,3 +166,4 @@ void finv_buffer_remote(void *buffer, size_t size, int hfh)
__insn_mtspr(SPR_DSTREAM_PF, old_dstream_pf);
#endif
}
EXPORT_SYMBOL_GPL(finv_buffer_remote);

2
arch/tile/lib/cpumask.c
View File

@ -16,6 +16,7 @@
#include <linux/ctype.h>
#include <linux/errno.h>
#include <linux/smp.h>
#include <linux/export.h>
/*
* Allow cropping out bits beyond the end of the array.
@ -50,3 +51,4 @@ int bitmap_parselist_crop(const char *bp, unsigned long *maskp, int nmaskbits)
} while (*bp != '\0' && *bp != '\n');
return 0;
}
EXPORT_SYMBOL(bitmap_parselist_crop);

2
arch/tile/lib/exports.c
View File

@ -55,6 +55,8 @@ EXPORT_SYMBOL(hv_dev_poll_cancel);
EXPORT_SYMBOL(hv_dev_close);
EXPORT_SYMBOL(hv_sysconf);
EXPORT_SYMBOL(hv_confstr);
EXPORT_SYMBOL(hv_get_rtc);
EXPORT_SYMBOL(hv_set_rtc);
/* libgcc.a */
uint32_t __udivsi3(uint32_t dividend, uint32_t divisor);

1
arch/tile/mm/homecache.c
View File

@ -408,6 +408,7 @@ void homecache_change_page_home(struct page *page, int order, int home)
__set_pte(ptep, pte_set_home(pteval, home));
}
}
EXPORT_SYMBOL(homecache_change_page_home);
struct page *homecache_alloc_pages(gfp_t gfp_mask,
unsigned int order, int home)

84
arch/x86/include/asm/mce.h
View File

@ -3,6 +3,90 @@
#include <uapi/asm/mce.h>
/*
* Machine Check support for x86
*/
/* MCG_CAP register defines */
#define MCG_BANKCNT_MASK 0xff /* Number of Banks */
#define MCG_CTL_P (1ULL<<8) /* MCG_CTL register available */
#define MCG_EXT_P (1ULL<<9) /* Extended registers available */
#define MCG_CMCI_P (1ULL<<10) /* CMCI supported */
#define MCG_EXT_CNT_MASK 0xff0000 /* Number of Extended registers */
#define MCG_EXT_CNT_SHIFT 16
#define MCG_EXT_CNT(c) (((c) & MCG_EXT_CNT_MASK) >> MCG_EXT_CNT_SHIFT)
#define MCG_SER_P (1ULL<<24) /* MCA recovery/new status bits */
/* MCG_STATUS register defines */
#define MCG_STATUS_RIPV (1ULL<<0) /* restart ip valid */
#define MCG_STATUS_EIPV (1ULL<<1) /* ip points to correct instruction */
#define MCG_STATUS_MCIP (1ULL<<2) /* machine check in progress */
/* MCi_STATUS register defines */
#define MCI_STATUS_VAL (1ULL<<63) /* valid error */
#define MCI_STATUS_OVER (1ULL<<62) /* previous errors lost */
#define MCI_STATUS_UC (1ULL<<61) /* uncorrected error */
#define MCI_STATUS_EN (1ULL<<60) /* error enabled */
#define MCI_STATUS_MISCV (1ULL<<59) /* misc error reg. valid */
#define MCI_STATUS_ADDRV (1ULL<<58) /* addr reg. valid */
#define MCI_STATUS_PCC (1ULL<<57) /* processor context corrupt */
#define MCI_STATUS_S (1ULL<<56) /* Signaled machine check */
#define MCI_STATUS_AR (1ULL<<55) /* Action required */
#define MCACOD 0xffff /* MCA Error Code */
/* Architecturally defined codes from SDM Vol. 3B Chapter 15 */
#define MCACOD_SCRUB 0x00C0 /* 0xC0-0xCF Memory Scrubbing */
#define MCACOD_SCRUBMSK 0xfff0
#define MCACOD_L3WB 0x017A /* L3 Explicit Writeback */
#define MCACOD_DATA 0x0134 /* Data Load */
#define MCACOD_INSTR 0x0150 /* Instruction Fetch */
/* MCi_MISC register defines */
#define MCI_MISC_ADDR_LSB(m) ((m) & 0x3f)
#define MCI_MISC_ADDR_MODE(m) (((m) >> 6) & 7)
#define MCI_MISC_ADDR_SEGOFF 0 /* segment offset */
#define MCI_MISC_ADDR_LINEAR 1 /* linear address */
#define MCI_MISC_ADDR_PHYS 2 /* physical address */
#define MCI_MISC_ADDR_MEM 3 /* memory address */
#define MCI_MISC_ADDR_GENERIC 7 /* generic */
/* CTL2 register defines */
#define MCI_CTL2_CMCI_EN (1ULL << 30)
#define MCI_CTL2_CMCI_THRESHOLD_MASK 0x7fffULL
#define MCJ_CTX_MASK 3
#define MCJ_CTX(flags) ((flags) & MCJ_CTX_MASK)
#define MCJ_CTX_RANDOM 0 /* inject context: random */
#define MCJ_CTX_PROCESS 0x1 /* inject context: process */
#define MCJ_CTX_IRQ 0x2 /* inject context: IRQ */
#define MCJ_NMI_BROADCAST 0x4 /* do NMI broadcasting */
#define MCJ_EXCEPTION 0x8 /* raise as exception */
#define MCJ_IRQ_BRAODCAST 0x10 /* do IRQ broadcasting */
#define MCE_OVERFLOW 0 /* bit 0 in flags means overflow */
/* Software defined banks */
#define MCE_EXTENDED_BANK 128
#define MCE_THERMAL_BANK (MCE_EXTENDED_BANK + 0)
#define K8_MCE_THRESHOLD_BASE (MCE_EXTENDED_BANK + 1)
#define MCE_LOG_LEN 32
#define MCE_LOG_SIGNATURE "MACHINECHECK"
/*
* This structure contains all data related to the MCE log. Also
* carries a signature to make it easier to find from external
* debugging tools. Each entry is only valid when its finished flag
* is set.
*/
struct mce_log {
char signature[12]; /* "MACHINECHECK" */
unsigned len; /* = MCE_LOG_LEN */
unsigned next;
unsigned flags;
unsigned recordlen; /* length of struct mce */
struct mce entry[MCE_LOG_LEN];
};
struct mca_config {
bool dont_log_ce;

5
arch/x86/include/asm/pgtable.h
View File

@ -142,6 +142,11 @@ static inline unsigned long pmd_pfn(pmd_t pmd)
return (pmd_val(pmd) & PTE_PFN_MASK) >> PAGE_SHIFT;
}
static inline unsigned long pud_pfn(pud_t pud)
{
return (pud_val(pud) & PTE_PFN_MASK) >> PAGE_SHIFT;
}
#define pte_page(pte) pfn_to_page(pte_pfn(pte))
static inline int pmd_large(pmd_t pte)

87
arch/x86/include/uapi/asm/mce.h
View File

@ -4,66 +4,6 @@
#include <linux/types.h>
#include <asm/ioctls.h>
/*
* Machine Check support for x86
*/
/* MCG_CAP register defines */
#define MCG_BANKCNT_MASK 0xff /* Number of Banks */
#define MCG_CTL_P (1ULL<<8) /* MCG_CTL register available */
#define MCG_EXT_P (1ULL<<9) /* Extended registers available */
#define MCG_CMCI_P (1ULL<<10) /* CMCI supported */
#define MCG_EXT_CNT_MASK 0xff0000 /* Number of Extended registers */
#define MCG_EXT_CNT_SHIFT 16
#define MCG_EXT_CNT(c) (((c) & MCG_EXT_CNT_MASK) >> MCG_EXT_CNT_SHIFT)
#define MCG_SER_P (1ULL<<24) /* MCA recovery/new status bits */
/* MCG_STATUS register defines */
#define MCG_STATUS_RIPV (1ULL<<0) /* restart ip valid */
#define MCG_STATUS_EIPV (1ULL<<1) /* ip points to correct instruction */
#define MCG_STATUS_MCIP (1ULL<<2) /* machine check in progress */
/* MCi_STATUS register defines */
#define MCI_STATUS_VAL (1ULL<<63) /* valid error */
#define MCI_STATUS_OVER (1ULL<<62) /* previous errors lost */
#define MCI_STATUS_UC (1ULL<<61) /* uncorrected error */
#define MCI_STATUS_EN (1ULL<<60) /* error enabled */
#define MCI_STATUS_MISCV (1ULL<<59) /* misc error reg. valid */
#define MCI_STATUS_ADDRV (1ULL<<58) /* addr reg. valid */
#define MCI_STATUS_PCC (1ULL<<57) /* processor context corrupt */
#define MCI_STATUS_S (1ULL<<56) /* Signaled machine check */
#define MCI_STATUS_AR (1ULL<<55) /* Action required */
#define MCACOD 0xffff /* MCA Error Code */
/* Architecturally defined codes from SDM Vol. 3B Chapter 15 */
#define MCACOD_SCRUB 0x00C0 /* 0xC0-0xCF Memory Scrubbing */
#define MCACOD_SCRUBMSK 0xfff0
#define MCACOD_L3WB 0x017A /* L3 Explicit Writeback */
#define MCACOD_DATA 0x0134 /* Data Load */
#define MCACOD_INSTR 0x0150 /* Instruction Fetch */
/* MCi_MISC register defines */
#define MCI_MISC_ADDR_LSB(m) ((m) & 0x3f)
#define MCI_MISC_ADDR_MODE(m) (((m) >> 6) & 7)
#define MCI_MISC_ADDR_SEGOFF 0 /* segment offset */
#define MCI_MISC_ADDR_LINEAR 1 /* linear address */
#define MCI_MISC_ADDR_PHYS 2 /* physical address */
#define MCI_MISC_ADDR_MEM 3 /* memory address */
#define MCI_MISC_ADDR_GENERIC 7 /* generic */
/* CTL2 register defines */
#define MCI_CTL2_CMCI_EN (1ULL << 30)
#define MCI_CTL2_CMCI_THRESHOLD_MASK 0x7fffULL
#define MCJ_CTX_MASK 3
#define MCJ_CTX(flags) ((flags) & MCJ_CTX_MASK)
#define MCJ_CTX_RANDOM 0 /* inject context: random */
#define MCJ_CTX_PROCESS 0x1 /* inject context: process */
#define MCJ_CTX_IRQ 0x2 /* inject context: IRQ */
#define MCJ_NMI_BROADCAST 0x4 /* do NMI broadcasting */
#define MCJ_EXCEPTION 0x8 /* raise as exception */
#define MCJ_IRQ_BRAODCAST 0x10 /* do IRQ broadcasting */
/* Fields are zero when not available */
struct mce {
__u64 status;
@ -87,35 +27,8 @@ struct mce {
__u64 mcgcap; /* MCGCAP MSR: machine check capabilities of CPU */
};
/*
* This structure contains all data related to the MCE log. Also
* carries a signature to make it easier to find from external
* debugging tools. Each entry is only valid when its finished flag
* is set.
*/
#define MCE_LOG_LEN 32
struct mce_log {
char signature[12]; /* "MACHINECHECK" */
unsigned len; /* = MCE_LOG_LEN */
unsigned next;
unsigned flags;
unsigned recordlen; /* length of struct mce */
struct mce entry[MCE_LOG_LEN];
};
#define MCE_OVERFLOW 0 /* bit 0 in flags means overflow */
#define MCE_LOG_SIGNATURE "MACHINECHECK"
#define MCE_GET_RECORD_LEN _IOR('M', 1, int)
#define MCE_GET_LOG_LEN _IOR('M', 2, int)
#define MCE_GETCLEAR_FLAGS _IOR('M', 3, int)
/* Software defined banks */
#define MCE_EXTENDED_BANK 128
#define MCE_THERMAL_BANK MCE_EXTENDED_BANK + 0
#define K8_MCE_THRESHOLD_BASE (MCE_EXTENDED_BANK + 1)
#endif /* _UAPI_ASM_X86_MCE_H */

23
arch/x86/kernel/apic/x2apic_phys.c
View File

@ -20,18 +20,19 @@ static int set_x2apic_phys_mode(char *arg)
}
early_param("x2apic_phys", set_x2apic_phys_mode);
static bool x2apic_fadt_phys(void)
{
if ((acpi_gbl_FADT.header.revision >= FADT2_REVISION_ID) &&
(acpi_gbl_FADT.flags & ACPI_FADT_APIC_PHYSICAL)) {
printk(KERN_DEBUG "System requires x2apic physical mode\n");
return true;
}
return false;
}
static int x2apic_acpi_madt_oem_check(char *oem_id, char *oem_table_id)
{
if (x2apic_phys)
return x2apic_enabled();
else if ((acpi_gbl_FADT.header.revision >= FADT2_REVISION_ID) &&
(acpi_gbl_FADT.flags & ACPI_FADT_APIC_PHYSICAL) &&
x2apic_enabled()) {
printk(KERN_DEBUG "System requires x2apic physical mode\n");
return 1;
}
else
return 0;
return x2apic_enabled() && (x2apic_phys || x2apic_fadt_phys());
}
static void
@ -82,7 +83,7 @@ static void init_x2apic_ldr(void)
static int x2apic_phys_probe(void)
{
if (x2apic_mode && x2apic_phys)
if (x2apic_mode && (x2apic_phys || x2apic_fadt_phys()))
return 1;
return apic == &apic_x2apic_phys;

8
arch/x86/mm/fault.c
View File

@ -748,13 +748,15 @@ __bad_area_nosemaphore(struct pt_regs *regs, unsigned long error_code,
return;
}
#endif
/* Kernel addresses are always protection faults: */
if (address >= TASK_SIZE)
error_code |= PF_PROT;
if (unlikely(show_unhandled_signals))
if (likely(show_unhandled_signals))
show_signal_msg(regs, error_code, address, tsk);
/* Kernel addresses are always protection faults: */
tsk->thread.cr2 = address;
tsk->thread.error_code = error_code | (address >= TASK_SIZE);
tsk->thread.error_code = error_code;
tsk->thread.trap_nr = X86_TRAP_PF;
force_sig_info_fault(SIGSEGV, si_code, address, tsk, 0);

3
arch/x86/mm/init_64.c
View File

@ -831,6 +831,9 @@ int kern_addr_valid(unsigned long addr)
if (pud_none(*pud))
return 0;
if (pud_large(*pud))
return pfn_valid(pud_pfn(*pud));
pmd = pmd_offset(pud, addr);
if (pmd_none(*pmd))
return 0;

7
drivers/gpu/drm/nouveau/core/core/falcon.c
View File

@ -73,8 +73,11 @@ _nouveau_falcon_init(struct nouveau_object *object)
nv_debug(falcon, "data limit: %d\n", falcon->data.limit);
/* wait for 'uc halted' to be signalled before continuing */
if (falcon->secret) {
nv_wait(falcon, 0x008, 0x00000010, 0x00000010);
if (falcon->secret && falcon->version < 4) {
if (!falcon->version)
nv_wait(falcon, 0x008, 0x00000010, 0x00000010);
else
nv_wait(falcon, 0x180, 0x80000000, 0);
nv_wo32(falcon, 0x004, 0x00000010);
}

2
drivers/gpu/drm/nouveau/core/core/subdev.c
View File

@ -99,7 +99,7 @@ nouveau_subdev_create_(struct nouveau_object *parent,
if (ret)
return ret;
mutex_init(&subdev->mutex);
__mutex_init(&subdev->mutex, subname, &oclass->lock_class_key);
subdev->name = subname;
if (parent) {

7
drivers/gpu/drm/nouveau/core/include/core/object.h
View File

@ -50,10 +50,13 @@ int nouveau_object_fini(struct nouveau_object *, bool suspend);
extern struct nouveau_ofuncs nouveau_object_ofuncs;
/* Don't allocate dynamically, because lockdep needs lock_class_keys to be in
* ".data". */
struct nouveau_oclass {
u32 handle;
struct nouveau_ofuncs *ofuncs;
struct nouveau_omthds *omthds;
struct nouveau_ofuncs * const ofuncs;
struct nouveau_omthds * const omthds;
struct lock_class_key lock_class_key;
};
#define nv_oclass(o) nv_object(o)->oclass

4
drivers/gpu/drm/nouveau/core/subdev/fb/base.c
View File

@ -86,8 +86,8 @@ nouveau_fb_preinit(struct nouveau_fb *pfb)
return ret;
}
if (!nouveau_mm_initialised(&pfb->tags) && tags) {
ret = nouveau_mm_init(&pfb->tags, 0, ++tags, 1);
if (!nouveau_mm_initialised(&pfb->tags)) {
ret = nouveau_mm_init(&pfb->tags, 0, tags ? ++tags : 0, 1);
if (ret)
return ret;
}

5
drivers/gpu/drm/nouveau/core/subdev/fb/nv50.c
View File

@ -99,7 +99,7 @@ nv50_fb_vram_init(struct nouveau_fb *pfb)
struct nouveau_bios *bios = nouveau_bios(device);
const u32 rsvd_head = ( 256 * 1024) >> 12; /* vga memory */
const u32 rsvd_tail = (1024 * 1024) >> 12; /* vbios etc */
u32 size;
u32 size, tags = 0;
int ret;
pfb->ram.size = nv_rd32(pfb, 0x10020c);
@ -140,10 +140,11 @@ nv50_fb_vram_init(struct nouveau_fb *pfb)
return ret;
pfb->ram.ranks = (nv_rd32(pfb, 0x100200) & 0x4) ? 2 : 1;
tags = nv_rd32(pfb, 0x100320);
break;
}
return nv_rd32(pfb, 0x100320);
return tags;
}
static int

1
drivers/gpu/drm/nouveau/nouveau_bo.c
View File

@ -28,6 +28,7 @@
*/
#include <core/engine.h>
#include <linux/swiotlb.h>
#include <subdev/fb.h>
#include <subdev/vm.h>

3
drivers/gpu/drm/nouveau/nouveau_drm.c
View File

@ -245,6 +245,8 @@ static int nouveau_drm_probe(struct pci_dev *pdev,
return 0;
}
static struct lock_class_key drm_client_lock_class_key;
static int
nouveau_drm_load(struct drm_device *dev, unsigned long flags)
{
@ -256,6 +258,7 @@ nouveau_drm_load(struct drm_device *dev, unsigned long flags)
ret = nouveau_cli_create(pdev, "DRM", sizeof(*drm), (void**)&drm);
if (ret)
return ret;
lockdep_set_class(&drm->client.mutex, &drm_client_lock_class_key);
dev->dev_private = drm;
drm->dev = dev;

86
drivers/gpu/drm/radeon/evergreen_cs.c
View File

@ -2909,14 +2909,14 @@ int evergreen_dma_cs_parse(struct radeon_cs_parser *p)
return -EINVAL;
}
if (tiled) {
dst_offset = ib[idx+1];
dst_offset = radeon_get_ib_value(p, idx+1);
dst_offset <<= 8;
ib[idx+1] += (u32)(dst_reloc->lobj.gpu_offset >> 8);
p->idx += count + 7;
} else {
dst_offset = ib[idx+1];
dst_offset |= ((u64)(ib[idx+2] & 0xff)) << 32;
dst_offset = radeon_get_ib_value(p, idx+1);
dst_offset |= ((u64)(radeon_get_ib_value(p, idx+2) & 0xff)) << 32;
ib[idx+1] += (u32)(dst_reloc->lobj.gpu_offset & 0xfffffffc);
ib[idx+2] += upper_32_bits(dst_reloc->lobj.gpu_offset) & 0xff;
@ -2954,12 +2954,12 @@ int evergreen_dma_cs_parse(struct radeon_cs_parser *p)
DRM_ERROR("bad L2T, frame to fields DMA_PACKET_COPY\n");
return -EINVAL;
}
dst_offset = ib[idx+1];
dst_offset = radeon_get_ib_value(p, idx+1);
dst_offset <<= 8;
dst2_offset = ib[idx+2];
dst2_offset = radeon_get_ib_value(p, idx+2);
dst2_offset <<= 8;
src_offset = ib[idx+8];
src_offset |= ((u64)(ib[idx+9] & 0xff)) << 32;
src_offset = radeon_get_ib_value(p, idx+8);
src_offset |= ((u64)(radeon_get_ib_value(p, idx+9) & 0xff)) << 32;
if ((src_offset + (count * 4)) > radeon_bo_size(src_reloc->robj)) {
dev_warn(p->dev, "DMA L2T, frame to fields src buffer too small (%llu %lu)\n",
src_offset + (count * 4), radeon_bo_size(src_reloc->robj));
@ -3014,12 +3014,12 @@ int evergreen_dma_cs_parse(struct radeon_cs_parser *p)
DRM_ERROR("bad L2T, broadcast DMA_PACKET_COPY\n");
return -EINVAL;
}
dst_offset = ib[idx+1];
dst_offset = radeon_get_ib_value(p, idx+1);
dst_offset <<= 8;
dst2_offset = ib[idx+2];
dst2_offset = radeon_get_ib_value(p, idx+2);
dst2_offset <<= 8;
src_offset = ib[idx+8];
src_offset |= ((u64)(ib[idx+9] & 0xff)) << 32;
src_offset = radeon_get_ib_value(p, idx+8);
src_offset |= ((u64)(radeon_get_ib_value(p, idx+9) & 0xff)) << 32;
if ((src_offset + (count * 4)) > radeon_bo_size(src_reloc->robj)) {
dev_warn(p->dev, "DMA L2T, broadcast src buffer too small (%llu %lu)\n",
src_offset + (count * 4), radeon_bo_size(src_reloc->robj));
@ -3046,22 +3046,22 @@ int evergreen_dma_cs_parse(struct radeon_cs_parser *p)
/* detile bit */
if (idx_value & (1 << 31)) {
/* tiled src, linear dst */
src_offset = ib[idx+1];
src_offset = radeon_get_ib_value(p, idx+1);
src_offset <<= 8;
ib[idx+1] += (u32)(src_reloc->lobj.gpu_offset >> 8);
dst_offset = ib[idx+7];
dst_offset |= ((u64)(ib[idx+8] & 0xff)) << 32;
dst_offset = radeon_get_ib_value(p, idx+7);
dst_offset |= ((u64)(radeon_get_ib_value(p, idx+8) & 0xff)) << 32;
ib[idx+7] += (u32)(dst_reloc->lobj.gpu_offset & 0xfffffffc);
ib[idx+8] += upper_32_bits(dst_reloc->lobj.gpu_offset) & 0xff;
} else {
/* linear src, tiled dst */
src_offset = ib[idx+7];
src_offset |= ((u64)(ib[idx+8] & 0xff)) << 32;
src_offset = radeon_get_ib_value(p, idx+7);
src_offset |= ((u64)(radeon_get_ib_value(p, idx+8) & 0xff)) << 32;
ib[idx+7] += (u32)(src_reloc->lobj.gpu_offset & 0xfffffffc);
ib[idx+8] += upper_32_bits(src_reloc->lobj.gpu_offset) & 0xff;
dst_offset = ib[idx+1];
dst_offset = radeon_get_ib_value(p, idx+1);
dst_offset <<= 8;
ib[idx+1] += (u32)(dst_reloc->lobj.gpu_offset >> 8);
}
@ -3098,12 +3098,12 @@ int evergreen_dma_cs_parse(struct radeon_cs_parser *p)
DRM_ERROR("bad L2T, broadcast DMA_PACKET_COPY\n");
return -EINVAL;
}
dst_offset = ib[idx+1];
dst_offset = radeon_get_ib_value(p, idx+1);
dst_offset <<= 8;
dst2_offset = ib[idx+2];
dst2_offset = radeon_get_ib_value(p, idx+2);
dst2_offset <<= 8;
src_offset = ib[idx+8];
src_offset |= ((u64)(ib[idx+9] & 0xff)) << 32;
src_offset = radeon_get_ib_value(p, idx+8);
src_offset |= ((u64)(radeon_get_ib_value(p, idx+9) & 0xff)) << 32;
if ((src_offset + (count * 4)) > radeon_bo_size(src_reloc->robj)) {
dev_warn(p->dev, "DMA L2T, broadcast src buffer too small (%llu %lu)\n",
src_offset + (count * 4), radeon_bo_size(src_reloc->robj));
@ -3135,22 +3135,22 @@ int evergreen_dma_cs_parse(struct radeon_cs_parser *p)
/* detile bit */
if (idx_value & (1 << 31)) {
/* tiled src, linear dst */
src_offset = ib[idx+1];
src_offset = radeon_get_ib_value(p, idx+1);
src_offset <<= 8;
ib[idx+1] += (u32)(src_reloc->lobj.gpu_offset >> 8);
dst_offset = ib[idx+7];
dst_offset |= ((u64)(ib[idx+8] & 0xff)) << 32;
dst_offset = radeon_get_ib_value(p, idx+7);
dst_offset |= ((u64)(radeon_get_ib_value(p, idx+8) & 0xff)) << 32;
ib[idx+7] += (u32)(dst_reloc->lobj.gpu_offset & 0xfffffffc);
ib[idx+8] += upper_32_bits(dst_reloc->lobj.gpu_offset) & 0xff;
} else {
/* linear src, tiled dst */
src_offset = ib[idx+7];
src_offset |= ((u64)(ib[idx+8] & 0xff)) << 32;
src_offset = radeon_get_ib_value(p, idx+7);
src_offset |= ((u64)(radeon_get_ib_value(p, idx+8) & 0xff)) << 32;
ib[idx+7] += (u32)(src_reloc->lobj.gpu_offset & 0xfffffffc);
ib[idx+8] += upper_32_bits(src_reloc->lobj.gpu_offset) & 0xff;
dst_offset = ib[idx+1];
dst_offset = radeon_get_ib_value(p, idx+1);
dst_offset <<= 8;
ib[idx+1] += (u32)(dst_reloc->lobj.gpu_offset >> 8);
}
@ -3176,10 +3176,10 @@ int evergreen_dma_cs_parse(struct radeon_cs_parser *p)
switch (misc) {
case 0:
/* L2L, byte */
src_offset = ib[idx+2];
src_offset |= ((u64)(ib[idx+4] & 0xff)) << 32;
dst_offset = ib[idx+1];
dst_offset |= ((u64)(ib[idx+3] & 0xff)) << 32;
src_offset = radeon_get_ib_value(p, idx+2);
src_offset |= ((u64)(radeon_get_ib_value(p, idx+4) & 0xff)) << 32;
dst_offset = radeon_get_ib_value(p, idx+1);
dst_offset |= ((u64)(radeon_get_ib_value(p, idx+3) & 0xff)) << 32;
if ((src_offset + count) > radeon_bo_size(src_reloc->robj)) {
dev_warn(p->dev, "DMA L2L, byte src buffer too small (%llu %lu)\n",
src_offset + count, radeon_bo_size(src_reloc->robj));
@ -3216,12 +3216,12 @@ int evergreen_dma_cs_parse(struct radeon_cs_parser *p)
DRM_ERROR("bad L2L, dw, broadcast DMA_PACKET_COPY\n");
return -EINVAL;
}
dst_offset = ib[idx+1];
dst_offset |= ((u64)(ib[idx+4] & 0xff)) << 32;
dst2_offset = ib[idx+2];
dst2_offset |= ((u64)(ib[idx+5] & 0xff)) << 32;
src_offset = ib[idx+3];
src_offset |= ((u64)(ib[idx+6] & 0xff)) << 32;
dst_offset = radeon_get_ib_value(p, idx+1);
dst_offset |= ((u64)(radeon_get_ib_value(p, idx+4) & 0xff)) << 32;
dst2_offset = radeon_get_ib_value(p, idx+2);
dst2_offset |= ((u64)(radeon_get_ib_value(p, idx+5) & 0xff)) << 32;
src_offset = radeon_get_ib_value(p, idx+3);
src_offset |= ((u64)(radeon_get_ib_value(p, idx+6) & 0xff)) << 32;
if ((src_offset + (count * 4)) > radeon_bo_size(src_reloc->robj)) {
dev_warn(p->dev, "DMA L2L, dw, broadcast src buffer too small (%llu %lu)\n",
src_offset + (count * 4), radeon_bo_size(src_reloc->robj));
@ -3251,10 +3251,10 @@ int evergreen_dma_cs_parse(struct radeon_cs_parser *p)
}
} else {
/* L2L, dw */
src_offset = ib[idx+2];
src_offset |= ((u64)(ib[idx+4] & 0xff)) << 32;
dst_offset = ib[idx+1];
dst_offset |= ((u64)(ib[idx+3] & 0xff)) << 32;
src_offset = radeon_get_ib_value(p, idx+2);
src_offset |= ((u64)(radeon_get_ib_value(p, idx+4) & 0xff)) << 32;
dst_offset = radeon_get_ib_value(p, idx+1);
dst_offset |= ((u64)(radeon_get_ib_value(p, idx+3) & 0xff)) << 32;
if ((src_offset + (count * 4)) > radeon_bo_size(src_reloc->robj)) {
dev_warn(p->dev, "DMA L2L, dw src buffer too small (%llu %lu)\n",
src_offset + (count * 4), radeon_bo_size(src_reloc->robj));
@ -3279,8 +3279,8 @@ int evergreen_dma_cs_parse(struct radeon_cs_parser *p)
DRM_ERROR("bad DMA_PACKET_CONSTANT_FILL\n");
return -EINVAL;
}
dst_offset = ib[idx+1];
dst_offset |= ((u64)(ib[idx+3] & 0x00ff0000)) << 16;
dst_offset = radeon_get_ib_value(p, idx+1);
dst_offset |= ((u64)(radeon_get_ib_value(p, idx+3) & 0x00ff0000)) << 16;
if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) {
dev_warn(p->dev, "DMA constant fill buffer too small (%llu %lu)\n",
dst_offset, radeon_bo_size(dst_reloc->robj));

38
drivers/gpu/drm/radeon/r600_cs.c
View File

@ -2623,14 +2623,14 @@ int r600_dma_cs_parse(struct radeon_cs_parser *p)
return -EINVAL;
}
if (tiled) {
dst_offset = ib[idx+1];
dst_offset = radeon_get_ib_value(p, idx+1);
dst_offset <<= 8;
ib[idx+1] += (u32)(dst_reloc->lobj.gpu_offset >> 8);
p->idx += count + 5;
} else {
dst_offset = ib[idx+1];
dst_offset |= ((u64)(ib[idx+2] & 0xff)) << 32;
dst_offset = radeon_get_ib_value(p, idx+1);
dst_offset |= ((u64)(radeon_get_ib_value(p, idx+2) & 0xff)) << 32;
ib[idx+1] += (u32)(dst_reloc->lobj.gpu_offset & 0xfffffffc);
ib[idx+2] += upper_32_bits(dst_reloc->lobj.gpu_offset) & 0xff;
@ -2658,32 +2658,32 @@ int r600_dma_cs_parse(struct radeon_cs_parser *p)
/* detile bit */
if (idx_value & (1 << 31)) {
/* tiled src, linear dst */
src_offset = ib[idx+1];
src_offset = radeon_get_ib_value(p, idx+1);
src_offset <<= 8;
ib[idx+1] += (u32)(src_reloc->lobj.gpu_offset >> 8);
dst_offset = ib[idx+5];
dst_offset |= ((u64)(ib[idx+6] & 0xff)) << 32;
dst_offset = radeon_get_ib_value(p, idx+5);
dst_offset |= ((u64)(radeon_get_ib_value(p, idx+6) & 0xff)) << 32;
ib[idx+5] += (u32)(dst_reloc->lobj.gpu_offset & 0xfffffffc);
ib[idx+6] += upper_32_bits(dst_reloc->lobj.gpu_offset) & 0xff;
} else {
/* linear src, tiled dst */
src_offset = ib[idx+5];
src_offset |= ((u64)(ib[idx+6] & 0xff)) << 32;
src_offset = radeon_get_ib_value(p, idx+5);
src_offset |= ((u64)(radeon_get_ib_value(p, idx+6) & 0xff)) << 32;
ib[idx+5] += (u32)(src_reloc->lobj.gpu_offset & 0xfffffffc);
ib[idx+6] += upper_32_bits(src_reloc->lobj.gpu_offset) & 0xff;
dst_offset = ib[idx+1];
dst_offset = radeon_get_ib_value(p, idx+1);
dst_offset <<= 8;
ib[idx+1] += (u32)(dst_reloc->lobj.gpu_offset >> 8);
}
p->idx += 7;
} else {
if (p->family >= CHIP_RV770) {
src_offset = ib[idx+2];
src_offset |= ((u64)(ib[idx+4] & 0xff)) << 32;
dst_offset = ib[idx+1];
dst_offset |= ((u64)(ib[idx+3] & 0xff)) << 32;
src_offset = radeon_get_ib_value(p, idx+2);
src_offset |= ((u64)(radeon_get_ib_value(p, idx+4) & 0xff)) << 32;
dst_offset = radeon_get_ib_value(p, idx+1);
dst_offset |= ((u64)(radeon_get_ib_value(p, idx+3) & 0xff)) << 32;
ib[idx+1] += (u32)(dst_reloc->lobj.gpu_offset & 0xfffffffc);
ib[idx+2] += (u32)(src_reloc->lobj.gpu_offset & 0xfffffffc);
@ -2691,10 +2691,10 @@ int r600_dma_cs_parse(struct radeon_cs_parser *p)
ib[idx+4] += upper_32_bits(src_reloc->lobj.gpu_offset) & 0xff;
p->idx += 5;
} else {
src_offset = ib[idx+2];
src_offset |= ((u64)(ib[idx+3] & 0xff)) << 32;
dst_offset = ib[idx+1];
dst_offset |= ((u64)(ib[idx+3] & 0xff0000)) << 16;
src_offset = radeon_get_ib_value(p, idx+2);
src_offset |= ((u64)(radeon_get_ib_value(p, idx+3) & 0xff)) << 32;
dst_offset = radeon_get_ib_value(p, idx+1);
dst_offset |= ((u64)(radeon_get_ib_value(p, idx+3) & 0xff0000)) << 16;
ib[idx+1] += (u32)(dst_reloc->lobj.gpu_offset & 0xfffffffc);
ib[idx+2] += (u32)(src_reloc->lobj.gpu_offset & 0xfffffffc);
@ -2724,8 +2724,8 @@ int r600_dma_cs_parse(struct radeon_cs_parser *p)
DRM_ERROR("bad DMA_PACKET_WRITE\n");
return -EINVAL;
}
dst_offset = ib[idx+1];
dst_offset |= ((u64)(ib[idx+3] & 0x00ff0000)) << 16;
dst_offset = radeon_get_ib_value(p, idx+1);
dst_offset |= ((u64)(radeon_get_ib_value(p, idx+3) & 0x00ff0000)) << 16;
if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) {
dev_warn(p->dev, "DMA constant fill buffer too small (%llu %lu)\n",
dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj));

1
drivers/gpu/drm/radeon/radeon_ttm.c
View File

@ -38,6 +38,7 @@
#include <drm/radeon_drm.h>
#include <linux/seq_file.h>
#include <linux/slab.h>
#include <linux/swiotlb.h>
#include "radeon_reg.h"
#include "radeon.h"

2
drivers/input/joystick/analog.c
View File

@ -162,7 +162,7 @@ static unsigned int get_time_pit(void)
#define GET_TIME(x) do { x = get_cycles(); } while (0)
#define DELTA(x,y) ((y)-(x))
#define TIME_NAME "PCC"
#elif defined(CONFIG_MN10300)
#elif defined(CONFIG_MN10300) || defined(CONFIG_TILE)
#define GET_TIME(x) do { x = get_cycles(); } while (0)
#define DELTA(x, y) ((x) - (y))
#define TIME_NAME "TSC"

71
drivers/net/ethernet/atheros/atl1c/atl1c_main.c
View File

@ -21,7 +21,7 @@
#include "atl1c.h"
#define ATL1C_DRV_VERSION "1.0.1.0-NAPI"
#define ATL1C_DRV_VERSION "1.0.1.1-NAPI"
char atl1c_driver_name[] = "atl1c";
char atl1c_driver_version[] = ATL1C_DRV_VERSION;
@ -1649,6 +1649,7 @@ static int atl1c_alloc_rx_buffer(struct atl1c_adapter *adapter)
u16 num_alloc = 0;
u16 rfd_next_to_use, next_next;
struct atl1c_rx_free_desc *rfd_desc;
dma_addr_t mapping;
next_next = rfd_next_to_use = rfd_ring->next_to_use;
if (++next_next == rfd_ring->count)
@ -1675,9 +1676,18 @@ static int atl1c_alloc_rx_buffer(struct atl1c_adapter *adapter)
ATL1C_SET_BUFFER_STATE(buffer_info, ATL1C_BUFFER_BUSY);
buffer_info->skb = skb;
buffer_info->length = adapter->rx_buffer_len;
buffer_info->dma = pci_map_single(pdev, vir_addr,
mapping = pci_map_single(pdev, vir_addr,
buffer_info->length,
PCI_DMA_FROMDEVICE);
if (unlikely(pci_dma_mapping_error(pdev, mapping))) {
dev_kfree_skb(skb);
buffer_info->skb = NULL;
buffer_info->length = 0;
ATL1C_SET_BUFFER_STATE(buffer_info, ATL1C_BUFFER_FREE);
netif_warn(adapter, rx_err, adapter->netdev, "RX pci_map_single failed");
break;
}
buffer_info->dma = mapping;
ATL1C_SET_PCIMAP_TYPE(buffer_info, ATL1C_PCIMAP_SINGLE,
ATL1C_PCIMAP_FROMDEVICE);
rfd_desc->buffer_addr = cpu_to_le64(buffer_info->dma);
@ -2012,7 +2022,29 @@ check_sum:
return 0;
}
static void atl1c_tx_map(struct atl1c_adapter *adapter,
static void atl1c_tx_rollback(struct atl1c_adapter *adpt,
struct atl1c_tpd_desc *first_tpd,
enum atl1c_trans_queue type)
{
struct atl1c_tpd_ring *tpd_ring = &adpt->tpd_ring[type];
struct atl1c_buffer *buffer_info;
struct atl1c_tpd_desc *tpd;
u16 first_index, index;
first_index = first_tpd - (struct atl1c_tpd_desc *)tpd_ring->desc;
index = first_index;
while (index != tpd_ring->next_to_use) {
tpd = ATL1C_TPD_DESC(tpd_ring, index);
buffer_info = &tpd_ring->buffer_info[index];
atl1c_clean_buffer(adpt->pdev, buffer_info, 0);
memset(tpd, 0, sizeof(struct atl1c_tpd_desc));
if (++index == tpd_ring->count)
index = 0;
}
tpd_ring->next_to_use = first_index;
}
static int atl1c_tx_map(struct atl1c_adapter *adapter,
struct sk_buff *skb, struct atl1c_tpd_desc *tpd,
enum atl1c_trans_queue type)
{
@ -2037,7 +2069,10 @@ static void atl1c_tx_map(struct atl1c_adapter *adapter,
buffer_info->length = map_len;
buffer_info->dma = pci_map_single(adapter->pdev,
skb->data, hdr_len, PCI_DMA_TODEVICE);
ATL1C_SET_BUFFER_STATE(buffer_info, ATL1C_BUFFER_BUSY);
if (unlikely(pci_dma_mapping_error(adapter->pdev,
buffer_info->dma)))
goto err_dma;
ATL1C_SET_PCIMAP_TYPE(buffer_info, ATL1C_PCIMAP_SINGLE,
ATL1C_PCIMAP_TODEVICE);
mapped_len += map_len;
@ -2059,6 +2094,10 @@ static void atl1c_tx_map(struct atl1c_adapter *adapter,
buffer_info->dma =
pci_map_single(adapter->pdev, skb->data + mapped_len,
buffer_info->length, PCI_DMA_TODEVICE);
if (unlikely(pci_dma_mapping_error(adapter->pdev,
buffer_info->dma)))
goto err_dma;
ATL1C_SET_BUFFER_STATE(buffer_info, ATL1C_BUFFER_BUSY);
ATL1C_SET_PCIMAP_TYPE(buffer_info, ATL1C_PCIMAP_SINGLE,
ATL1C_PCIMAP_TODEVICE);
@ -2080,6 +2119,9 @@ static void atl1c_tx_map(struct atl1c_adapter *adapter,
frag, 0,
buffer_info->length,
DMA_TO_DEVICE);
if (dma_mapping_error(&adapter->pdev->dev, buffer_info->dma))
goto err_dma;
ATL1C_SET_BUFFER_STATE(buffer_info, ATL1C_BUFFER_BUSY);
ATL1C_SET_PCIMAP_TYPE(buffer_info, ATL1C_PCIMAP_PAGE,
ATL1C_PCIMAP_TODEVICE);
@ -2092,6 +2134,13 @@ static void atl1c_tx_map(struct atl1c_adapter *adapter,
/* The last buffer info contain the skb address,
so it will be free after unmap */
buffer_info->skb = skb;
return 0;
err_dma:
buffer_info->dma = 0;
buffer_info->length = 0;
return -1;
}
static void atl1c_tx_queue(struct atl1c_adapter *adapter, struct sk_buff *skb,
@ -2154,10 +2203,18 @@ static netdev_tx_t atl1c_xmit_frame(struct sk_buff *skb,
if (skb_network_offset(skb) != ETH_HLEN)
tpd->word1 |= 1 << TPD_ETH_TYPE_SHIFT; /* Ethernet frame */
atl1c_tx_map(adapter, skb, tpd, type);
atl1c_tx_queue(adapter, skb, tpd, type);
if (atl1c_tx_map(adapter, skb, tpd, type) < 0) {
netif_info(adapter, tx_done, adapter->netdev,
"tx-skb droppted due to dma error\n");
/* roll back tpd/buffer */
atl1c_tx_rollback(adapter, tpd, type);
spin_unlock_irqrestore(&adapter->tx_lock, flags);
dev_kfree_skb(skb);
} else {
atl1c_tx_queue(adapter, skb, tpd, type);
spin_unlock_irqrestore(&adapter->tx_lock, flags);
}
spin_unlock_irqrestore(&adapter->tx_lock, flags);
return NETDEV_TX_OK;
}

5
drivers/net/ethernet/cadence/macb.c
View File

@ -693,6 +693,11 @@ static int macb_poll(struct napi_struct *napi, int budget)
* get notified when new packets arrive.
*/
macb_writel(bp, IER, MACB_RX_INT_FLAGS);
/* Packets received while interrupts were disabled */
status = macb_readl(bp, RSR);
if (unlikely(status))
napi_reschedule(napi);
}
/* TODO: Handle errors */

2
drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
View File

@ -2254,7 +2254,7 @@ static int __init stmmac_cmdline_opt(char *str)
} else if (!strncmp(opt, "pause:", 6)) {
if (kstrtoint(opt + 6, 0, &pause))
goto err;
} else if (!strncmp(opt, "eee_timer:", 6)) {
} else if (!strncmp(opt, "eee_timer:", 10)) {
if (kstrtoint(opt + 10, 0, &eee_timer))
goto err;
}

11
drivers/net/usb/cdc_ncm.c
View File

@ -576,9 +576,14 @@ static int cdc_ncm_bind(struct usbnet *dev, struct usb_interface *intf)
if ((intf->num_altsetting == 2) &&
!usb_set_interface(dev->udev,
intf->cur_altsetting->desc.bInterfaceNumber,
CDC_NCM_COMM_ALTSETTING_MBIM) &&
cdc_ncm_comm_intf_is_mbim(intf->cur_altsetting))
return -ENODEV;
CDC_NCM_COMM_ALTSETTING_MBIM)) {
if (cdc_ncm_comm_intf_is_mbim(intf->cur_altsetting))
return -ENODEV;
else
usb_set_interface(dev->udev,
intf->cur_altsetting->desc.bInterfaceNumber,
CDC_NCM_COMM_ALTSETTING_NCM);
}
#endif
/* NCM data altsetting is always 1 */

3
drivers/net/xen-netback/interface.c
View File

@ -132,6 +132,7 @@ static void xenvif_up(struct xenvif *vif)
static void xenvif_down(struct xenvif *vif)
{
disable_irq(vif->irq);
del_timer_sync(&vif->credit_timeout);
xen_netbk_deschedule_xenvif(vif);
xen_netbk_remove_xenvif(vif);
}
@ -365,8 +366,6 @@ void xenvif_disconnect(struct xenvif *vif)
atomic_dec(&vif->refcnt);
wait_event(vif->waiting_to_free, atomic_read(&vif->refcnt) == 0);
del_timer_sync(&vif->credit_timeout);
if (vif->irq)
unbind_from_irqhandler(vif->irq, vif);

8
drivers/net/xen-netback/netback.c
View File

@ -911,13 +911,13 @@ static int netbk_count_requests(struct xenvif *vif,
if (frags >= work_to_do) {
netdev_err(vif->dev, "Need more frags\n");
netbk_fatal_tx_err(vif);
return -frags;
return -ENODATA;
}
if (unlikely(frags >= MAX_SKB_FRAGS)) {
netdev_err(vif->dev, "Too many frags\n");
netbk_fatal_tx_err(vif);
return -frags;
return -E2BIG;
}
memcpy(txp, RING_GET_REQUEST(&vif->tx, cons + frags),
@ -925,7 +925,7 @@ static int netbk_count_requests(struct xenvif *vif,
if (txp->size > first->size) {
netdev_err(vif->dev, "Frag is bigger than frame.\n");
netbk_fatal_tx_err(vif);
return -frags;
return -EIO;
}
first->size -= txp->size;
@ -935,7 +935,7 @@ static int netbk_count_requests(struct xenvif *vif,
netdev_err(vif->dev, "txp->offset: %x, size: %u\n",
txp->offset, txp->size);
netbk_fatal_tx_err(vif);
return -frags;
return -EINVAL;
}
} while ((txp++)->flags & XEN_NETTXF_more_data);
return frags;

4
drivers/rtc/rtc-pl031.c
View File

@ -350,7 +350,9 @@ static int pl031_probe(struct amba_device *adev, const struct amba_id *id)
/* Enable the clockwatch on ST Variants */
if (vendor->clockwatch)
data |= RTC_CR_CWEN;
writel(data | RTC_CR_EN, ldata->base + RTC_CR);
else
data |= RTC_CR_EN;
writel(data, ldata->base + RTC_CR);
/*
* On ST PL031 variants, the RTC reset value does not provide correct

2
include/net/sock.h
View File

@ -1041,7 +1041,7 @@ static inline void sk_refcnt_debug_dec(struct sock *sk)
sk->sk_prot->name, sk, atomic_read(&sk->sk_prot->socks));
}
inline void sk_refcnt_debug_release(const struct sock *sk)
static inline void sk_refcnt_debug_release(const struct sock *sk)
{
if (atomic_read(&sk->sk_refcnt) != 1)
printk(KERN_DEBUG "Destruction of the %s socket %p delayed, refcnt=%d\n",

25
include/uapi/linux/auto_fs.h
View File

@ -28,25 +28,16 @@
#define AUTOFS_MIN_PROTO_VERSION AUTOFS_PROTO_VERSION
/*
* Architectures where both 32- and 64-bit binaries can be executed
* on 64-bit kernels need this. This keeps the structure format
* uniform, and makes sure the wait_queue_token isn't too big to be
* passed back down to the kernel.
*
* This assumes that on these architectures:
* mode 32 bit 64 bit
* -------------------------
* int 32 bit 32 bit
* long 32 bit 64 bit
*
* If so, 32-bit user-space code should be backwards compatible.
* The wait_queue_token (autofs_wqt_t) is part of a structure which is passed
* back to the kernel via ioctl from userspace. On architectures where 32- and
* 64-bit userspace binaries can be executed it's important that the size of
* autofs_wqt_t stays constant between 32- and 64-bit Linux kernels so that we
* do not break the binary ABI interface by changing the structure size.
*/
#if defined(__sparc__) || defined(__mips__) || defined(__x86_64__) \
|| defined(__powerpc__) || defined(__s390__)
typedef unsigned int autofs_wqt_t;
#else
#if defined(__ia64__) || defined(__alpha__) /* pure 64bit architectures */
typedef unsigned long autofs_wqt_t;
#else
typedef unsigned int autofs_wqt_t;
#endif
/* Packet types */

2
kernel/pid.c
View File

@ -331,7 +331,7 @@ out:
return pid;
out_unlock:
spin_unlock(&pidmap_lock);
spin_unlock_irq(&pidmap_lock);
out_free:
while (++i <= ns->level)
free_pidmap(pid->numbers + i);

4
mm/memcontrol.c
View File

@ -3030,7 +3030,9 @@ int memcg_register_cache(struct mem_cgroup *memcg, struct kmem_cache *s,
if (memcg) {
s->memcg_params->memcg = memcg;
s->memcg_params->root_cache = root_cache;
}
} else
s->memcg_params->is_root_cache = true;
return 0;
}

6
mm/mlock.c
View File

@ -517,11 +517,11 @@ SYSCALL_DEFINE2(munlock, unsigned long, start, size_t, len)
static int do_mlockall(int flags)
{
struct vm_area_struct * vma, * prev = NULL;
unsigned int def_flags = 0;
if (flags & MCL_FUTURE)
def_flags = VM_LOCKED;
current->mm->def_flags = def_flags;
current->mm->def_flags |= VM_LOCKED;
else
current->mm->def_flags &= ~VM_LOCKED;
if (flags == MCL_FUTURE)
goto out;

4
mm/page_alloc.c
View File

@ -773,6 +773,10 @@ void __init init_cma_reserved_pageblock(struct page *page)
set_pageblock_migratetype(page, MIGRATE_CMA);
__free_pages(page, pageblock_order);
totalram_pages += pageblock_nr_pages;
#ifdef CONFIG_HIGHMEM
if (PageHighMem(page))
totalhigh_pages += pageblock_nr_pages;
#endif
}
#endif

2
net/batman-adv/distributed-arp-table.c
View File

@ -440,7 +440,7 @@ static bool batadv_is_orig_node_eligible(struct batadv_dat_candidate *res,
/* this is an hash collision with the temporary selected node. Choose
* the one with the lowest address
*/
if ((tmp_max == max) &&
if ((tmp_max == max) && max_orig_node &&
(batadv_compare_eth(candidate->orig, max_orig_node->orig) > 0))
goto out;

6
net/ipv6/netfilter/nf_conntrack_reasm.c
View File

@ -97,9 +97,9 @@ static int nf_ct_frag6_sysctl_register(struct net *net)
if (table == NULL)
goto err_alloc;
table[0].data = &net->ipv6.frags.high_thresh;
table[1].data = &net->ipv6.frags.low_thresh;
table[2].data = &net->ipv6.frags.timeout;
table[0].data = &net->nf_frag.frags.timeout;
table[1].data = &net->nf_frag.frags.low_thresh;
table[2].data = &net->nf_frag.frags.high_thresh;
}
hdr = register_net_sysctl(net, "net/netfilter", table);

4
net/netfilter/nf_conntrack_helper.c
View File

@ -236,7 +236,9 @@ int __nf_ct_try_assign_helper(struct nf_conn *ct, struct nf_conn *tmpl,
/* We only allow helper re-assignment of the same sort since
* we cannot reallocate the helper extension area.
*/
if (help->helper != helper) {
struct nf_conntrack_helper *tmp = rcu_dereference(help->helper);
if (tmp && tmp->help != helper->help) {
RCU_INIT_POINTER(help->helper, NULL);
goto out;
}

3
net/netfilter/nf_conntrack_netlink.c
View File

@ -1782,6 +1782,9 @@ ctnetlink_new_conntrack(struct sock *ctnl, struct sk_buff *skb,
if (nlh->nlmsg_flags & NLM_F_CREATE) {
enum ip_conntrack_events events;
if (!cda[CTA_TUPLE_ORIG] || !cda[CTA_TUPLE_REPLY])
return -EINVAL;
ct = ctnetlink_create_conntrack(net, zone, cda, &otuple,
&rtuple, u3);
if (IS_ERR(ct))

4
net/sctp/Kconfig
View File

@ -3,8 +3,8 @@
#
menuconfig IP_SCTP
tristate "The SCTP Protocol (EXPERIMENTAL)"
depends on INET && EXPERIMENTAL
tristate "The SCTP Protocol"
depends on INET
depends on IPV6 || IPV6=n
select CRYPTO
select CRYPTO_HMAC

5
net/sctp/ipv6.c
View File

@ -326,9 +326,10 @@ static void sctp_v6_get_dst(struct sctp_transport *t, union sctp_addr *saddr,
*/
rcu_read_lock();
list_for_each_entry_rcu(laddr, &bp->address_list, list) {
if (!laddr->valid && laddr->state != SCTP_ADDR_SRC)
if (!laddr->valid)
continue;
if ((laddr->a.sa.sa_family == AF_INET6) &&
if ((laddr->state == SCTP_ADDR_SRC) &&
(laddr->a.sa.sa_family == AF_INET6) &&
(scope <= sctp_scope(&laddr->a))) {
bmatchlen = sctp_v6_addr_match_len(daddr, &laddr->a);
if (!baddr || (matchlen < bmatchlen)) {

1
net/tipc/bcast.c
View File

@ -774,6 +774,7 @@ void tipc_bclink_init(void)
bcl->owner = &bclink->node;
bcl->max_pkt = MAX_PKT_DEFAULT_MCAST;
tipc_link_set_queue_limits(bcl, BCLINK_WIN_DEFAULT);
spin_lock_init(&bcbearer->bearer.lock);
bcl->b_ptr = &bcbearer->bearer;
bcl->state = WORKING_WORKING;
strlcpy(bcl->name, tipc_bclink_name, TIPC_MAX_LINK_NAME);